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net/mlx5e: drop useless LIST_HEAD
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
f6dfb4c3 47#include <net/arp.h>
e8f887ac 48#include "en.h"
1d447a39 49#include "en_rep.h"
232c0013 50#include "en_tc.h"
03a9d11e 51#include "eswitch.h"
3f6d08d1 52#include "fs_core.h"
2c81bfd5 53#include "en/port.h"
101f4de9 54#include "en/tc_tun.h"
04de7dda 55#include "lib/devcom.h"
e8f887ac 56
3bc4b7bf
OG		 57struct mlx5_nic_flow_attr {
58 u32 action;
59 u32 flow_tag;
2f4fe4ca 60 u32 mod_hdr_id;
5c65c564 61 u32 hairpin_tirn;
38aa51c1 62 u8 match_level;
3f6d08d1 63 struct mlx5_flow_table *hairpin_ft;
b8aee822 64 struct mlx5_fc *counter;
3bc4b7bf
OG		 65};
66
60bd4af8
OG		 67#define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
68
65ba8fb7 69enum {
60bd4af8
OG		 70 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
71 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
d9ee0491
OG		 72 MLX5E_TC_FLOW_ESWITCH = MLX5E_TC_ESW_OFFLOAD,
73 MLX5E_TC_FLOW_NIC = MLX5E_TC_NIC_OFFLOAD,
74 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE),
75 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 1),
76 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 2),
77 MLX5E_TC_FLOW_SLOW = BIT(MLX5E_TC_FLOW_BASE + 3),
78 MLX5E_TC_FLOW_DUP = BIT(MLX5E_TC_FLOW_BASE + 4),
65ba8fb7
OG		 79};
80
e4ad91f2
CM		 81#define MLX5E_TC_MAX_SPLITS 1
82
79baaec7
EB		 83/* Helper struct for accessing a struct containing list_head array.
84 * Containing struct
85 * |- Helper array
86 * [0] Helper item 0
87 * |- list_head item 0
88 * |- index (0)
89 * [1] Helper item 1
90 * |- list_head item 1
91 * |- index (1)
92 * To access the containing struct from one of the list_head items:
93 * 1. Get the helper item from the list_head item using
94 * helper item =
95 * container_of(list_head item, helper struct type, list_head field)
96 * 2. Get the contining struct from the helper item and its index in the array:
97 * containing struct =
98 * container_of(helper item, containing struct type, helper field[index])
99 */
100struct encap_flow_item {
101 struct list_head list;
102 int index;
103};
104
e8f887ac
AV		 105struct mlx5e_tc_flow {
106 struct rhash_head node;
655dc3d2 107 struct mlx5e_priv *priv;
e8f887ac 108 u64 cookie;
5dbe906f 109 u16 flags;
e4ad91f2 110 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
79baaec7
EB		 111 /* Flow can be associated with multiple encap IDs.
112 * The number of encaps is bounded by the number of supported
113 * destinations.
114 */
115 struct encap_flow_item encaps[MLX5_MAX_FLOW_FWD_VPORTS];
04de7dda 116 struct mlx5e_tc_flow *peer_flow;
11c9c548 117 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 118 struct list_head hairpin; /* flows sharing the same hairpin */
04de7dda 119 struct list_head peer; /* flows with peer flow */
3bc4b7bf
OG		 120 union {
121 struct mlx5_esw_flow_attr esw_attr[0];
122 struct mlx5_nic_flow_attr nic_attr[0];
123 };
e8f887ac
AV		 124};
125
17091853 126struct mlx5e_tc_flow_parse_attr {
98b66cb1 127 struct ip_tunnel_info tun_info[MLX5_MAX_FLOW_FWD_VPORTS];
d11afc26 128 struct net_device *filter_dev;
17091853 129 struct mlx5_flow_spec spec;
d79b6df6
OG		 130 int num_mod_hdr_actions;
131 void *mod_hdr_actions;
98b66cb1 132 int mirred_ifindex[MLX5_MAX_FLOW_FWD_VPORTS];
17091853
OG		 133};
134
acff797c 135#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 136#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 137
77ab67b7
OG		 138struct mlx5e_hairpin {
139 struct mlx5_hairpin *pair;
140
141 struct mlx5_core_dev *func_mdev;
3f6d08d1 142 struct mlx5e_priv *func_priv;
77ab67b7
OG		 143 u32 tdn;
144 u32 tirn;
3f6d08d1
OG		 145
146 int num_channels;
147 struct mlx5e_rqt indir_rqt;
148 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
149 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 150};
151
5c65c564
OG		 152struct mlx5e_hairpin_entry {
153 /* a node of a hash table which keeps all the hairpin entries */
154 struct hlist_node hairpin_hlist;
155
156 /* flows sharing the same hairpin */
157 struct list_head flows;
158
d8822868 159 u16 peer_vhca_id;
106be53b 160 u8 prio;
5c65c564
OG		 161 struct mlx5e_hairpin *hp;
162};
163
11c9c548
OG		 164struct mod_hdr_key {
165 int num_actions;
166 void *actions;
167};
168
169struct mlx5e_mod_hdr_entry {
170 /* a node of a hash table which keeps all the mod_hdr entries */
171 struct hlist_node mod_hdr_hlist;
172
173 /* flows sharing the same mod_hdr entry */
174 struct list_head flows;
175
176 struct mod_hdr_key key;
177
178 u32 mod_hdr_id;
179};
180
181#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
182
183static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
184{
185 return jhash(key->actions,
186 key->num_actions * MLX5_MH_ACT_SZ, 0);
187}
188
189static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
190 struct mod_hdr_key *b)
191{
192 if (a->num_actions != b->num_actions)
193 return 1;
194
195 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
196}
197
198static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
199 struct mlx5e_tc_flow *flow,
200 struct mlx5e_tc_flow_parse_attr *parse_attr)
201{
202 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
203 int num_actions, actions_size, namespace, err;
204 struct mlx5e_mod_hdr_entry *mh;
205 struct mod_hdr_key key;
206 bool found = false;
207 u32 hash_key;
208
209 num_actions = parse_attr->num_mod_hdr_actions;
210 actions_size = MLX5_MH_ACT_SZ * num_actions;
211
212 key.actions = parse_attr->mod_hdr_actions;
213 key.num_actions = num_actions;
214
215 hash_key = hash_mod_hdr_info(&key);
216
217 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
218 namespace = MLX5_FLOW_NAMESPACE_FDB;
219 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
220 mod_hdr_hlist, hash_key) {
221 if (!cmp_mod_hdr_info(&mh->key, &key)) {
222 found = true;
223 break;
224 }
225 }
226 } else {
227 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
228 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
229 mod_hdr_hlist, hash_key) {
230 if (!cmp_mod_hdr_info(&mh->key, &key)) {
231 found = true;
232 break;
233 }
234 }
235 }
236
237 if (found)
238 goto attach_flow;
239
240 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
241 if (!mh)
242 return -ENOMEM;
243
244 mh->key.actions = (void *)mh + sizeof(*mh);
245 memcpy(mh->key.actions, key.actions, actions_size);
246 mh->key.num_actions = num_actions;
247 INIT_LIST_HEAD(&mh->flows);
248
249 err = mlx5_modify_header_alloc(priv->mdev, namespace,
250 mh->key.num_actions,
251 mh->key.actions,
252 &mh->mod_hdr_id);
253 if (err)
254 goto out_err;
255
256 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
257 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
258 else
259 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
260
261attach_flow:
262 list_add(&flow->mod_hdr, &mh->flows);
263 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
264 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
265 else
266 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
267
268 return 0;
269
270out_err:
271 kfree(mh);
272 return err;
273}
274
275static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
276 struct mlx5e_tc_flow *flow)
277{
278 struct list_head *next = flow->mod_hdr.next;
279
280 list_del(&flow->mod_hdr);
281
282 if (list_empty(next)) {
283 struct mlx5e_mod_hdr_entry *mh;
284
285 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
286
287 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
288 hash_del(&mh->mod_hdr_hlist);
289 kfree(mh);
290 }
291}
292
77ab67b7
OG		 293static
294struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
295{
296 struct net_device *netdev;
297 struct mlx5e_priv *priv;
298
299 netdev = __dev_get_by_index(net, ifindex);
300 priv = netdev_priv(netdev);
301 return priv->mdev;
302}
303
304static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
305{
306 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
307 void *tirc;
308 int err;
309
310 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
311 if (err)
312 goto alloc_tdn_err;
313
314 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
315
316 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 317 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 318 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
319
320 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
321 if (err)
322 goto create_tir_err;
323
324 return 0;
325
326create_tir_err:
327 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
328alloc_tdn_err:
329 return err;
330}
331
332static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
333{
334 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
335 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
336}
337
3f6d08d1
OG		 338static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
339{
340 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
341 struct mlx5e_priv *priv = hp->func_priv;
342 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
343
344 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
345 hp->num_channels);
346
347 for (i = 0; i < sz; i++) {
348 ix = i;
bbeb53b8 349 if (priv->rss_params.hfunc == ETH_RSS_HASH_XOR)
3f6d08d1
OG		 350 ix = mlx5e_bits_invert(i, ilog2(sz));
351 ix = indirection_rqt[ix];
352 rqn = hp->pair->rqn[ix];
353 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
354 }
355}
356
357static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
358{
359 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
360 struct mlx5e_priv *priv = hp->func_priv;
361 struct mlx5_core_dev *mdev = priv->mdev;
362 void *rqtc;
363 u32 *in;
364
365 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
366 in = kvzalloc(inlen, GFP_KERNEL);
367 if (!in)
368 return -ENOMEM;
369
370 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
371
372 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
373 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
374
375 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
376
377 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
378 if (!err)
379 hp->indir_rqt.enabled = true;
380
381 kvfree(in);
382 return err;
383}
384
385static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
386{
387 struct mlx5e_priv *priv = hp->func_priv;
388 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
389 int tt, i, err;
390 void *tirc;
391
392 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
d930ac79
AL		 393 struct mlx5e_tirc_config ttconfig = mlx5e_tirc_get_default_config(tt);
394
3f6d08d1
OG		 395 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
396 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
397
398 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
399 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
400 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
bbeb53b8
AL		 401 mlx5e_build_indir_tir_ctx_hash(&priv->rss_params, &ttconfig, tirc, false);
402
3f6d08d1
OG		 403 err = mlx5_core_create_tir(hp->func_mdev, in,
404 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
405 if (err) {
406 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
407 goto err_destroy_tirs;
408 }
409 }
410 return 0;
411
412err_destroy_tirs:
413 for (i = 0; i < tt; i++)
414 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
415 return err;
416}
417
418static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
419{
420 int tt;
421
422 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
423 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
424}
425
426static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
427 struct ttc_params *ttc_params)
428{
429 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
430 int tt;
431
432 memset(ttc_params, 0, sizeof(*ttc_params));
433
434 ttc_params->any_tt_tirn = hp->tirn;
435
436 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
437 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
438
439 ft_attr->max_fte = MLX5E_NUM_TT;
440 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
441 ft_attr->prio = MLX5E_TC_PRIO;
442}
443
444static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
445{
446 struct mlx5e_priv *priv = hp->func_priv;
447 struct ttc_params ttc_params;
448 int err;
449
450 err = mlx5e_hairpin_create_indirect_rqt(hp);
451 if (err)
452 return err;
453
454 err = mlx5e_hairpin_create_indirect_tirs(hp);
455 if (err)
456 goto err_create_indirect_tirs;
457
458 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
459 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
460 if (err)
461 goto err_create_ttc_table;
462
463 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
464 hp->num_channels, hp->ttc.ft.t->id);
465
466 return 0;
467
468err_create_ttc_table:
469 mlx5e_hairpin_destroy_indirect_tirs(hp);
470err_create_indirect_tirs:
471 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
472
473 return err;
474}
475
476static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
477{
478 struct mlx5e_priv *priv = hp->func_priv;
479
480 mlx5e_destroy_ttc_table(priv, &hp->ttc);
481 mlx5e_hairpin_destroy_indirect_tirs(hp);
482 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
483}
484
77ab67b7
OG		 485static struct mlx5e_hairpin *
486mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
487 int peer_ifindex)
488{
489 struct mlx5_core_dev *func_mdev, *peer_mdev;
490 struct mlx5e_hairpin *hp;
491 struct mlx5_hairpin *pair;
492 int err;
493
494 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
495 if (!hp)
496 return ERR_PTR(-ENOMEM);
497
498 func_mdev = priv->mdev;
499 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
500
501 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
502 if (IS_ERR(pair)) {
503 err = PTR_ERR(pair);
504 goto create_pair_err;
505 }
506 hp->pair = pair;
507 hp->func_mdev = func_mdev;
3f6d08d1
OG		 508 hp->func_priv = priv;
509 hp->num_channels = params->num_channels;
77ab67b7
OG		 510
511 err = mlx5e_hairpin_create_transport(hp);
512 if (err)
513 goto create_transport_err;
514
3f6d08d1
OG		 515 if (hp->num_channels > 1) {
516 err = mlx5e_hairpin_rss_init(hp);
517 if (err)
518 goto rss_init_err;
519 }
520
77ab67b7
OG		 521 return hp;
522
3f6d08d1
OG		 523rss_init_err:
524 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 525create_transport_err:
526 mlx5_core_hairpin_destroy(hp->pair);
527create_pair_err:
528 kfree(hp);
529 return ERR_PTR(err);
530}
531
532static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
533{
3f6d08d1
OG		 534 if (hp->num_channels > 1)
535 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 536 mlx5e_hairpin_destroy_transport(hp);
537 mlx5_core_hairpin_destroy(hp->pair);
538 kvfree(hp);
539}
540
106be53b
OG		 541static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
542{
543 return (peer_vhca_id << 16 | prio);
544}
545
5c65c564 546static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 547 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 548{
549 struct mlx5e_hairpin_entry *hpe;
106be53b 550 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 551
552 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 553 hairpin_hlist, hash_key) {
554 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 555 return hpe;
556 }
557
558 return NULL;
559}
560
106be53b
OG		 561#define UNKNOWN_MATCH_PRIO 8
562
563static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 564 struct mlx5_flow_spec *spec, u8 *match_prio,
565 struct netlink_ext_ack *extack)
106be53b
OG		 566{
567 void *headers_c, *headers_v;
568 u8 prio_val, prio_mask = 0;
569 bool vlan_present;
570
571#ifdef CONFIG_MLX5_CORE_EN_DCB
572 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 573 NL_SET_ERR_MSG_MOD(extack,
574 "only PCP trust state supported for hairpin");
106be53b
OG		 575 return -EOPNOTSUPP;
576 }
577#endif
578 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
579 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
580
581 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
582 if (vlan_present) {
583 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
584 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
585 }
586
587 if (!vlan_present || !prio_mask) {
588 prio_val = UNKNOWN_MATCH_PRIO;
589 } else if (prio_mask != 0x7) {
e98bedf5
EB		 590 NL_SET_ERR_MSG_MOD(extack,
591 "masked priority match not supported for hairpin");
106be53b
OG		 592 return -EOPNOTSUPP;
593 }
594
595 *match_prio = prio_val;
596 return 0;
597}
598
5c65c564
OG		 599static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
600 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 601 struct mlx5e_tc_flow_parse_attr *parse_attr,
602 struct netlink_ext_ack *extack)
5c65c564 603{
98b66cb1 604 int peer_ifindex = parse_attr->mirred_ifindex[0];
5c65c564 605 struct mlx5_hairpin_params params;
d8822868 606 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 607 struct mlx5e_hairpin_entry *hpe;
608 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 609 u64 link_speed64;
610 u32 link_speed;
106be53b 611 u8 match_prio;
d8822868 612 u16 peer_id;
5c65c564
OG		 613 int err;
614
d8822868
OG		 615 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
616 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 617 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 618 return -EOPNOTSUPP;
619 }
620
d8822868 621 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 622 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
623 extack);
106be53b
OG		 624 if (err)
625 return err;
626 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 627 if (hpe)
628 goto attach_flow;
629
630 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
631 if (!hpe)
632 return -ENOMEM;
633
634 INIT_LIST_HEAD(&hpe->flows);
d8822868 635 hpe->peer_vhca_id = peer_id;
106be53b 636 hpe->prio = match_prio;
5c65c564
OG		 637
638 params.log_data_size = 15;
639 params.log_data_size = min_t(u8, params.log_data_size,
640 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
641 params.log_data_size = max_t(u8, params.log_data_size,
642 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 643
eb9180f7
OG		 644 params.log_num_packets = params.log_data_size -
645 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
646 params.log_num_packets = min_t(u8, params.log_num_packets,
647 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
648
649 params.q_counter = priv->q_counter;
3f6d08d1 650 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 651 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 652 link_speed = max_t(u32, link_speed, 50000);
653 link_speed64 = link_speed;
654 do_div(link_speed64, 50000);
655 params.num_channels = link_speed64;
656
5c65c564
OG		 657 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
658 if (IS_ERR(hp)) {
659 err = PTR_ERR(hp);
660 goto create_hairpin_err;
661 }
662
eb9180f7 663 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 664 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 665 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 666
667 hpe->hp = hp;
106be53b
OG		 668 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
669 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 670
671attach_flow:
3f6d08d1
OG		 672 if (hpe->hp->num_channels > 1) {
673 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
674 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
675 } else {
676 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
677 }
5c65c564 678 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 679
5c65c564
OG		 680 return 0;
681
682create_hairpin_err:
683 kfree(hpe);
684 return err;
685}
686
687static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
688 struct mlx5e_tc_flow *flow)
689{
690 struct list_head *next = flow->hairpin.next;
691
692 list_del(&flow->hairpin);
693
694 /* no more hairpin flows for us, release the hairpin pair */
695 if (list_empty(next)) {
696 struct mlx5e_hairpin_entry *hpe;
697
698 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
699
700 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
701 hpe->hp->pair->peer_mdev->priv.name);
702
703 mlx5e_hairpin_destroy(hpe->hp);
704 hash_del(&hpe->hairpin_hlist);
705 kfree(hpe);
706 }
707}
708
c83954ab 709static int
74491de9 710mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 711 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 712 struct mlx5e_tc_flow *flow,
713 struct netlink_ext_ack *extack)
e8f887ac 714{
aa0cbbae 715 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 716 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 717 struct mlx5_flow_destination dest[2] = {};
66958ed9 718 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 719 .action = attr->action,
720 .flow_tag = attr->flow_tag,
60786f09 721 .reformat_id = 0,
42f7ad67 722 .flags = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND,
66958ed9 723 };
aad7e08d 724 struct mlx5_fc *counter = NULL;
e8f887ac 725 bool table_created = false;
5c65c564 726 int err, dest_ix = 0;
e8f887ac 727
3f6d08d1 728 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
e98bedf5 729 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
3f6d08d1 730 if (err) {
3f6d08d1
OG		 731 goto err_add_hairpin_flow;
732 }
733 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
734 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
735 dest[dest_ix].ft = attr->hairpin_ft;
736 } else {
5c65c564
OG		 737 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
738 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 739 }
740 dest_ix++;
3f6d08d1
OG		 741 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
742 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
743 dest[dest_ix].ft = priv->fs.vlan.ft.t;
744 dest_ix++;
5c65c564 745 }
aad7e08d 746
5c65c564
OG		 747 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
748 counter = mlx5_fc_create(dev, true);
749 if (IS_ERR(counter)) {
c83954ab 750 err = PTR_ERR(counter);
5c65c564
OG		 751 goto err_fc_create;
752 }
753 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 754 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 755 dest_ix++;
b8aee822 756 attr->counter = counter;
aad7e08d
AV		 757 }
758
2f4fe4ca 759 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 760 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 761 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 762 kfree(parse_attr->mod_hdr_actions);
c83954ab 763 if (err)
2f4fe4ca 764 goto err_create_mod_hdr_id;
2f4fe4ca
OG		 765 }
766
acff797c 767 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 768 int tc_grp_size, tc_tbl_size;
769 u32 max_flow_counter;
770
771 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
772 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
773
774 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
775
776 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
777 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
778
acff797c
MG		 779 priv->fs.tc.t =
780 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
781 MLX5E_TC_PRIO,
21b9c144 782 tc_tbl_size,
acff797c 783 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 784 MLX5E_TC_FT_LEVEL, 0);
acff797c 785 if (IS_ERR(priv->fs.tc.t)) {
e98bedf5
EB		 786 NL_SET_ERR_MSG_MOD(extack,
787 "Failed to create tc offload table\n");
e8f887ac
AV		 788 netdev_err(priv->netdev,
789 "Failed to create tc offload table\n");
c83954ab 790 err = PTR_ERR(priv->fs.tc.t);
aad7e08d 791 goto err_create_ft;
e8f887ac
AV		 792 }
793
794 table_created = true;
795 }
796
38aa51c1
OG		 797 if (attr->match_level != MLX5_MATCH_NONE)
798 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
799
c83954ab
RL		 800 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
801 &flow_act, dest, dest_ix);
aad7e08d 802
c83954ab
RL		 803 if (IS_ERR(flow->rule[0])) {
804 err = PTR_ERR(flow->rule[0]);
aad7e08d 805 goto err_add_rule;
c83954ab 806 }
aad7e08d 807
c83954ab 808 return 0;
e8f887ac 809
aad7e08d
AV		 810err_add_rule:
811 if (table_created) {
acff797c
MG		 812 mlx5_destroy_flow_table(priv->fs.tc.t);
813 priv->fs.tc.t = NULL;
e8f887ac 814 }
aad7e08d 815err_create_ft:
2f4fe4ca 816 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 817 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 818err_create_mod_hdr_id:
aad7e08d 819 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 820err_fc_create:
821 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
822 mlx5e_hairpin_flow_del(priv, flow);
823err_add_hairpin_flow:
c83954ab 824 return err;
e8f887ac
AV		 825}
826
d85cdccb
OG		 827static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
828 struct mlx5e_tc_flow *flow)
829{
513f8f7f 830 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 831 struct mlx5_fc *counter = NULL;
832
b8aee822 833 counter = attr->counter;
e4ad91f2 834 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 835 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 836
d9ee0491 837 if (!mlx5e_tc_num_filters(priv, MLX5E_TC_NIC_OFFLOAD) && priv->fs.tc.t) {
d85cdccb
OG		 838 mlx5_destroy_flow_table(priv->fs.tc.t);
839 priv->fs.tc.t = NULL;
840 }
2f4fe4ca 841
513f8f7f 842 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 843 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 844
845 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
846 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 847}
848
aa0cbbae 849static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 850 struct mlx5e_tc_flow *flow, int out_index);
aa0cbbae 851
3c37745e
OG		 852static int mlx5e_attach_encap(struct mlx5e_priv *priv,
853 struct ip_tunnel_info *tun_info,
854 struct net_device *mirred_dev,
855 struct net_device **encap_dev,
e98bedf5 856 struct mlx5e_tc_flow *flow,
8c4dc42b
EB		 857 struct netlink_ext_ack *extack,
858 int out_index);
3c37745e 859
6d2a3ed0
OG		 860static struct mlx5_flow_handle *
861mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
862 struct mlx5e_tc_flow *flow,
863 struct mlx5_flow_spec *spec,
864 struct mlx5_esw_flow_attr *attr)
865{
866 struct mlx5_flow_handle *rule;
867
868 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
869 if (IS_ERR(rule))
870 return rule;
871
e85e02ba 872 if (attr->split_count) {
6d2a3ed0
OG		 873 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
874 if (IS_ERR(flow->rule[1])) {
875 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
876 return flow->rule[1];
877 }
878 }
879
880 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
881 return rule;
882}
883
884static void
885mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
886 struct mlx5e_tc_flow *flow,
887 struct mlx5_esw_flow_attr *attr)
888{
889 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
890
e85e02ba 891 if (attr->split_count)
6d2a3ed0
OG		 892 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
893
894 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
895}
896
5dbe906f
PB		 897static struct mlx5_flow_handle *
898mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
899 struct mlx5e_tc_flow *flow,
900 struct mlx5_flow_spec *spec,
901 struct mlx5_esw_flow_attr *slow_attr)
902{
903 struct mlx5_flow_handle *rule;
904
905 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 906 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 907 slow_attr->split_count = 0;
154e62ab 908 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 909
910 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
911 if (!IS_ERR(rule))
912 flow->flags |= MLX5E_TC_FLOW_SLOW;
913
914 return rule;
915}
916
917static void
918mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
919 struct mlx5e_tc_flow *flow,
920 struct mlx5_esw_flow_attr *slow_attr)
921{
922 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
154e62ab 923 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2be09de7 924 slow_attr->split_count = 0;
154e62ab 925 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN;
5dbe906f
PB		 926 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
927 flow->flags &= ~MLX5E_TC_FLOW_SLOW;
928}
929
c83954ab 930static int
74491de9 931mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 932 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 933 struct mlx5e_tc_flow *flow,
934 struct netlink_ext_ack *extack)
adb4c123
OG		 935{
936 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 937 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 938 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
bf07aa73 939 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 940 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 941 struct mlx5_fc *counter = NULL;
3c37745e
OG		 942 struct mlx5e_rep_priv *rpriv;
943 struct mlx5e_priv *out_priv;
c83954ab 944 int err = 0, encap_err = 0;
f493f155 945 int out_index;
8b32580d 946
d14f6f2a
OG		 947 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
948 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
949 return -EOPNOTSUPP;
950 }
bf07aa73
PB		 951
952 if (attr->chain > max_chain) {
953 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
954 err = -EOPNOTSUPP;
955 goto err_max_prio_chain;
956 }
957
958 if (attr->prio > max_prio) {
959 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
960 err = -EOPNOTSUPP;
961 goto err_max_prio_chain;
962 }
e52c2802 963
f493f155 964 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++) {
8c4dc42b
EB		 965 int mirred_ifindex;
966
f493f155
EB		 967 if (!(attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP))
968 continue;
969
8c4dc42b 970 mirred_ifindex = attr->parse_attr->mirred_ifindex[out_index];
3c37745e 971 out_dev = __dev_get_by_index(dev_net(priv->netdev),
8c4dc42b
EB		 972 mirred_ifindex);
973 err = mlx5e_attach_encap(priv,
974 &parse_attr->tun_info[out_index],
975 out_dev, &encap_dev, flow,
976 extack, out_index);
977 if (err && err != -EAGAIN)
c83954ab 978 goto err_attach_encap;
8c4dc42b
EB		 979 if (err == -EAGAIN)
980 encap_err = err;
3c37745e
OG		 981 out_priv = netdev_priv(encap_dev);
982 rpriv = out_priv->ppriv;
1cc26d74
EB		 983 attr->dests[out_index].rep = rpriv->rep;
984 attr->dests[out_index].mdev = out_priv->mdev;
3c37745e
OG		 985 }
986
8b32580d 987 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 988 if (err)
aa0cbbae 989 goto err_add_vlan;
adb4c123 990
d7e75a32 991 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 992 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 993 kfree(parse_attr->mod_hdr_actions);
c83954ab 994 if (err)
d7e75a32 995 goto err_mod_hdr;
d7e75a32
OG		 996 }
997
b8aee822 998 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
f9392795 999 counter = mlx5_fc_create(attr->counter_dev, true);
b8aee822 1000 if (IS_ERR(counter)) {
c83954ab 1001 err = PTR_ERR(counter);
b8aee822
MB		 1002 goto err_create_counter;
1003 }
1004
1005 attr->counter = counter;
1006 }
1007
c83954ab 1008 /* we get here if (1) there's no error or when
3c37745e
OG		 1009 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
1010 */
5dbe906f
PB		 1011 if (encap_err == -EAGAIN) {
1012 /* continue with goto slow path rule instead */
1013 struct mlx5_esw_flow_attr slow_attr;
1014
1015 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
1016 } else {
6d2a3ed0 1017 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 1018 }
c83954ab 1019
5dbe906f
PB		 1020 if (IS_ERR(flow->rule[0])) {
1021 err = PTR_ERR(flow->rule[0]);
1022 goto err_add_rule;
1023 }
1024
1025 return 0;
aa0cbbae
OG		 1026
1027err_add_rule:
f9392795 1028 mlx5_fc_destroy(attr->counter_dev, counter);
b8aee822 1029err_create_counter:
513f8f7f 1030 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1031 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 1032err_mod_hdr:
aa0cbbae
OG		 1033 mlx5_eswitch_del_vlan_action(esw, attr);
1034err_add_vlan:
f493f155 1035 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1036 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1037 mlx5e_detach_encap(priv, flow, out_index);
3c37745e 1038err_attach_encap:
bf07aa73 1039err_max_prio_chain:
c83954ab 1040 return err;
aa0cbbae 1041}
d85cdccb
OG		 1042
1043static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
1044 struct mlx5e_tc_flow *flow)
1045{
1046 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1047 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1048 struct mlx5_esw_flow_attr slow_attr;
f493f155 1049 int out_index;
d85cdccb 1050
5dbe906f
PB		 1051 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1052 if (flow->flags & MLX5E_TC_FLOW_SLOW)
1053 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1054 else
1055 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1056 }
d85cdccb 1057
513f8f7f 1058 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1059
f493f155 1060 for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
8c4dc42b
EB		 1061 if (attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1062 mlx5e_detach_encap(priv, flow, out_index);
f493f155 1063 kvfree(attr->parse_attr);
d7e75a32 1064
513f8f7f 1065 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1066 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1067
1068 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
f9392795 1069 mlx5_fc_destroy(attr->counter_dev, attr->counter);
d85cdccb
OG		 1070}
1071
232c0013
HHZ		 1072void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1073 struct mlx5e_encap_entry *e)
1074{
3c37745e 1075 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1076 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
6d2a3ed0
OG		 1077 struct mlx5_flow_handle *rule;
1078 struct mlx5_flow_spec *spec;
79baaec7 1079 struct encap_flow_item *efi;
232c0013
HHZ		 1080 struct mlx5e_tc_flow *flow;
1081 int err;
1082
54c177ca
OS		 1083 err = mlx5_packet_reformat_alloc(priv->mdev,
1084 e->reformat_type,
60786f09 1085 e->encap_size, e->encap_header,
31ca3648 1086 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1087 &e->encap_id);
232c0013
HHZ		 1088 if (err) {
1089 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1090 err);
1091 return;
1092 }
1093 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1094 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013 1095
79baaec7 1096 list_for_each_entry(efi, &e->flows, list) {
8c4dc42b
EB		 1097 bool all_flow_encaps_valid = true;
1098 int i;
1099
79baaec7 1100 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
3c37745e 1101 esw_attr = flow->esw_attr;
6d2a3ed0
OG		 1102 spec = &esw_attr->parse_attr->spec;
1103
8c4dc42b
EB		 1104 esw_attr->dests[efi->index].encap_id = e->encap_id;
1105 esw_attr->dests[efi->index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
1106 /* Flow can be associated with multiple encap entries.
1107 * Before offloading the flow verify that all of them have
1108 * a valid neighbour.
1109 */
1110 for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
1111 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP))
1112 continue;
1113 if (!(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID)) {
1114 all_flow_encaps_valid = false;
1115 break;
1116 }
1117 }
1118 /* Do not offload flows with unresolved neighbors */
1119 if (!all_flow_encaps_valid)
1120 continue;
5dbe906f 1121 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1122 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1123 if (IS_ERR(rule)) {
1124 err = PTR_ERR(rule);
232c0013
HHZ		 1125 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1126 err);
1127 continue;
1128 }
5dbe906f
PB		 1129
1130 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1131 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */
6d2a3ed0 1132 flow->rule[0] = rule;
232c0013
HHZ		 1133 }
1134}
1135
1136void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1137 struct mlx5e_encap_entry *e)
1138{
3c37745e 1139 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1140 struct mlx5_esw_flow_attr slow_attr;
1141 struct mlx5_flow_handle *rule;
1142 struct mlx5_flow_spec *spec;
79baaec7 1143 struct encap_flow_item *efi;
232c0013 1144 struct mlx5e_tc_flow *flow;
5dbe906f 1145 int err;
232c0013 1146
79baaec7
EB		 1147 list_for_each_entry(efi, &e->flows, list) {
1148 flow = container_of(efi, struct mlx5e_tc_flow, encaps[efi->index]);
5dbe906f
PB		 1149 spec = &flow->esw_attr->parse_attr->spec;
1150
1151 /* update from encap rule to slow path rule */
1152 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
8c4dc42b
EB		 1153 /* mark the flow's encap dest as non-valid */
1154 flow->esw_attr->dests[efi->index].flags &= ~MLX5_ESW_DEST_ENCAP_VALID;
5dbe906f
PB		 1155
1156 if (IS_ERR(rule)) {
1157 err = PTR_ERR(rule);
1158 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1159 err);
1160 continue;
1161 }
1162
1163 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1164 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */
1165 flow->rule[0] = rule;
232c0013
HHZ		 1166 }
1167
61c806da
OG		 1168 /* we know that the encap is valid */
1169 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
1170 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1171}
1172
b8aee822
MB		 1173static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1174{
1175 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1176 return flow->esw_attr->counter;
1177 else
1178 return flow->nic_attr->counter;
1179}
1180
f6dfb4c3
HHZ		 1181void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1182{
1183 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1184 u64 bytes, packets, lastuse = 0;
1185 struct mlx5e_tc_flow *flow;
1186 struct mlx5e_encap_entry *e;
1187 struct mlx5_fc *counter;
1188 struct neigh_table *tbl;
1189 bool neigh_used = false;
1190 struct neighbour *n;
1191
1192 if (m_neigh->family == AF_INET)
1193 tbl = &arp_tbl;
1194#if IS_ENABLED(CONFIG_IPV6)
1195 else if (m_neigh->family == AF_INET6)
423c9db2 1196 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1197#endif
1198 else
1199 return;
1200
1201 list_for_each_entry(e, &nhe->encap_list, encap_list) {
79baaec7 1202 struct encap_flow_item *efi;
f6dfb4c3
HHZ		 1203 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1204 continue;
79baaec7
EB		 1205 list_for_each_entry(efi, &e->flows, list) {
1206 flow = container_of(efi, struct mlx5e_tc_flow,
1207 encaps[efi->index]);
f6dfb4c3 1208 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
b8aee822 1209 counter = mlx5e_tc_get_counter(flow);
f6dfb4c3
HHZ		 1210 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1211 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1212 neigh_used = true;
1213 break;
1214 }
1215 }
1216 }
e36d4810
RD		 1217 if (neigh_used)
1218 break;
f6dfb4c3
HHZ		 1219 }
1220
1221 if (neigh_used) {
1222 nhe->reported_lastuse = jiffies;
1223
1224 /* find the relevant neigh according to the cached device and
1225 * dst ip pair
1226 */
1227 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1228 if (!n)
f6dfb4c3 1229 return;
f6dfb4c3
HHZ		 1230
1231 neigh_event_send(n, NULL);
1232 neigh_release(n);
1233 }
1234}
1235
d85cdccb 1236static void mlx5e_detach_encap(struct mlx5e_priv *priv,
8c4dc42b 1237 struct mlx5e_tc_flow *flow, int out_index)
d85cdccb 1238{
8c4dc42b 1239 struct list_head *next = flow->encaps[out_index].list.next;
5067b602 1240
8c4dc42b 1241 list_del(&flow->encaps[out_index].list);
5067b602 1242 if (list_empty(next)) {
c1ae1152 1243 struct mlx5e_encap_entry *e;
5067b602 1244
c1ae1152 1245 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1246 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1247
1248 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1249 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1250
cdc5a7f3 1251 hash_del_rcu(&e->encap_hlist);
232c0013 1252 kfree(e->encap_header);
5067b602
RD		 1253 kfree(e);
1254 }
1255}
1256
04de7dda
RD		 1257static void __mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1258{
1259 struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
1260
1261 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
1262 !(flow->flags & MLX5E_TC_FLOW_DUP))
1263 return;
1264
1265 mutex_lock(&esw->offloads.peer_mutex);
1266 list_del(&flow->peer);
1267 mutex_unlock(&esw->offloads.peer_mutex);
1268
1269 flow->flags &= ~MLX5E_TC_FLOW_DUP;
1270
1271 mlx5e_tc_del_fdb_flow(flow->peer_flow->priv, flow->peer_flow);
1272 kvfree(flow->peer_flow);
1273 flow->peer_flow = NULL;
1274}
1275
1276static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow)
1277{
1278 struct mlx5_core_dev *dev = flow->priv->mdev;
1279 struct mlx5_devcom *devcom = dev->priv.devcom;
1280 struct mlx5_eswitch *peer_esw;
1281
1282 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1283 if (!peer_esw)
1284 return;
1285
1286 __mlx5e_tc_del_fdb_peer_flow(flow);
1287 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
1288}
1289
e8f887ac 1290static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1291 struct mlx5e_tc_flow *flow)
e8f887ac 1292{
04de7dda
RD		 1293 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
1294 mlx5e_tc_del_fdb_peer_flow(flow);
d85cdccb 1295 mlx5e_tc_del_fdb_flow(priv, flow);
04de7dda 1296 } else {
d85cdccb 1297 mlx5e_tc_del_nic_flow(priv, flow);
04de7dda 1298 }
e8f887ac
AV		 1299}
1300
bbd00f7e
HHZ		 1301
1302static int parse_tunnel_attr(struct mlx5e_priv *priv,
1303 struct mlx5_flow_spec *spec,
54c177ca
OS		 1304 struct tc_cls_flower_offload *f,
1305 struct net_device *filter_dev)
bbd00f7e 1306{
e98bedf5 1307 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1308 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1309 outer_headers);
1310 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1311 outer_headers);
1312
2e72eb43
OG		 1313 struct flow_dissector_key_control *enc_control =
1314 skb_flow_dissector_target(f->dissector,
1315 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1316 f->key);
54c177ca 1317 int err = 0;
2e72eb43 1318
101f4de9
OS		 1319 err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
1320 headers_c, headers_v);
54c177ca
OS		 1321 if (err) {
1322 NL_SET_ERR_MSG_MOD(extack,
1323 "failed to parse tunnel attributes");
101f4de9 1324 return err;
bbd00f7e
HHZ		 1325 }
1326
2e72eb43 1327 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 1328 struct flow_dissector_key_ipv4_addrs *key =
1329 skb_flow_dissector_target(f->dissector,
1330 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1331 f->key);
1332 struct flow_dissector_key_ipv4_addrs *mask =
1333 skb_flow_dissector_target(f->dissector,
1334 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1335 f->mask);
1336 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1337 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1338 ntohl(mask->src));
1339 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1340 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1341 ntohl(key->src));
1342
1343 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1344 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1345 ntohl(mask->dst));
1346 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1347 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1348 ntohl(key->dst));
bbd00f7e 1349
2e72eb43
OG		 1350 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1351 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 1352 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1353 struct flow_dissector_key_ipv6_addrs *key =
1354 skb_flow_dissector_target(f->dissector,
1355 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1356 f->key);
1357 struct flow_dissector_key_ipv6_addrs *mask =
1358 skb_flow_dissector_target(f->dissector,
1359 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1360 f->mask);
1361
1362 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1363 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1364 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1365 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1366 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1367 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1368
1369 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1370 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1371 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1372 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1373 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1374 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1375
1376 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1377 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1378 }
bbd00f7e 1379
bcef735c
OG		 1380 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_IP)) {
1381 struct flow_dissector_key_ip *key =
1382 skb_flow_dissector_target(f->dissector,
1383 FLOW_DISSECTOR_KEY_ENC_IP,
1384 f->key);
1385 struct flow_dissector_key_ip *mask =
1386 skb_flow_dissector_target(f->dissector,
1387 FLOW_DISSECTOR_KEY_ENC_IP,
1388 f->mask);
1389
1390 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1391 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1392
1393 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1394 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1395
1396 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1397 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
e98bedf5
EB		 1398
1399 if (mask->ttl &&
1400 !MLX5_CAP_ESW_FLOWTABLE_FDB
1401 (priv->mdev,
1402 ft_field_support.outer_ipv4_ttl)) {
1403 NL_SET_ERR_MSG_MOD(extack,
1404 "Matching on TTL is not supported");
1405 return -EOPNOTSUPP;
1406 }
1407
bcef735c
OG		 1408 }
1409
bbd00f7e
HHZ		 1410 /* Enforce DMAC when offloading incoming tunneled flows.
1411 * Flow counters require a match on the DMAC.
1412 */
1413 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1414 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1415 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1416 dmac_47_16), priv->netdev->dev_addr);
1417
1418 /* let software handle IP fragments */
1419 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1420 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1421
1422 return 0;
1423}
1424
de0af0bf
RD		 1425static int __parse_cls_flower(struct mlx5e_priv *priv,
1426 struct mlx5_flow_spec *spec,
1427 struct tc_cls_flower_offload *f,
54c177ca 1428 struct net_device *filter_dev,
d708f902 1429 u8 *match_level)
e3a2b7ed 1430{
e98bedf5 1431 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1432 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1433 outer_headers);
1434 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1435 outer_headers);
699e96dd
JL		 1436 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1437 misc_parameters);
1438 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1439 misc_parameters);
e3a2b7ed
AV		 1440 u16 addr_type = 0;
1441 u8 ip_proto = 0;
1442
d708f902 1443 *match_level = MLX5_MATCH_NONE;
de0af0bf 1444
e3a2b7ed
AV		 1445 if (f->dissector->used_keys &
1446 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1447 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1448 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1449 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1450 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1451 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1452 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1453 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1454 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1455 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1456 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1457 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1458 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1459 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c
OG		 1460 BIT(FLOW_DISSECTOR_KEY_IP) |
1461 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
e98bedf5 1462 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed
AV		 1463 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1464 f->dissector->used_keys);
1465 return -EOPNOTSUPP;
1466 }
1467
bbd00f7e
HHZ		 1468 if ((dissector_uses_key(f->dissector,
1469 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1470 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1471 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1472 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1473 struct flow_dissector_key_control *key =
1474 skb_flow_dissector_target(f->dissector,
1475 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1476 f->key);
1477 switch (key->addr_type) {
1478 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1479 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
54c177ca 1480 if (parse_tunnel_attr(priv, spec, f, filter_dev))
bbd00f7e
HHZ		 1481 return -EOPNOTSUPP;
1482 break;
1483 default:
1484 return -EOPNOTSUPP;
1485 }
1486
1487 /* In decap flow, header pointers should point to the inner
1488 * headers, outer header were already set by parse_tunnel_attr
1489 */
1490 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1491 inner_headers);
1492 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1493 inner_headers);
1494 }
1495
d3a80bb5
OG		 1496 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1497 struct flow_dissector_key_basic *key =
e3a2b7ed 1498 skb_flow_dissector_target(f->dissector,
d3a80bb5 1499 FLOW_DISSECTOR_KEY_BASIC,
e3a2b7ed 1500 f->key);
d3a80bb5 1501 struct flow_dissector_key_basic *mask =
e3a2b7ed 1502 skb_flow_dissector_target(f->dissector,
d3a80bb5 1503 FLOW_DISSECTOR_KEY_BASIC,
e3a2b7ed 1504 f->mask);
d3a80bb5
OG		 1505 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1506 ntohs(mask->n_proto));
1507 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1508 ntohs(key->n_proto));
e3a2b7ed 1509
d3a80bb5 1510 if (mask->n_proto)
d708f902 1511 *match_level = MLX5_MATCH_L2;
e3a2b7ed
AV		 1512 }
1513
095b6cfd
OG		 1514 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1515 struct flow_dissector_key_vlan *key =
1516 skb_flow_dissector_target(f->dissector,
1517 FLOW_DISSECTOR_KEY_VLAN,
1518 f->key);
1519 struct flow_dissector_key_vlan *mask =
1520 skb_flow_dissector_target(f->dissector,
1521 FLOW_DISSECTOR_KEY_VLAN,
1522 f->mask);
699e96dd
JL		 1523 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1524 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1525 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1526 svlan_tag, 1);
1527 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1528 svlan_tag, 1);
1529 } else {
1530 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1531 cvlan_tag, 1);
1532 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1533 cvlan_tag, 1);
1534 }
095b6cfd
OG		 1535
1536 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1537 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 1538
1539 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1540 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
54782900 1541
d708f902 1542 *match_level = MLX5_MATCH_L2;
54782900 1543 }
d3a80bb5 1544 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1545 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1546 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1547 *match_level = MLX5_MATCH_L2;
54782900
OG		 1548 }
1549
699e96dd
JL		 1550 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CVLAN)) {
1551 struct flow_dissector_key_vlan *key =
1552 skb_flow_dissector_target(f->dissector,
1553 FLOW_DISSECTOR_KEY_CVLAN,
1554 f->key);
1555 struct flow_dissector_key_vlan *mask =
1556 skb_flow_dissector_target(f->dissector,
1557 FLOW_DISSECTOR_KEY_CVLAN,
1558 f->mask);
1559 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1560 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1561 MLX5_SET(fte_match_set_misc, misc_c,
1562 outer_second_svlan_tag, 1);
1563 MLX5_SET(fte_match_set_misc, misc_v,
1564 outer_second_svlan_tag, 1);
1565 } else {
1566 MLX5_SET(fte_match_set_misc, misc_c,
1567 outer_second_cvlan_tag, 1);
1568 MLX5_SET(fte_match_set_misc, misc_v,
1569 outer_second_cvlan_tag, 1);
1570 }
1571
1572 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1573 mask->vlan_id);
1574 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1575 key->vlan_id);
1576 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1577 mask->vlan_priority);
1578 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1579 key->vlan_priority);
1580
1581 *match_level = MLX5_MATCH_L2;
1582 }
1583 }
1584
d3a80bb5
OG		 1585 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1586 struct flow_dissector_key_eth_addrs *key =
54782900 1587 skb_flow_dissector_target(f->dissector,
d3a80bb5 1588 FLOW_DISSECTOR_KEY_ETH_ADDRS,
54782900 1589 f->key);
d3a80bb5 1590 struct flow_dissector_key_eth_addrs *mask =
54782900 1591 skb_flow_dissector_target(f->dissector,
d3a80bb5 1592 FLOW_DISSECTOR_KEY_ETH_ADDRS,
54782900 1593 f->mask);
54782900 1594
d3a80bb5
OG		 1595 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1596 dmac_47_16),
1597 mask->dst);
1598 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1599 dmac_47_16),
1600 key->dst);
1601
1602 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1603 smac_47_16),
1604 mask->src);
1605 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1606 smac_47_16),
1607 key->src);
1608
1609 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
d708f902 1610 *match_level = MLX5_MATCH_L2;
54782900
OG		 1611 }
1612
1613 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1614 struct flow_dissector_key_control *key =
1615 skb_flow_dissector_target(f->dissector,
1616 FLOW_DISSECTOR_KEY_CONTROL,
1617 f->key);
1618
1619 struct flow_dissector_key_control *mask =
1620 skb_flow_dissector_target(f->dissector,
1621 FLOW_DISSECTOR_KEY_CONTROL,
1622 f->mask);
1623 addr_type = key->addr_type;
1624
1625 /* the HW doesn't support frag first/later */
1626 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1627 return -EOPNOTSUPP;
1628
1629 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1630 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1631 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1632 key->flags & FLOW_DIS_IS_FRAGMENT);
1633
1634 /* the HW doesn't need L3 inline to match on frag=no */
1635 if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1636 *match_level = MLX5_MATCH_L2;
54782900
OG		 1637 /* *** L2 attributes parsing up to here *** */
1638 else
83621b7d 1639 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1640 }
1641 }
1642
54782900
OG		 1643 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1644 struct flow_dissector_key_basic *key =
1645 skb_flow_dissector_target(f->dissector,
1646 FLOW_DISSECTOR_KEY_BASIC,
1647 f->key);
1648 struct flow_dissector_key_basic *mask =
1649 skb_flow_dissector_target(f->dissector,
1650 FLOW_DISSECTOR_KEY_BASIC,
1651 f->mask);
1652 ip_proto = key->ip_proto;
1653
1654 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1655 mask->ip_proto);
1656 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1657 key->ip_proto);
1658
1659 if (mask->ip_proto)
d708f902 1660 *match_level = MLX5_MATCH_L3;
54782900
OG		 1661 }
1662
e3a2b7ed
AV		 1663 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1664 struct flow_dissector_key_ipv4_addrs *key =
1665 skb_flow_dissector_target(f->dissector,
1666 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1667 f->key);
1668 struct flow_dissector_key_ipv4_addrs *mask =
1669 skb_flow_dissector_target(f->dissector,
1670 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1671 f->mask);
1672
1673 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1674 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1675 &mask->src, sizeof(mask->src));
1676 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1677 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1678 &key->src, sizeof(key->src));
1679 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1680 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1681 &mask->dst, sizeof(mask->dst));
1682 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1683 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1684 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1685
1686 if (mask->src || mask->dst)
d708f902 1687 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1688 }
1689
1690 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1691 struct flow_dissector_key_ipv6_addrs *key =
1692 skb_flow_dissector_target(f->dissector,
1693 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1694 f->key);
1695 struct flow_dissector_key_ipv6_addrs *mask =
1696 skb_flow_dissector_target(f->dissector,
1697 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1698 f->mask);
1699
1700 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1701 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1702 &mask->src, sizeof(mask->src));
1703 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1704 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1705 &key->src, sizeof(key->src));
1706
1707 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1708 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1709 &mask->dst, sizeof(mask->dst));
1710 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1711 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1712 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1713
1714 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1715 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
d708f902 1716 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1717 }
1718
1f97a526
OG		 1719 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1720 struct flow_dissector_key_ip *key =
1721 skb_flow_dissector_target(f->dissector,
1722 FLOW_DISSECTOR_KEY_IP,
1723 f->key);
1724 struct flow_dissector_key_ip *mask =
1725 skb_flow_dissector_target(f->dissector,
1726 FLOW_DISSECTOR_KEY_IP,
1727 f->mask);
1728
1729 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1730 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1731
1732 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1733 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1734
a8ade55f
OG		 1735 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1736 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 1737
a8ade55f
OG		 1738 if (mask->ttl &&
1739 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1740 ft_field_support.outer_ipv4_ttl)) {
1741 NL_SET_ERR_MSG_MOD(extack,
1742 "Matching on TTL is not supported");
1f97a526 1743 return -EOPNOTSUPP;
e98bedf5 1744 }
a8ade55f
OG		 1745
1746 if (mask->tos || mask->ttl)
d708f902 1747 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1748 }
1749
54782900
OG		 1750 /* *** L3 attributes parsing up to here *** */
1751
e3a2b7ed
AV		 1752 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1753 struct flow_dissector_key_ports *key =
1754 skb_flow_dissector_target(f->dissector,
1755 FLOW_DISSECTOR_KEY_PORTS,
1756 f->key);
1757 struct flow_dissector_key_ports *mask =
1758 skb_flow_dissector_target(f->dissector,
1759 FLOW_DISSECTOR_KEY_PORTS,
1760 f->mask);
1761 switch (ip_proto) {
1762 case IPPROTO_TCP:
1763 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1764 tcp_sport, ntohs(mask->src));
1765 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1766 tcp_sport, ntohs(key->src));
1767
1768 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1769 tcp_dport, ntohs(mask->dst));
1770 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1771 tcp_dport, ntohs(key->dst));
1772 break;
1773
1774 case IPPROTO_UDP:
1775 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1776 udp_sport, ntohs(mask->src));
1777 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1778 udp_sport, ntohs(key->src));
1779
1780 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1781 udp_dport, ntohs(mask->dst));
1782 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1783 udp_dport, ntohs(key->dst));
1784 break;
1785 default:
e98bedf5
EB		 1786 NL_SET_ERR_MSG_MOD(extack,
1787 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1788 netdev_err(priv->netdev,
1789 "Only UDP and TCP transport are supported\n");
1790 return -EINVAL;
1791 }
de0af0bf
RD		 1792
1793 if (mask->src || mask->dst)
d708f902 1794 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1795 }
1796
e77834ec
OG		 1797 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1798 struct flow_dissector_key_tcp *key =
1799 skb_flow_dissector_target(f->dissector,
1800 FLOW_DISSECTOR_KEY_TCP,
1801 f->key);
1802 struct flow_dissector_key_tcp *mask =
1803 skb_flow_dissector_target(f->dissector,
1804 FLOW_DISSECTOR_KEY_TCP,
1805 f->mask);
1806
1807 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1808 ntohs(mask->flags));
1809 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1810 ntohs(key->flags));
1811
1812 if (mask->flags)
d708f902 1813 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1814 }
1815
e3a2b7ed
AV		 1816 return 0;
1817}
1818
de0af0bf 1819static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1820 struct mlx5e_tc_flow *flow,
de0af0bf 1821 struct mlx5_flow_spec *spec,
54c177ca
OS		 1822 struct tc_cls_flower_offload *f,
1823 struct net_device *filter_dev)
de0af0bf 1824{
e98bedf5 1825 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1826 struct mlx5_core_dev *dev = priv->mdev;
1827 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1828 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1829 struct mlx5_eswitch_rep *rep;
d708f902 1830 u8 match_level;
de0af0bf
RD		 1831 int err;
1832
54c177ca 1833 err = __parse_cls_flower(priv, spec, f, filter_dev, &match_level);
de0af0bf 1834
1d447a39
SM		 1835 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1836 rep = rpriv->rep;
1837 if (rep->vport != FDB_UPLINK_VPORT &&
1838 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1839 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1840 NL_SET_ERR_MSG_MOD(extack,
1841 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1842 netdev_warn(priv->netdev,
1843 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1844 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1845 return -EOPNOTSUPP;
1846 }
1847 }
1848
38aa51c1
OG		 1849 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1850 flow->esw_attr->match_level = match_level;
1851 else
1852 flow->nic_attr->match_level = match_level;
1853
de0af0bf
RD		 1854 return err;
1855}
1856
d79b6df6
OG		 1857struct pedit_headers {
1858 struct ethhdr eth;
1859 struct iphdr ip4;
1860 struct ipv6hdr ip6;
1861 struct tcphdr tcp;
1862 struct udphdr udp;
1863};
1864
1865static int pedit_header_offsets[] = {
1866 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1867 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1868 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1869 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1870 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1871};
1872
1873#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1874
1875static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1876 struct pedit_headers *masks,
1877 struct pedit_headers *vals)
1878{
1879 u32 *curr_pmask, *curr_pval;
1880
1881 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1882 goto out_err;
1883
1884 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1885 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1886
1887 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1888 goto out_err;
1889
1890 *curr_pmask |= mask;
1891 *curr_pval |= (val & mask);
1892
1893 return 0;
1894
1895out_err:
1896 return -EOPNOTSUPP;
1897}
1898
1899struct mlx5_fields {
1900 u8 field;
1901 u8 size;
1902 u32 offset;
1903};
1904
a8e4f0c4
OG		 1905#define OFFLOAD(fw_field, size, field, off) \
1906 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1907
d79b6df6 1908static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1909 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1910 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1911 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1912 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1913 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1914
1915 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1916 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1917 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1918
1919 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1920 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1921 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1922 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1923 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1924 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1925 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1926 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1927 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1928
1929 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1930 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1931 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1932
1933 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1934 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1935};
1936
1937/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1938 * max from the SW pedit action. On success, it says how many HW actions were
1939 * actually parsed.
1940 */
1941static int offload_pedit_fields(struct pedit_headers *masks,
1942 struct pedit_headers *vals,
e98bedf5
EB		 1943 struct mlx5e_tc_flow_parse_attr *parse_attr,
1944 struct netlink_ext_ack *extack)
d79b6df6
OG		 1945{
1946 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1947 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1948 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1949 struct mlx5_fields *f;
1950 u8 cmd, field_bsize;
e3ca4e05 1951 u32 s_mask, a_mask;
d79b6df6 1952 unsigned long mask;
2b64beba
OG		 1953 __be32 mask_be32;
1954 __be16 mask_be16;
d79b6df6
OG		 1955 void *action;
1956
1957 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1958 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1959 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1960 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1961
1962 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1963 action = parse_attr->mod_hdr_actions;
1964 max_actions = parse_attr->num_mod_hdr_actions;
1965 nactions = 0;
1966
1967 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1968 f = &fields[i];
1969 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1970 s_mask = 0;
1971 a_mask = 0;
d79b6df6
OG		 1972
1973 s_masks_p = (void *)set_masks + f->offset;
1974 a_masks_p = (void *)add_masks + f->offset;
1975
1976 memcpy(&s_mask, s_masks_p, f->size);
1977 memcpy(&a_mask, a_masks_p, f->size);
1978
1979 if (!s_mask && !a_mask) /* nothing to offload here */
1980 continue;
1981
1982 if (s_mask && a_mask) {
e98bedf5
EB		 1983 NL_SET_ERR_MSG_MOD(extack,
1984 "can't set and add to the same HW field");
d79b6df6
OG		 1985 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1986 return -EOPNOTSUPP;
1987 }
1988
1989 if (nactions == max_actions) {
e98bedf5
EB		 1990 NL_SET_ERR_MSG_MOD(extack,
1991 "too many pedit actions, can't offload");
d79b6df6
OG		 1992 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1993 return -EOPNOTSUPP;
1994 }
1995
1996 if (s_mask) {
1997 cmd = MLX5_ACTION_TYPE_SET;
1998 mask = s_mask;
1999 vals_p = (void *)set_vals + f->offset;
2000 /* clear to denote we consumed this field */
2001 memset(s_masks_p, 0, f->size);
2002 } else {
2003 cmd = MLX5_ACTION_TYPE_ADD;
2004 mask = a_mask;
2005 vals_p = (void *)add_vals + f->offset;
2006 /* clear to denote we consumed this field */
2007 memset(a_masks_p, 0, f->size);
2008 }
2009
d79b6df6 2010 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 2011
2b64beba
OG		 2012 if (field_bsize == 32) {
2013 mask_be32 = *(__be32 *)&mask;
2014 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
2015 } else if (field_bsize == 16) {
2016 mask_be16 = *(__be16 *)&mask;
2017 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
2018 }
2019
d79b6df6 2020 first = find_first_bit(&mask, field_bsize);
2b64beba 2021 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 2022 last = find_last_bit(&mask, field_bsize);
2b64beba 2023 if (first < next_z && next_z < last) {
e98bedf5
EB		 2024 NL_SET_ERR_MSG_MOD(extack,
2025 "rewrite of few sub-fields isn't supported");
2b64beba 2026 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 2027 mask);
2028 return -EOPNOTSUPP;
2029 }
2030
2031 MLX5_SET(set_action_in, action, action_type, cmd);
2032 MLX5_SET(set_action_in, action, field, f->field);
2033
2034 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 2035 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 2036 /* length is num of bits to be written, zero means length of 32 */
2b64beba 2037 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 2038 }
2039
2040 if (field_bsize == 32)
2b64beba 2041 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 2042 else if (field_bsize == 16)
2b64beba 2043 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 2044 else if (field_bsize == 8)
2b64beba 2045 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 2046
2047 action += action_size;
2048 nactions++;
2049 }
2050
2051 parse_attr->num_mod_hdr_actions = nactions;
2052 return 0;
2053}
2054
2055static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
2056 const struct tc_action *a, int namespace,
2057 struct mlx5e_tc_flow_parse_attr *parse_attr)
2058{
2059 int nkeys, action_size, max_actions;
2060
2061 nkeys = tcf_pedit_nkeys(a);
2062 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2063
2064 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2065 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
2066 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2067 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
2068
2069 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2070 max_actions = min(max_actions, nkeys * 16);
2071
2072 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2073 if (!parse_attr->mod_hdr_actions)
2074 return -ENOMEM;
2075
2076 parse_attr->num_mod_hdr_actions = max_actions;
2077 return 0;
2078}
2079
2080static const struct pedit_headers zero_masks = {};
2081
2082static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2083 const struct tc_action *a, int namespace,
e98bedf5
EB		 2084 struct mlx5e_tc_flow_parse_attr *parse_attr,
2085 struct netlink_ext_ack *extack)
d79b6df6
OG		 2086{
2087 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
2088 int nkeys, i, err = -EOPNOTSUPP;
2089 u32 mask, val, offset;
2090 u8 cmd, htype;
2091
2092 nkeys = tcf_pedit_nkeys(a);
2093
2094 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2095 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2096
2097 for (i = 0; i < nkeys; i++) {
2098 htype = tcf_pedit_htype(a, i);
2099 cmd = tcf_pedit_cmd(a, i);
2100 err = -EOPNOTSUPP; /* can't be all optimistic */
2101
2102 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
e98bedf5
EB		 2103 NL_SET_ERR_MSG_MOD(extack,
2104 "legacy pedit isn't offloaded");
d79b6df6
OG		 2105 goto out_err;
2106 }
2107
2108 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
e98bedf5 2109 NL_SET_ERR_MSG_MOD(extack, "pedit cmd isn't offloaded");
d79b6df6
OG		 2110 goto out_err;
2111 }
2112
2113 mask = tcf_pedit_mask(a, i);
2114 val = tcf_pedit_val(a, i);
2115 offset = tcf_pedit_offset(a, i);
2116
2117 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
2118 if (err)
2119 goto out_err;
2120 }
2121
2122 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
2123 if (err)
2124 goto out_err;
2125
e98bedf5 2126 err = offload_pedit_fields(masks, vals, parse_attr, extack);
d79b6df6
OG		 2127 if (err < 0)
2128 goto out_dealloc_parsed_actions;
2129
2130 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2131 cmd_masks = &masks[cmd];
2132 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2133 NL_SET_ERR_MSG_MOD(extack,
2134 "attempt to offload an unsupported field");
b3a433de 2135 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2136 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2137 16, 1, cmd_masks, sizeof(zero_masks), true);
2138 err = -EOPNOTSUPP;
2139 goto out_dealloc_parsed_actions;
2140 }
2141 }
2142
2143 return 0;
2144
2145out_dealloc_parsed_actions:
2146 kfree(parse_attr->mod_hdr_actions);
2147out_err:
2148 return err;
2149}
2150
e98bedf5
EB		 2151static bool csum_offload_supported(struct mlx5e_priv *priv,
2152 u32 action,
2153 u32 update_flags,
2154 struct netlink_ext_ack *extack)
26c02749
OG		 2155{
2156 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2157 TCA_CSUM_UPDATE_FLAG_UDP;
2158
2159 /* The HW recalcs checksums only if re-writing headers */
2160 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2161 NL_SET_ERR_MSG_MOD(extack,
2162 "TC csum action is only offloaded with pedit");
26c02749
OG		 2163 netdev_warn(priv->netdev,
2164 "TC csum action is only offloaded with pedit\n");
2165 return false;
2166 }
2167
2168 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2169 NL_SET_ERR_MSG_MOD(extack,
2170 "can't offload TC csum action for some header/s");
26c02749
OG		 2171 netdev_warn(priv->netdev,
2172 "can't offload TC csum action for some header/s - flags %#x\n",
2173 update_flags);
2174 return false;
2175 }
2176
2177 return true;
2178}
2179
bdd66ac0 2180static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
e98bedf5
EB		 2181 struct tcf_exts *exts,
2182 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2183{
2184 const struct tc_action *a;
2185 bool modify_ip_header;
bdd66ac0
OG		 2186 u8 htype, ip_proto;
2187 void *headers_v;
2188 u16 ethertype;
2189 int nkeys, i;
2190
2191 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2192 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2193
2194 /* for non-IP we only re-write MACs, so we're okay */
2195 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2196 goto out_ok;
2197
2198 modify_ip_header = false;
244cd96a
CW		 2199 tcf_exts_for_each_action(i, a, exts) {
2200 int k;
2201
bdd66ac0
OG		 2202 if (!is_tcf_pedit(a))
2203 continue;
2204
2205 nkeys = tcf_pedit_nkeys(a);
244cd96a
CW		 2206 for (k = 0; k < nkeys; k++) {
2207 htype = tcf_pedit_htype(a, k);
bdd66ac0
OG		 2208 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
2209 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
2210 modify_ip_header = true;
2211 break;
2212 }
2213 }
2214 }
2215
2216 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2217 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2218 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2219 NL_SET_ERR_MSG_MOD(extack,
2220 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2221 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2222 return false;
2223 }
2224
2225out_ok:
2226 return true;
2227}
2228
2229static bool actions_match_supported(struct mlx5e_priv *priv,
2230 struct tcf_exts *exts,
2231 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2232 struct mlx5e_tc_flow *flow,
2233 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2234{
2235 u32 actions;
2236
2237 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2238 actions = flow->esw_attr->action;
2239 else
2240 actions = flow->nic_attr->action;
2241
7e29392e
RD		 2242 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2243 !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2244 return false;
2245
bdd66ac0 2246 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
e98bedf5
EB		 2247 return modify_header_match_supported(&parse_attr->spec, exts,
2248 extack);
bdd66ac0
OG		 2249
2250 return true;
2251}
2252
5c65c564
OG		 2253static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2254{
2255 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2256 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2257
2258 fmdev = priv->mdev;
2259 pmdev = peer_priv->mdev;
2260
59c9d35e
AH		 2261 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2262 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2263
816f6706 2264 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2265}
2266
5c40348c 2267static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae 2268 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2269 struct mlx5e_tc_flow *flow,
2270 struct netlink_ext_ack *extack)
e3a2b7ed 2271{
aa0cbbae 2272 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 2273 const struct tc_action *a;
1cab1cd7 2274 u32 action = 0;
244cd96a 2275 int err, i;
e3a2b7ed 2276
3bcc0cec 2277 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 2278 return -EINVAL;
2279
3bc4b7bf 2280 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2281
244cd96a 2282 tcf_exts_for_each_action(i, a, exts) {
e3a2b7ed 2283 if (is_tcf_gact_shot(a)) {
1cab1cd7 2284 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2285 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2286 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2287 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 2288 continue;
2289 }
2290
2f4fe4ca
OG		 2291 if (is_tcf_pedit(a)) {
2292 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
e98bedf5 2293 parse_attr, extack);
2f4fe4ca
OG		 2294 if (err)
2295 return err;
2296
1cab1cd7
OG		 2297 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2298 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2f4fe4ca
OG		 2299 continue;
2300 }
2301
26c02749 2302 if (is_tcf_csum(a)) {
1cab1cd7 2303 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2304 tcf_csum_update_flags(a),
2305 extack))
26c02749
OG		 2306 continue;
2307
2308 return -EOPNOTSUPP;
2309 }
2310
5c65c564
OG		 2311 if (is_tcf_mirred_egress_redirect(a)) {
2312 struct net_device *peer_dev = tcf_mirred_dev(a);
2313
2314 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2315 same_hw_devs(priv, netdev_priv(peer_dev))) {
98b66cb1 2316 parse_attr->mirred_ifindex[0] = peer_dev->ifindex;
5c65c564 2317 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 2318 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2319 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2320 } else {
e98bedf5
EB		 2321 NL_SET_ERR_MSG_MOD(extack,
2322 "device is not on same HW, can't offload");
5c65c564
OG		 2323 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2324 peer_dev->name);
2325 return -EINVAL;
2326 }
2327 continue;
2328 }
2329
e3a2b7ed
AV		 2330 if (is_tcf_skbedit_mark(a)) {
2331 u32 mark = tcf_skbedit_mark(a);
2332
2333 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2334 NL_SET_ERR_MSG_MOD(extack,
2335 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2336 return -EINVAL;
2337 }
2338
3bc4b7bf 2339 attr->flow_tag = mark;
1cab1cd7 2340 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 2341 continue;
2342 }
2343
2344 return -EINVAL;
2345 }
2346
1cab1cd7 2347 attr->action = action;
e98bedf5 2348 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2349 return -EOPNOTSUPP;
2350
e3a2b7ed
AV		 2351 return 0;
2352}
2353
76f7444d
OG		 2354static inline int cmp_encap_info(struct ip_tunnel_key *a,
2355 struct ip_tunnel_key *b)
a54e20b4
HHZ		 2356{
2357 return memcmp(a, b, sizeof(*a));
2358}
2359
76f7444d 2360static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2361{
76f7444d 2362 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2363}
2364
a54e20b4 2365
b1d90e6b
RL		 2366static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2367 struct net_device *peer_netdev)
2368{
2369 struct mlx5e_priv *peer_priv;
2370
2371 peer_priv = netdev_priv(peer_netdev);
2372
2373 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2374 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2375 same_hw_devs(priv, peer_priv) &&
2376 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2377 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2378}
2379
32f3671f 2380
f5bc2c5d 2381
a54e20b4
HHZ		 2382static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2383 struct ip_tunnel_info *tun_info,
2384 struct net_device *mirred_dev,
45247bf2 2385 struct net_device **encap_dev,
e98bedf5 2386 struct mlx5e_tc_flow *flow,
8c4dc42b
EB		 2387 struct netlink_ext_ack *extack,
2388 int out_index)
a54e20b4
HHZ		 2389{
2390 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2391 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2 2392 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2393 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2394 struct mlx5e_encap_entry *e;
a54e20b4
HHZ		 2395 uintptr_t hash_key;
2396 bool found = false;
54c177ca 2397 int err = 0;
a54e20b4 2398
76f7444d 2399 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2400
2401 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2402 encap_hlist, hash_key) {
76f7444d 2403 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2404 found = true;
2405 break;
2406 }
2407 }
2408
b2812089 2409 /* must verify if encap is valid or not */
45247bf2
OG		 2410 if (found)
2411 goto attach_flow;
a54e20b4
HHZ		 2412
2413 e = kzalloc(sizeof(*e), GFP_KERNEL);
2414 if (!e)
2415 return -ENOMEM;
2416
76f7444d 2417 e->tun_info = *tun_info;
101f4de9 2418 err = mlx5e_tc_tun_init_encap_attr(mirred_dev, priv, e, extack);
54c177ca
OS		 2419 if (err)
2420 goto out_err;
2421
a54e20b4
HHZ		 2422 INIT_LIST_HEAD(&e->flows);
2423
ce99f6b9 2424 if (family == AF_INET)
101f4de9 2425 err = mlx5e_tc_tun_create_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2426 else if (family == AF_INET6)
101f4de9 2427 err = mlx5e_tc_tun_create_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2428
232c0013 2429 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2430 goto out_err;
2431
a54e20b4
HHZ		 2432 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2433
45247bf2 2434attach_flow:
8c4dc42b
EB		 2435 list_add(&flow->encaps[out_index].list, &e->flows);
2436 flow->encaps[out_index].index = out_index;
45247bf2 2437 *encap_dev = e->out_dev;
8c4dc42b
EB		 2438 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
2439 attr->dests[out_index].encap_id = e->encap_id;
2440 attr->dests[out_index].flags |= MLX5_ESW_DEST_ENCAP_VALID;
2441 } else {
b2812089 2442 err = -EAGAIN;
8c4dc42b 2443 }
45247bf2 2444
232c0013 2445 return err;
a54e20b4
HHZ		 2446
2447out_err:
2448 kfree(e);
2449 return err;
2450}
2451
1482bd3d
JL		 2452static int parse_tc_vlan_action(struct mlx5e_priv *priv,
2453 const struct tc_action *a,
2454 struct mlx5_esw_flow_attr *attr,
2455 u32 *action)
2456{
cc495188
JL		 2457 u8 vlan_idx = attr->total_vlan;
2458
2459 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2460 return -EOPNOTSUPP;
2461
1482bd3d 2462 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
cc495188
JL		 2463 if (vlan_idx) {
2464 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2465 MLX5_FS_VLAN_DEPTH))
2466 return -EOPNOTSUPP;
2467
2468 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2469 } else {
2470 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2471 }
1482bd3d 2472 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
cc495188
JL		 2473 attr->vlan_vid[vlan_idx] = tcf_vlan_push_vid(a);
2474 attr->vlan_prio[vlan_idx] = tcf_vlan_push_prio(a);
2475 attr->vlan_proto[vlan_idx] = tcf_vlan_push_proto(a);
2476 if (!attr->vlan_proto[vlan_idx])
2477 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2478
2479 if (vlan_idx) {
2480 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2481 MLX5_FS_VLAN_DEPTH))
2482 return -EOPNOTSUPP;
2483
2484 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2485 } else {
2486 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
2487 (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2488 tcf_vlan_push_prio(a)))
2489 return -EOPNOTSUPP;
2490
2491 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d
JL		 2492 }
2493 } else { /* action is TCA_VLAN_ACT_MODIFY */
2494 return -EOPNOTSUPP;
2495 }
2496
cc495188
JL		 2497 attr->total_vlan = vlan_idx + 1;
2498
1482bd3d
JL		 2499 return 0;
2500}
2501
03a9d11e 2502static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 2503 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2504 struct mlx5e_tc_flow *flow,
2505 struct netlink_ext_ack *extack)
03a9d11e 2506{
bf07aa73 2507 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2508 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2509 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 2510 struct ip_tunnel_info *info = NULL;
03a9d11e 2511 const struct tc_action *a;
a54e20b4 2512 bool encap = false;
1cab1cd7 2513 u32 action = 0;
244cd96a 2514 int err, i;
03a9d11e 2515
3bcc0cec 2516 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 2517 return -EINVAL;
2518
1d447a39 2519 attr->in_rep = rpriv->rep;
10ff5359 2520 attr->in_mdev = priv->mdev;
03a9d11e 2521
244cd96a 2522 tcf_exts_for_each_action(i, a, exts) {
03a9d11e 2523 if (is_tcf_gact_shot(a)) {
1cab1cd7
OG		 2524 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2525 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 2526 continue;
2527 }
2528
d7e75a32
OG		 2529 if (is_tcf_pedit(a)) {
2530 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
e98bedf5 2531 parse_attr, extack);
d7e75a32
OG		 2532 if (err)
2533 return err;
2534
1cab1cd7 2535 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
e85e02ba 2536 attr->split_count = attr->out_count;
d7e75a32
OG		 2537 continue;
2538 }
2539
26c02749 2540 if (is_tcf_csum(a)) {
1cab1cd7 2541 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2542 tcf_csum_update_flags(a),
2543 extack))
26c02749
OG		 2544 continue;
2545
2546 return -EOPNOTSUPP;
2547 }
2548
592d3651 2549 if (is_tcf_mirred_egress_redirect(a) || is_tcf_mirred_egress_mirror(a)) {
03a9d11e 2550 struct mlx5e_priv *out_priv;
592d3651 2551 struct net_device *out_dev;
03a9d11e 2552
9f8a739e 2553 out_dev = tcf_mirred_dev(a);
ef381359
OS		 2554 if (!out_dev) {
2555 /* out_dev is NULL when filters with
2556 * non-existing mirred device are replayed to
2557 * the driver.
2558 */
2559 return -EINVAL;
2560 }
03a9d11e 2561
592d3651 2562 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2563 NL_SET_ERR_MSG_MOD(extack,
2564 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2565 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2566 attr->out_count);
2567 return -EOPNOTSUPP;
2568 }
2569
f493f155
EB		 2570 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2571 MLX5_FLOW_CONTEXT_ACTION_COUNT;
a54e20b4 2572 if (switchdev_port_same_parent_id(priv->netdev,
b1d90e6b
RL		 2573 out_dev) ||
2574 is_merged_eswitch_dev(priv, out_dev)) {
7ba58ba7
RL		 2575 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2576 struct net_device *uplink_dev = mlx5_eswitch_uplink_get_proto_dev(esw, REP_ETH);
2577 struct net_device *uplink_upper = netdev_master_upper_dev_get(uplink_dev);
2578
2579 if (uplink_upper &&
2580 netif_is_lag_master(uplink_upper) &&
2581 uplink_upper == out_dev)
2582 out_dev = uplink_dev;
2583
a0646c88
EB		 2584 if (!mlx5e_eswitch_rep(out_dev))
2585 return -EOPNOTSUPP;
2586
a54e20b4 2587 out_priv = netdev_priv(out_dev);
1d447a39 2588 rpriv = out_priv->ppriv;
df65a573
EB		 2589 attr->dests[attr->out_count].rep = rpriv->rep;
2590 attr->dests[attr->out_count].mdev = out_priv->mdev;
2591 attr->out_count++;
a54e20b4 2592 } else if (encap) {
8c4dc42b
EB		 2593 parse_attr->mirred_ifindex[attr->out_count] =
2594 out_dev->ifindex;
2595 parse_attr->tun_info[attr->out_count] = *info;
2596 encap = false;
3c37745e 2597 attr->parse_attr = parse_attr;
f493f155
EB		 2598 attr->dests[attr->out_count].flags |=
2599 MLX5_ESW_DEST_ENCAP;
1cc26d74 2600 attr->out_count++;
df65a573
EB		 2601 /* attr->dests[].rep is resolved when we
2602 * handle encap
2603 */
ef381359
OS		 2604 } else if (parse_attr->filter_dev != priv->netdev) {
2605 /* All mlx5 devices are called to configure
2606 * high level device filters. Therefore, the
2607 * *attempt* to install a filter on invalid
2608 * eswitch should not trigger an explicit error
2609 */
2610 return -EINVAL;
a54e20b4 2611 } else {
e98bedf5
EB		 2612 NL_SET_ERR_MSG_MOD(extack,
2613 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 2614 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2615 priv->netdev->name, out_dev->name);
2616 return -EINVAL;
2617 }
a54e20b4
HHZ		 2618 continue;
2619 }
03a9d11e 2620
a54e20b4
HHZ		 2621 if (is_tcf_tunnel_set(a)) {
2622 info = tcf_tunnel_info(a);
2623 if (info)
2624 encap = true;
2625 else
2626 return -EOPNOTSUPP;
03a9d11e
OG		 2627 continue;
2628 }
2629
8b32580d 2630 if (is_tcf_vlan(a)) {
1482bd3d
JL		 2631 err = parse_tc_vlan_action(priv, a, attr, &action);
2632
2633 if (err)
2634 return err;
2635
e85e02ba 2636 attr->split_count = attr->out_count;
8b32580d
OG		 2637 continue;
2638 }
2639
bbd00f7e 2640 if (is_tcf_tunnel_release(a)) {
1cab1cd7 2641 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bbd00f7e
HHZ		 2642 continue;
2643 }
2644
bf07aa73
PB		 2645 if (is_tcf_gact_goto_chain(a)) {
2646 u32 dest_chain = tcf_gact_goto_chain_index(a);
2647 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
2648
2649 if (dest_chain <= attr->chain) {
2650 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
2651 return -EOPNOTSUPP;
2652 }
2653 if (dest_chain > max_chain) {
2654 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
2655 return -EOPNOTSUPP;
2656 }
e88afe75 2657 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73
PB		 2658 attr->dest_chain = dest_chain;
2659
2660 continue;
2661 }
2662
03a9d11e
OG		 2663 return -EINVAL;
2664 }
bdd66ac0 2665
1cab1cd7 2666 attr->action = action;
e98bedf5 2667 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2668 return -EOPNOTSUPP;
2669
e88afe75
OG		 2670 if (attr->dest_chain) {
2671 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
2672 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
2673 return -EOPNOTSUPP;
2674 }
2675 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2676 }
2677
e85e02ba 2678 if (attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 2679 NL_SET_ERR_MSG_MOD(extack,
2680 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 2681 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2682 return -EOPNOTSUPP;
2683 }
2684
31c8eba5 2685 return 0;
03a9d11e
OG		 2686}
2687
5dbe906f 2688static void get_flags(int flags, u16 *flow_flags)
60bd4af8 2689{
5dbe906f 2690 u16 __flow_flags = 0;
60bd4af8
OG		 2691
2692 if (flags & MLX5E_TC_INGRESS)
2693 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2694 if (flags & MLX5E_TC_EGRESS)
2695 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
2696
d9ee0491
OG		 2697 if (flags & MLX5E_TC_ESW_OFFLOAD)
2698 __flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2699 if (flags & MLX5E_TC_NIC_OFFLOAD)
2700 __flow_flags |= MLX5E_TC_FLOW_NIC;
2701
60bd4af8
OG		 2702 *flow_flags = __flow_flags;
2703}
2704
05866c82
OG		 2705static const struct rhashtable_params tc_ht_params = {
2706 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2707 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2708 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2709 .automatic_shrinking = true,
2710};
2711
d9ee0491 2712static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv, int flags)
05866c82 2713{
655dc3d2
OG		 2714 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2715 struct mlx5e_rep_priv *uplink_rpriv;
2716
d9ee0491 2717 if (flags & MLX5E_TC_ESW_OFFLOAD) {
655dc3d2 2718 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ec1366c2 2719 return &uplink_rpriv->uplink_priv.tc_ht;
d9ee0491 2720 } else /* NIC offload */
655dc3d2 2721 return &priv->fs.tc.ht;
05866c82
OG		 2722}
2723
04de7dda
RD		 2724static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
2725{
1418ddd9
AH		 2726 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
2727 bool is_rep_ingress = attr->in_rep->vport != FDB_UPLINK_VPORT &&
2728 flow->flags & MLX5E_TC_FLOW_INGRESS;
2729 bool act_is_encap = !!(attr->action &
2730 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
2731 bool esw_paired = mlx5_devcom_is_paired(attr->in_mdev->priv.devcom,
2732 MLX5_DEVCOM_ESW_OFFLOADS);
2733
7c34ec19 2734 return esw_paired && mlx5_lag_is_sriov(attr->in_mdev) &&
1418ddd9 2735 (is_rep_ingress || act_is_encap);
04de7dda
RD		 2736}
2737
a88780a9
RD		 2738static int
2739mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
5dbe906f 2740 struct tc_cls_flower_offload *f, u16 flow_flags,
a88780a9
RD		 2741 struct mlx5e_tc_flow_parse_attr **__parse_attr,
2742 struct mlx5e_tc_flow **__flow)
e3a2b7ed 2743{
17091853 2744 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 2745 struct mlx5e_tc_flow *flow;
a88780a9 2746 int err;
e3a2b7ed 2747
65ba8fb7 2748 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2749 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2750 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2751 err = -ENOMEM;
2752 goto err_free;
2753 }
2754
2755 flow->cookie = f->cookie;
65ba8fb7 2756 flow->flags = flow_flags;
655dc3d2 2757 flow->priv = priv;
e3a2b7ed 2758
a88780a9
RD		 2759 *__flow = flow;
2760 *__parse_attr = parse_attr;
2761
2762 return 0;
2763
2764err_free:
2765 kfree(flow);
2766 kvfree(parse_attr);
2767 return err;
2768}
2769
2770static int
04de7dda
RD		 2771__mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
2772 struct tc_cls_flower_offload *f,
2773 u16 flow_flags,
2774 struct net_device *filter_dev,
2775 struct mlx5_eswitch_rep *in_rep,
2776 struct mlx5_core_dev *in_mdev,
2777 struct mlx5e_tc_flow **__flow)
a88780a9
RD		 2778{
2779 struct netlink_ext_ack *extack = f->common.extack;
f9392795 2780 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a88780a9
RD		 2781 struct mlx5e_tc_flow_parse_attr *parse_attr;
2782 struct mlx5e_tc_flow *flow;
2783 int attr_size, err;
e3a2b7ed 2784
a88780a9
RD		 2785 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
2786 attr_size = sizeof(struct mlx5_esw_flow_attr);
2787 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
2788 &parse_attr, &flow);
2789 if (err)
2790 goto out;
d11afc26
OS		 2791 parse_attr->filter_dev = filter_dev;
2792 flow->esw_attr->parse_attr = parse_attr;
54c177ca
OS		 2793 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
2794 f, filter_dev);
d11afc26
OS		 2795 if (err)
2796 goto err_free;
a88780a9 2797
bf07aa73
PB		 2798 flow->esw_attr->chain = f->common.chain_index;
2799 flow->esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
a88780a9
RD		 2800 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow, extack);
2801 if (err)
2802 goto err_free;
2803
04de7dda
RD		 2804 flow->esw_attr->in_rep = in_rep;
2805 flow->esw_attr->in_mdev = in_mdev;
f9392795
SK		 2806
2807 if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
2808 MLX5_COUNTER_SOURCE_ESWITCH)
2809 flow->esw_attr->counter_dev = in_mdev;
2810 else
2811 flow->esw_attr->counter_dev = priv->mdev;
2812
a88780a9 2813 err = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow, extack);
5dbe906f 2814 if (err)
c83954ab 2815 goto err_free;
e3a2b7ed 2816
a88780a9 2817 *__flow = flow;
5c40348c 2818
a88780a9
RD		 2819 return 0;
2820
2821err_free:
2822 kfree(flow);
2823 kvfree(parse_attr);
2824out:
232c0013 2825 return err;
a88780a9
RD		 2826}
2827
04de7dda
RD		 2828static int mlx5e_tc_add_fdb_peer_flow(struct tc_cls_flower_offload *f,
2829 struct mlx5e_tc_flow *flow)
2830{
2831 struct mlx5e_priv *priv = flow->priv, *peer_priv;
2832 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch, *peer_esw;
2833 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
2834 struct mlx5e_tc_flow_parse_attr *parse_attr;
2835 struct mlx5e_rep_priv *peer_urpriv;
2836 struct mlx5e_tc_flow *peer_flow;
2837 struct mlx5_core_dev *in_mdev;
2838 int err = 0;
2839
2840 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2841 if (!peer_esw)
2842 return -ENODEV;
2843
2844 peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
2845 peer_priv = netdev_priv(peer_urpriv->netdev);
2846
2847 /* in_mdev is assigned of which the packet originated from.
2848 * So packets redirected to uplink use the same mdev of the
2849 * original flow and packets redirected from uplink use the
2850 * peer mdev.
2851 */
2852 if (flow->esw_attr->in_rep->vport == FDB_UPLINK_VPORT)
2853 in_mdev = peer_priv->mdev;
2854 else
2855 in_mdev = priv->mdev;
2856
2857 parse_attr = flow->esw_attr->parse_attr;
2858 err = __mlx5e_add_fdb_flow(peer_priv, f, flow->flags,
2859 parse_attr->filter_dev,
2860 flow->esw_attr->in_rep, in_mdev, &peer_flow);
2861 if (err)
2862 goto out;
2863
2864 flow->peer_flow = peer_flow;
2865 flow->flags |= MLX5E_TC_FLOW_DUP;
2866 mutex_lock(&esw->offloads.peer_mutex);
2867 list_add_tail(&flow->peer, &esw->offloads.peer_flows);
2868 mutex_unlock(&esw->offloads.peer_mutex);
2869
2870out:
2871 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
2872 return err;
2873}
2874
2875static int
2876mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
2877 struct tc_cls_flower_offload *f,
2878 u16 flow_flags,
2879 struct net_device *filter_dev,
2880 struct mlx5e_tc_flow **__flow)
2881{
2882 struct mlx5e_rep_priv *rpriv = priv->ppriv;
2883 struct mlx5_eswitch_rep *in_rep = rpriv->rep;
2884 struct mlx5_core_dev *in_mdev = priv->mdev;
2885 struct mlx5e_tc_flow *flow;
2886 int err;
2887
2888 err = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
2889 in_mdev, &flow);
2890 if (err)
2891 goto out;
2892
2893 if (is_peer_flow_needed(flow)) {
2894 err = mlx5e_tc_add_fdb_peer_flow(f, flow);
2895 if (err) {
2896 mlx5e_tc_del_fdb_flow(priv, flow);
2897 goto out;
2898 }
2899 }
2900
2901 *__flow = flow;
2902
2903 return 0;
2904
2905out:
2906 return err;
2907}
2908
a88780a9
RD		 2909static int
2910mlx5e_add_nic_flow(struct mlx5e_priv *priv,
2911 struct tc_cls_flower_offload *f,
5dbe906f 2912 u16 flow_flags,
d11afc26 2913 struct net_device *filter_dev,
a88780a9
RD		 2914 struct mlx5e_tc_flow **__flow)
2915{
2916 struct netlink_ext_ack *extack = f->common.extack;
2917 struct mlx5e_tc_flow_parse_attr *parse_attr;
2918 struct mlx5e_tc_flow *flow;
2919 int attr_size, err;
2920
bf07aa73
PB		 2921 /* multi-chain not supported for NIC rules */
2922 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
2923 return -EOPNOTSUPP;
2924
a88780a9
RD		 2925 flow_flags |= MLX5E_TC_FLOW_NIC;
2926 attr_size = sizeof(struct mlx5_nic_flow_attr);
2927 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
2928 &parse_attr, &flow);
2929 if (err)
2930 goto out;
2931
d11afc26 2932 parse_attr->filter_dev = filter_dev;
54c177ca
OS		 2933 err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
2934 f, filter_dev);
d11afc26
OS		 2935 if (err)
2936 goto err_free;
2937
a88780a9
RD		 2938 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow, extack);
2939 if (err)
2940 goto err_free;
2941
2942 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
2943 if (err)
2944 goto err_free;
2945
2946 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2947 kvfree(parse_attr);
2948 *__flow = flow;
2949
2950 return 0;
e3a2b7ed 2951
e3a2b7ed 2952err_free:
a88780a9 2953 kfree(flow);
17091853 2954 kvfree(parse_attr);
a88780a9
RD		 2955out:
2956 return err;
2957}
2958
2959static int
2960mlx5e_tc_add_flow(struct mlx5e_priv *priv,
2961 struct tc_cls_flower_offload *f,
2962 int flags,
d11afc26 2963 struct net_device *filter_dev,
a88780a9
RD		 2964 struct mlx5e_tc_flow **flow)
2965{
2966 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 2967 u16 flow_flags;
a88780a9
RD		 2968 int err;
2969
2970 get_flags(flags, &flow_flags);
2971
bf07aa73
PB		 2972 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
2973 return -EOPNOTSUPP;
2974
a88780a9 2975 if (esw && esw->mode == SRIOV_OFFLOADS)
d11afc26
OS		 2976 err = mlx5e_add_fdb_flow(priv, f, flow_flags,
2977 filter_dev, flow);
a88780a9 2978 else
d11afc26
OS		 2979 err = mlx5e_add_nic_flow(priv, f, flow_flags,
2980 filter_dev, flow);
a88780a9
RD		 2981
2982 return err;
2983}
2984
71d82d2a 2985int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
a88780a9
RD		 2986 struct tc_cls_flower_offload *f, int flags)
2987{
2988 struct netlink_ext_ack *extack = f->common.extack;
d9ee0491 2989 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
a88780a9
RD		 2990 struct mlx5e_tc_flow *flow;
2991 int err = 0;
2992
2993 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2994 if (flow) {
2995 NL_SET_ERR_MSG_MOD(extack,
2996 "flow cookie already exists, ignoring");
2997 netdev_warn_once(priv->netdev,
2998 "flow cookie %lx already exists, ignoring\n",
2999 f->cookie);
3000 goto out;
3001 }
3002
d11afc26 3003 err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
a88780a9
RD		 3004 if (err)
3005 goto out;
3006
3007 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
3008 if (err)
3009 goto err_free;
3010
3011 return 0;
3012
3013err_free:
3014 mlx5e_tc_del_flow(priv, flow);
232c0013 3015 kfree(flow);
a88780a9 3016out:
e3a2b7ed
AV		 3017 return err;
3018}
3019
8f8ae895
OG		 3020#define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
3021#define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
3022
3023static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3024{
3025 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
3026 return true;
3027
3028 return false;
3029}
3030
71d82d2a 3031int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 3032 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 3033{
d9ee0491 3034 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
e3a2b7ed 3035 struct mlx5e_tc_flow *flow;
e3a2b7ed 3036
05866c82 3037 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3038 if (!flow || !same_flow_direction(flow, flags))
e3a2b7ed
AV		 3039 return -EINVAL;
3040
05866c82 3041 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
e3a2b7ed 3042
961e8979 3043 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 3044
3045 kfree(flow);
3046
3047 return 0;
3048}
3049
71d82d2a 3050int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
60bd4af8 3051 struct tc_cls_flower_offload *f, int flags)
aad7e08d 3052{
04de7dda 3053 struct mlx5_devcom *devcom = priv->mdev->priv.devcom;
d9ee0491 3054 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
04de7dda 3055 struct mlx5_eswitch *peer_esw;
aad7e08d 3056 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 3057 struct mlx5_fc *counter;
3058 u64 bytes;
3059 u64 packets;
3060 u64 lastuse;
3061
05866c82 3062 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3063 if (!flow || !same_flow_direction(flow, flags))
aad7e08d
AV		 3064 return -EINVAL;
3065
0b67a38f
HHZ		 3066 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
3067 return 0;
3068
b8aee822 3069 counter = mlx5e_tc_get_counter(flow);
aad7e08d
AV		 3070 if (!counter)
3071 return 0;
3072
3073 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3074
04de7dda
RD		 3075 peer_esw = mlx5_devcom_get_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3076 if (!peer_esw)
3077 goto out;
3078
3079 if ((flow->flags & MLX5E_TC_FLOW_DUP) &&
3080 (flow->peer_flow->flags & MLX5E_TC_FLOW_OFFLOADED)) {
3081 u64 bytes2;
3082 u64 packets2;
3083 u64 lastuse2;
3084
3085 counter = mlx5e_tc_get_counter(flow->peer_flow);
3086 mlx5_fc_query_cached(counter, &bytes2, &packets2, &lastuse2);
3087
3088 bytes += bytes2;
3089 packets += packets2;
3090 lastuse = max_t(u64, lastuse, lastuse2);
3091 }
3092
3093 mlx5_devcom_release_peer_data(devcom, MLX5_DEVCOM_ESW_OFFLOADS);
3094
3095out:
d897a638 3096 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 3097
aad7e08d
AV		 3098 return 0;
3099}
3100
4d8fcf21
AH		 3101static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3102 struct mlx5e_priv *peer_priv)
3103{
3104 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3105 struct mlx5e_hairpin_entry *hpe;
3106 u16 peer_vhca_id;
3107 int bkt;
3108
3109 if (!same_hw_devs(priv, peer_priv))
3110 return;
3111
3112 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3113
3114 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3115 if (hpe->peer_vhca_id == peer_vhca_id)
3116 hpe->hp->pair->peer_gone = true;
3117 }
3118}
3119
3120static int mlx5e_tc_netdev_event(struct notifier_block *this,
3121 unsigned long event, void *ptr)
3122{
3123 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3124 struct mlx5e_flow_steering *fs;
3125 struct mlx5e_priv *peer_priv;
3126 struct mlx5e_tc_table *tc;
3127 struct mlx5e_priv *priv;
3128
3129 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3130 event != NETDEV_UNREGISTER ||
3131 ndev->reg_state == NETREG_REGISTERED)
3132 return NOTIFY_DONE;
3133
3134 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3135 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3136 priv = container_of(fs, struct mlx5e_priv, fs);
3137 peer_priv = netdev_priv(ndev);
3138 if (priv == peer_priv ||
3139 !(priv->netdev->features & NETIF_F_HW_TC))
3140 return NOTIFY_DONE;
3141
3142 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3143
3144 return NOTIFY_DONE;
3145}
3146
655dc3d2 3147int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3148{
acff797c 3149 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3150 int err;
e8f887ac 3151
11c9c548 3152 hash_init(tc->mod_hdr_tbl);
5c65c564 3153 hash_init(tc->hairpin_tbl);
11c9c548 3154
4d8fcf21
AH		 3155 err = rhashtable_init(&tc->ht, &tc_ht_params);
3156 if (err)
3157 return err;
3158
3159 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3160 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3161 tc->netdevice_nb.notifier_call = NULL;
3162 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3163 }
3164
3165 return err;
e8f887ac
AV		 3166}
3167
3168static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3169{
3170 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3171 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3172
961e8979 3173 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3174 kfree(flow);
3175}
3176
655dc3d2 3177void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3178{
acff797c 3179 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3180
4d8fcf21
AH		 3181 if (tc->netdevice_nb.notifier_call)
3182 unregister_netdevice_notifier(&tc->netdevice_nb);
3183
d9ee0491 3184 rhashtable_destroy(&tc->ht);
e8f887ac 3185
acff797c
MG		 3186 if (!IS_ERR_OR_NULL(tc->t)) {
3187 mlx5_destroy_flow_table(tc->t);
3188 tc->t = NULL;
e8f887ac
AV		 3189 }
3190}
655dc3d2
OG		 3191
3192int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3193{
3194 return rhashtable_init(tc_ht, &tc_ht_params);
3195}
3196
3197void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3198{
3199 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3200}
01252a27 3201
d9ee0491 3202int mlx5e_tc_num_filters(struct mlx5e_priv *priv, int flags)
01252a27 3203{
d9ee0491 3204 struct rhashtable *tc_ht = get_tc_ht(priv, flags);
01252a27
OG		 3205
3206 return atomic_read(&tc_ht->nelems);
3207}
04de7dda
RD		 3208
3209void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
3210{
3211 struct mlx5e_tc_flow *flow, *tmp;
3212
3213 list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows, peer)
3214 __mlx5e_tc_del_fdb_peer_flow(flow);
3215}
Linux 6.x block layer and io_uring tree(s)