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net/mlx5e: Get the required HW match level while parsing TC flow matches
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
bbd00f7e 53#include "vxlan.h"
3f6d08d1 54#include "fs_core.h"
e8f887ac 55
3bc4b7bf
OG		 56struct mlx5_nic_flow_attr {
57 u32 action;
58 u32 flow_tag;
2f4fe4ca 59 u32 mod_hdr_id;
5c65c564 60 u32 hairpin_tirn;
3f6d08d1 61 struct mlx5_flow_table *hairpin_ft;
3bc4b7bf
OG		 62};
63
65ba8fb7
OG		 64enum {
65 MLX5E_TC_FLOW_ESWITCH = BIT(0),
3bc4b7bf 66 MLX5E_TC_FLOW_NIC = BIT(1),
0b67a38f 67 MLX5E_TC_FLOW_OFFLOADED = BIT(2),
5c65c564 68 MLX5E_TC_FLOW_HAIRPIN = BIT(3),
3f6d08d1 69 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(4),
65ba8fb7
OG		 70};
71
e8f887ac
AV		 72struct mlx5e_tc_flow {
73 struct rhash_head node;
74 u64 cookie;
65ba8fb7 75 u8 flags;
74491de9 76 struct mlx5_flow_handle *rule;
11c9c548
OG		 77 struct list_head encap; /* flows sharing the same encap ID */
78 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 79 struct list_head hairpin; /* flows sharing the same hairpin */
3bc4b7bf
OG		 80 union {
81 struct mlx5_esw_flow_attr esw_attr[0];
82 struct mlx5_nic_flow_attr nic_attr[0];
83 };
e8f887ac
AV		 84};
85
17091853 86struct mlx5e_tc_flow_parse_attr {
3c37745e 87 struct ip_tunnel_info tun_info;
17091853 88 struct mlx5_flow_spec spec;
d79b6df6
OG		 89 int num_mod_hdr_actions;
90 void *mod_hdr_actions;
3c37745e 91 int mirred_ifindex;
17091853
OG		 92};
93
a54e20b4
HHZ		 94enum {
95 MLX5_HEADER_TYPE_VXLAN = 0x0,
96 MLX5_HEADER_TYPE_NVGRE = 0x1,
97};
98
acff797c 99#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 100#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 101
77ab67b7
OG		 102struct mlx5e_hairpin {
103 struct mlx5_hairpin *pair;
104
105 struct mlx5_core_dev *func_mdev;
3f6d08d1 106 struct mlx5e_priv *func_priv;
77ab67b7
OG		 107 u32 tdn;
108 u32 tirn;
3f6d08d1
OG		 109
110 int num_channels;
111 struct mlx5e_rqt indir_rqt;
112 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
113 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 114};
115
5c65c564
OG		 116struct mlx5e_hairpin_entry {
117 /* a node of a hash table which keeps all the hairpin entries */
118 struct hlist_node hairpin_hlist;
119
120 /* flows sharing the same hairpin */
121 struct list_head flows;
122
d8822868 123 u16 peer_vhca_id;
106be53b 124 u8 prio;
5c65c564
OG		 125 struct mlx5e_hairpin *hp;
126};
127
11c9c548
OG		 128struct mod_hdr_key {
129 int num_actions;
130 void *actions;
131};
132
133struct mlx5e_mod_hdr_entry {
134 /* a node of a hash table which keeps all the mod_hdr entries */
135 struct hlist_node mod_hdr_hlist;
136
137 /* flows sharing the same mod_hdr entry */
138 struct list_head flows;
139
140 struct mod_hdr_key key;
141
142 u32 mod_hdr_id;
143};
144
145#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
146
147static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
148{
149 return jhash(key->actions,
150 key->num_actions * MLX5_MH_ACT_SZ, 0);
151}
152
153static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
154 struct mod_hdr_key *b)
155{
156 if (a->num_actions != b->num_actions)
157 return 1;
158
159 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
160}
161
162static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
163 struct mlx5e_tc_flow *flow,
164 struct mlx5e_tc_flow_parse_attr *parse_attr)
165{
166 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
167 int num_actions, actions_size, namespace, err;
168 struct mlx5e_mod_hdr_entry *mh;
169 struct mod_hdr_key key;
170 bool found = false;
171 u32 hash_key;
172
173 num_actions = parse_attr->num_mod_hdr_actions;
174 actions_size = MLX5_MH_ACT_SZ * num_actions;
175
176 key.actions = parse_attr->mod_hdr_actions;
177 key.num_actions = num_actions;
178
179 hash_key = hash_mod_hdr_info(&key);
180
181 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
182 namespace = MLX5_FLOW_NAMESPACE_FDB;
183 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
184 mod_hdr_hlist, hash_key) {
185 if (!cmp_mod_hdr_info(&mh->key, &key)) {
186 found = true;
187 break;
188 }
189 }
190 } else {
191 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
192 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
193 mod_hdr_hlist, hash_key) {
194 if (!cmp_mod_hdr_info(&mh->key, &key)) {
195 found = true;
196 break;
197 }
198 }
199 }
200
201 if (found)
202 goto attach_flow;
203
204 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
205 if (!mh)
206 return -ENOMEM;
207
208 mh->key.actions = (void *)mh + sizeof(*mh);
209 memcpy(mh->key.actions, key.actions, actions_size);
210 mh->key.num_actions = num_actions;
211 INIT_LIST_HEAD(&mh->flows);
212
213 err = mlx5_modify_header_alloc(priv->mdev, namespace,
214 mh->key.num_actions,
215 mh->key.actions,
216 &mh->mod_hdr_id);
217 if (err)
218 goto out_err;
219
220 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
221 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
222 else
223 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
224
225attach_flow:
226 list_add(&flow->mod_hdr, &mh->flows);
227 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
228 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
229 else
230 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
231
232 return 0;
233
234out_err:
235 kfree(mh);
236 return err;
237}
238
239static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
240 struct mlx5e_tc_flow *flow)
241{
242 struct list_head *next = flow->mod_hdr.next;
243
244 list_del(&flow->mod_hdr);
245
246 if (list_empty(next)) {
247 struct mlx5e_mod_hdr_entry *mh;
248
249 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
250
251 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
252 hash_del(&mh->mod_hdr_hlist);
253 kfree(mh);
254 }
255}
256
77ab67b7
OG		 257static
258struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
259{
260 struct net_device *netdev;
261 struct mlx5e_priv *priv;
262
263 netdev = __dev_get_by_index(net, ifindex);
264 priv = netdev_priv(netdev);
265 return priv->mdev;
266}
267
268static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
269{
270 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
271 void *tirc;
272 int err;
273
274 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
275 if (err)
276 goto alloc_tdn_err;
277
278 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
279
280 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 281 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 282 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
283
284 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
285 if (err)
286 goto create_tir_err;
287
288 return 0;
289
290create_tir_err:
291 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
292alloc_tdn_err:
293 return err;
294}
295
296static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
297{
298 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
299 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
300}
301
3f6d08d1
OG		 302static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
303{
304 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
305 struct mlx5e_priv *priv = hp->func_priv;
306 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
307
308 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
309 hp->num_channels);
310
311 for (i = 0; i < sz; i++) {
312 ix = i;
313 if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR)
314 ix = mlx5e_bits_invert(i, ilog2(sz));
315 ix = indirection_rqt[ix];
316 rqn = hp->pair->rqn[ix];
317 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
318 }
319}
320
321static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
322{
323 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
324 struct mlx5e_priv *priv = hp->func_priv;
325 struct mlx5_core_dev *mdev = priv->mdev;
326 void *rqtc;
327 u32 *in;
328
329 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
330 in = kvzalloc(inlen, GFP_KERNEL);
331 if (!in)
332 return -ENOMEM;
333
334 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
335
336 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
337 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
338
339 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
340
341 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
342 if (!err)
343 hp->indir_rqt.enabled = true;
344
345 kvfree(in);
346 return err;
347}
348
349static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
350{
351 struct mlx5e_priv *priv = hp->func_priv;
352 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
353 int tt, i, err;
354 void *tirc;
355
356 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
357 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
358 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
359
360 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
361 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
362 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
363 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
364
365 err = mlx5_core_create_tir(hp->func_mdev, in,
366 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
367 if (err) {
368 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
369 goto err_destroy_tirs;
370 }
371 }
372 return 0;
373
374err_destroy_tirs:
375 for (i = 0; i < tt; i++)
376 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
377 return err;
378}
379
380static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
381{
382 int tt;
383
384 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
385 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
386}
387
388static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
389 struct ttc_params *ttc_params)
390{
391 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
392 int tt;
393
394 memset(ttc_params, 0, sizeof(*ttc_params));
395
396 ttc_params->any_tt_tirn = hp->tirn;
397
398 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
399 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
400
401 ft_attr->max_fte = MLX5E_NUM_TT;
402 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
403 ft_attr->prio = MLX5E_TC_PRIO;
404}
405
406static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
407{
408 struct mlx5e_priv *priv = hp->func_priv;
409 struct ttc_params ttc_params;
410 int err;
411
412 err = mlx5e_hairpin_create_indirect_rqt(hp);
413 if (err)
414 return err;
415
416 err = mlx5e_hairpin_create_indirect_tirs(hp);
417 if (err)
418 goto err_create_indirect_tirs;
419
420 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
421 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
422 if (err)
423 goto err_create_ttc_table;
424
425 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
426 hp->num_channels, hp->ttc.ft.t->id);
427
428 return 0;
429
430err_create_ttc_table:
431 mlx5e_hairpin_destroy_indirect_tirs(hp);
432err_create_indirect_tirs:
433 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
434
435 return err;
436}
437
438static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
439{
440 struct mlx5e_priv *priv = hp->func_priv;
441
442 mlx5e_destroy_ttc_table(priv, &hp->ttc);
443 mlx5e_hairpin_destroy_indirect_tirs(hp);
444 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
445}
446
77ab67b7
OG		 447static struct mlx5e_hairpin *
448mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
449 int peer_ifindex)
450{
451 struct mlx5_core_dev *func_mdev, *peer_mdev;
452 struct mlx5e_hairpin *hp;
453 struct mlx5_hairpin *pair;
454 int err;
455
456 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
457 if (!hp)
458 return ERR_PTR(-ENOMEM);
459
460 func_mdev = priv->mdev;
461 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
462
463 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
464 if (IS_ERR(pair)) {
465 err = PTR_ERR(pair);
466 goto create_pair_err;
467 }
468 hp->pair = pair;
469 hp->func_mdev = func_mdev;
3f6d08d1
OG		 470 hp->func_priv = priv;
471 hp->num_channels = params->num_channels;
77ab67b7
OG		 472
473 err = mlx5e_hairpin_create_transport(hp);
474 if (err)
475 goto create_transport_err;
476
3f6d08d1
OG		 477 if (hp->num_channels > 1) {
478 err = mlx5e_hairpin_rss_init(hp);
479 if (err)
480 goto rss_init_err;
481 }
482
77ab67b7
OG		 483 return hp;
484
3f6d08d1
OG		 485rss_init_err:
486 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 487create_transport_err:
488 mlx5_core_hairpin_destroy(hp->pair);
489create_pair_err:
490 kfree(hp);
491 return ERR_PTR(err);
492}
493
494static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
495{
3f6d08d1
OG		 496 if (hp->num_channels > 1)
497 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 498 mlx5e_hairpin_destroy_transport(hp);
499 mlx5_core_hairpin_destroy(hp->pair);
500 kvfree(hp);
501}
502
106be53b
OG		 503static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
504{
505 return (peer_vhca_id << 16 | prio);
506}
507
5c65c564 508static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 509 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 510{
511 struct mlx5e_hairpin_entry *hpe;
106be53b 512 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 513
514 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 515 hairpin_hlist, hash_key) {
516 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 517 return hpe;
518 }
519
520 return NULL;
521}
522
106be53b
OG		 523#define UNKNOWN_MATCH_PRIO 8
524
525static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
526 struct mlx5_flow_spec *spec, u8 *match_prio)
527{
528 void *headers_c, *headers_v;
529 u8 prio_val, prio_mask = 0;
530 bool vlan_present;
531
532#ifdef CONFIG_MLX5_CORE_EN_DCB
533 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
534 netdev_warn(priv->netdev,
535 "only PCP trust state supported for hairpin\n");
536 return -EOPNOTSUPP;
537 }
538#endif
539 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
540 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
541
542 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
543 if (vlan_present) {
544 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
545 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
546 }
547
548 if (!vlan_present || !prio_mask) {
549 prio_val = UNKNOWN_MATCH_PRIO;
550 } else if (prio_mask != 0x7) {
551 netdev_warn(priv->netdev,
552 "masked priority match not supported for hairpin\n");
553 return -EOPNOTSUPP;
554 }
555
556 *match_prio = prio_val;
557 return 0;
558}
559
5c65c564
OG		 560static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
561 struct mlx5e_tc_flow *flow,
562 struct mlx5e_tc_flow_parse_attr *parse_attr)
563{
564 int peer_ifindex = parse_attr->mirred_ifindex;
565 struct mlx5_hairpin_params params;
d8822868 566 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 567 struct mlx5e_hairpin_entry *hpe;
568 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 569 u64 link_speed64;
570 u32 link_speed;
106be53b 571 u8 match_prio;
d8822868 572 u16 peer_id;
5c65c564
OG		 573 int err;
574
d8822868
OG		 575 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
576 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
5c65c564
OG		 577 netdev_warn(priv->netdev, "hairpin is not supported\n");
578 return -EOPNOTSUPP;
579 }
580
d8822868 581 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
106be53b
OG		 582 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio);
583 if (err)
584 return err;
585 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 586 if (hpe)
587 goto attach_flow;
588
589 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
590 if (!hpe)
591 return -ENOMEM;
592
593 INIT_LIST_HEAD(&hpe->flows);
d8822868 594 hpe->peer_vhca_id = peer_id;
106be53b 595 hpe->prio = match_prio;
5c65c564
OG		 596
597 params.log_data_size = 15;
598 params.log_data_size = min_t(u8, params.log_data_size,
599 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
600 params.log_data_size = max_t(u8, params.log_data_size,
601 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 602
eb9180f7
OG		 603 params.log_num_packets = params.log_data_size -
604 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
605 params.log_num_packets = min_t(u8, params.log_num_packets,
606 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
607
608 params.q_counter = priv->q_counter;
3f6d08d1
OG		 609 /* set hairpin pair per each 50Gbs share of the link */
610 mlx5e_get_max_linkspeed(priv->mdev, &link_speed);
611 link_speed = max_t(u32, link_speed, 50000);
612 link_speed64 = link_speed;
613 do_div(link_speed64, 50000);
614 params.num_channels = link_speed64;
615
5c65c564
OG		 616 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
617 if (IS_ERR(hp)) {
618 err = PTR_ERR(hp);
619 goto create_hairpin_err;
620 }
621
eb9180f7 622 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 623 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 624 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 625
626 hpe->hp = hp;
106be53b
OG		 627 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
628 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 629
630attach_flow:
3f6d08d1
OG		 631 if (hpe->hp->num_channels > 1) {
632 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
633 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
634 } else {
635 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
636 }
5c65c564 637 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 638
5c65c564
OG		 639 return 0;
640
641create_hairpin_err:
642 kfree(hpe);
643 return err;
644}
645
646static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
647 struct mlx5e_tc_flow *flow)
648{
649 struct list_head *next = flow->hairpin.next;
650
651 list_del(&flow->hairpin);
652
653 /* no more hairpin flows for us, release the hairpin pair */
654 if (list_empty(next)) {
655 struct mlx5e_hairpin_entry *hpe;
656
657 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
658
659 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
660 hpe->hp->pair->peer_mdev->priv.name);
661
662 mlx5e_hairpin_destroy(hpe->hp);
663 hash_del(&hpe->hairpin_hlist);
664 kfree(hpe);
665 }
666}
667
74491de9
MB		 668static struct mlx5_flow_handle *
669mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 670 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 671 struct mlx5e_tc_flow *flow)
e8f887ac 672{
aa0cbbae 673 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 674 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 675 struct mlx5_flow_destination dest[2] = {};
66958ed9 676 struct mlx5_flow_act flow_act = {
3bc4b7bf 677 .action = attr->action,
a9db0ecf 678 .has_flow_tag = true,
3bc4b7bf 679 .flow_tag = attr->flow_tag,
66958ed9
HHZ		 680 .encap_id = 0,
681 };
aad7e08d 682 struct mlx5_fc *counter = NULL;
74491de9 683 struct mlx5_flow_handle *rule;
e8f887ac 684 bool table_created = false;
5c65c564 685 int err, dest_ix = 0;
e8f887ac 686
3f6d08d1
OG		 687 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
688 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr);
689 if (err) {
690 rule = ERR_PTR(err);
691 goto err_add_hairpin_flow;
692 }
693 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
694 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
695 dest[dest_ix].ft = attr->hairpin_ft;
696 } else {
5c65c564
OG		 697 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
698 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 699 }
700 dest_ix++;
3f6d08d1
OG		 701 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
702 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
703 dest[dest_ix].ft = priv->fs.vlan.ft.t;
704 dest_ix++;
5c65c564 705 }
aad7e08d 706
5c65c564
OG		 707 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
708 counter = mlx5_fc_create(dev, true);
709 if (IS_ERR(counter)) {
710 rule = ERR_CAST(counter);
711 goto err_fc_create;
712 }
713 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
714 dest[dest_ix].counter = counter;
715 dest_ix++;
aad7e08d
AV		 716 }
717
2f4fe4ca 718 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 719 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 720 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG		 721 kfree(parse_attr->mod_hdr_actions);
722 if (err) {
723 rule = ERR_PTR(err);
724 goto err_create_mod_hdr_id;
725 }
726 }
727
acff797c 728 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 729 int tc_grp_size, tc_tbl_size;
730 u32 max_flow_counter;
731
732 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
733 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
734
735 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
736
737 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
738 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
739
acff797c
MG		 740 priv->fs.tc.t =
741 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
742 MLX5E_TC_PRIO,
21b9c144 743 tc_tbl_size,
acff797c 744 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 745 MLX5E_TC_FT_LEVEL, 0);
acff797c 746 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV		 747 netdev_err(priv->netdev,
748 "Failed to create tc offload table\n");
aad7e08d
AV		 749 rule = ERR_CAST(priv->fs.tc.t);
750 goto err_create_ft;
e8f887ac
AV		 751 }
752
753 table_created = true;
754 }
755
17091853
OG		 756 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
757 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
5c65c564 758 &flow_act, dest, dest_ix);
aad7e08d
AV		 759
760 if (IS_ERR(rule))
761 goto err_add_rule;
762
763 return rule;
e8f887ac 764
aad7e08d
AV		 765err_add_rule:
766 if (table_created) {
acff797c
MG		 767 mlx5_destroy_flow_table(priv->fs.tc.t);
768 priv->fs.tc.t = NULL;
e8f887ac 769 }
aad7e08d 770err_create_ft:
2f4fe4ca 771 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 772 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 773err_create_mod_hdr_id:
aad7e08d 774 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 775err_fc_create:
776 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
777 mlx5e_hairpin_flow_del(priv, flow);
778err_add_hairpin_flow:
e8f887ac
AV		 779 return rule;
780}
781
d85cdccb
OG		 782static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
783 struct mlx5e_tc_flow *flow)
784{
513f8f7f 785 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 786 struct mlx5_fc *counter = NULL;
787
aa0cbbae
OG		 788 counter = mlx5_flow_rule_counter(flow->rule);
789 mlx5_del_flow_rules(flow->rule);
790 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 791
b3a433de 792 if (!mlx5e_tc_num_filters(priv) && priv->fs.tc.t) {
d85cdccb
OG		 793 mlx5_destroy_flow_table(priv->fs.tc.t);
794 priv->fs.tc.t = NULL;
795 }
2f4fe4ca 796
513f8f7f 797 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 798 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 799
800 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
801 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 802}
803
aa0cbbae
OG		 804static void mlx5e_detach_encap(struct mlx5e_priv *priv,
805 struct mlx5e_tc_flow *flow);
806
3c37745e
OG		 807static int mlx5e_attach_encap(struct mlx5e_priv *priv,
808 struct ip_tunnel_info *tun_info,
809 struct net_device *mirred_dev,
810 struct net_device **encap_dev,
811 struct mlx5e_tc_flow *flow);
812
74491de9
MB		 813static struct mlx5_flow_handle *
814mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 815 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 816 struct mlx5e_tc_flow *flow)
adb4c123
OG		 817{
818 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 819 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3c37745e
OG		 820 struct net_device *out_dev, *encap_dev = NULL;
821 struct mlx5_flow_handle *rule = NULL;
822 struct mlx5e_rep_priv *rpriv;
823 struct mlx5e_priv *out_priv;
8b32580d
OG		 824 int err;
825
3c37745e
OG		 826 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
827 out_dev = __dev_get_by_index(dev_net(priv->netdev),
828 attr->parse_attr->mirred_ifindex);
829 err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
830 out_dev, &encap_dev, flow);
831 if (err) {
832 rule = ERR_PTR(err);
833 if (err != -EAGAIN)
834 goto err_attach_encap;
835 }
836 out_priv = netdev_priv(encap_dev);
837 rpriv = out_priv->ppriv;
838 attr->out_rep = rpriv->rep;
839 }
840
8b32580d 841 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG		 842 if (err) {
843 rule = ERR_PTR(err);
844 goto err_add_vlan;
845 }
adb4c123 846
d7e75a32 847 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 848 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32
OG		 849 kfree(parse_attr->mod_hdr_actions);
850 if (err) {
851 rule = ERR_PTR(err);
852 goto err_mod_hdr;
853 }
854 }
855
3c37745e
OG		 856 /* we get here if (1) there's no error (rule being null) or when
857 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
858 */
859 if (rule != ERR_PTR(-EAGAIN)) {
860 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
861 if (IS_ERR(rule))
862 goto err_add_rule;
863 }
aa0cbbae
OG		 864 return rule;
865
866err_add_rule:
513f8f7f 867 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 868 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 869err_mod_hdr:
aa0cbbae
OG		 870 mlx5_eswitch_del_vlan_action(esw, attr);
871err_add_vlan:
872 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
873 mlx5e_detach_encap(priv, flow);
3c37745e 874err_attach_encap:
aa0cbbae
OG		 875 return rule;
876}
d85cdccb
OG		 877
878static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
879 struct mlx5e_tc_flow *flow)
880{
881 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 882 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 883
232c0013
HHZ		 884 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
885 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
513f8f7f 886 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, attr);
232c0013 887 }
d85cdccb 888
513f8f7f 889 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 890
513f8f7f 891 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
d85cdccb 892 mlx5e_detach_encap(priv, flow);
513f8f7f 893 kvfree(attr->parse_attr);
232c0013 894 }
d7e75a32 895
513f8f7f 896 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 897 mlx5e_detach_mod_hdr(priv, flow);
d85cdccb
OG		 898}
899
232c0013
HHZ		 900void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
901 struct mlx5e_encap_entry *e)
902{
3c37745e
OG		 903 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
904 struct mlx5_esw_flow_attr *esw_attr;
232c0013
HHZ		 905 struct mlx5e_tc_flow *flow;
906 int err;
907
908 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
909 e->encap_size, e->encap_header,
910 &e->encap_id);
911 if (err) {
912 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
913 err);
914 return;
915 }
916 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 917 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 918
919 list_for_each_entry(flow, &e->flows, encap) {
3c37745e
OG		 920 esw_attr = flow->esw_attr;
921 esw_attr->encap_id = e->encap_id;
922 flow->rule = mlx5_eswitch_add_offloaded_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
232c0013
HHZ		 923 if (IS_ERR(flow->rule)) {
924 err = PTR_ERR(flow->rule);
925 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
926 err);
927 continue;
928 }
929 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
930 }
931}
932
933void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
934 struct mlx5e_encap_entry *e)
935{
3c37745e 936 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
232c0013 937 struct mlx5e_tc_flow *flow;
232c0013
HHZ		 938
939 list_for_each_entry(flow, &e->flows, encap) {
940 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
941 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
3c37745e 942 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, flow->esw_attr);
232c0013
HHZ		 943 }
944 }
945
946 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
947 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
948 mlx5_encap_dealloc(priv->mdev, e->encap_id);
949 }
950}
951
f6dfb4c3
HHZ		 952void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
953{
954 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
955 u64 bytes, packets, lastuse = 0;
956 struct mlx5e_tc_flow *flow;
957 struct mlx5e_encap_entry *e;
958 struct mlx5_fc *counter;
959 struct neigh_table *tbl;
960 bool neigh_used = false;
961 struct neighbour *n;
962
963 if (m_neigh->family == AF_INET)
964 tbl = &arp_tbl;
965#if IS_ENABLED(CONFIG_IPV6)
966 else if (m_neigh->family == AF_INET6)
423c9db2 967 tbl = &nd_tbl;
f6dfb4c3
HHZ		 968#endif
969 else
970 return;
971
972 list_for_each_entry(e, &nhe->encap_list, encap_list) {
973 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
974 continue;
975 list_for_each_entry(flow, &e->flows, encap) {
976 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
977 counter = mlx5_flow_rule_counter(flow->rule);
978 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
979 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
980 neigh_used = true;
981 break;
982 }
983 }
984 }
e36d4810
RD		 985 if (neigh_used)
986 break;
f6dfb4c3
HHZ		 987 }
988
989 if (neigh_used) {
990 nhe->reported_lastuse = jiffies;
991
992 /* find the relevant neigh according to the cached device and
993 * dst ip pair
994 */
995 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
996 if (!n) {
997 WARN(1, "The neighbour already freed\n");
998 return;
999 }
1000
1001 neigh_event_send(n, NULL);
1002 neigh_release(n);
1003 }
1004}
1005
d85cdccb
OG		 1006static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1007 struct mlx5e_tc_flow *flow)
1008{
5067b602
RD		 1009 struct list_head *next = flow->encap.next;
1010
1011 list_del(&flow->encap);
1012 if (list_empty(next)) {
c1ae1152 1013 struct mlx5e_encap_entry *e;
5067b602 1014
c1ae1152 1015 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1016 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1017
1018 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
5067b602 1019 mlx5_encap_dealloc(priv->mdev, e->encap_id);
232c0013 1020
cdc5a7f3 1021 hash_del_rcu(&e->encap_hlist);
232c0013 1022 kfree(e->encap_header);
5067b602
RD		 1023 kfree(e);
1024 }
1025}
1026
e8f887ac 1027static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1028 struct mlx5e_tc_flow *flow)
e8f887ac 1029{
d85cdccb
OG		 1030 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1031 mlx5e_tc_del_fdb_flow(priv, flow);
1032 else
1033 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 1034}
1035
bbd00f7e
HHZ		 1036static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
1037 struct tc_cls_flower_offload *f)
1038{
1039 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1040 outer_headers);
1041 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1042 outer_headers);
1043 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1044 misc_parameters);
1045 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1046 misc_parameters);
1047
1048 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
1049 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1050
1051 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
1052 struct flow_dissector_key_keyid *key =
1053 skb_flow_dissector_target(f->dissector,
1054 FLOW_DISSECTOR_KEY_ENC_KEYID,
1055 f->key);
1056 struct flow_dissector_key_keyid *mask =
1057 skb_flow_dissector_target(f->dissector,
1058 FLOW_DISSECTOR_KEY_ENC_KEYID,
1059 f->mask);
1060 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
1061 be32_to_cpu(mask->keyid));
1062 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
1063 be32_to_cpu(key->keyid));
1064 }
1065}
1066
1067static int parse_tunnel_attr(struct mlx5e_priv *priv,
1068 struct mlx5_flow_spec *spec,
1069 struct tc_cls_flower_offload *f)
1070{
1071 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1072 outer_headers);
1073 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1074 outer_headers);
1075
2e72eb43
OG		 1076 struct flow_dissector_key_control *enc_control =
1077 skb_flow_dissector_target(f->dissector,
1078 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1079 f->key);
1080
bbd00f7e
HHZ		 1081 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
1082 struct flow_dissector_key_ports *key =
1083 skb_flow_dissector_target(f->dissector,
1084 FLOW_DISSECTOR_KEY_ENC_PORTS,
1085 f->key);
1086 struct flow_dissector_key_ports *mask =
1087 skb_flow_dissector_target(f->dissector,
1088 FLOW_DISSECTOR_KEY_ENC_PORTS,
1089 f->mask);
1ad9a00a 1090 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4 1091 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5ed99fb4 1092 struct net_device *up_dev = uplink_rpriv->netdev;
1ad9a00a 1093 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ		 1094
1095 /* Full udp dst port must be given */
1096 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 1097 goto vxlan_match_offload_err;
bbd00f7e 1098
1ad9a00a 1099 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 1100 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
1101 parse_vxlan_attr(spec, f);
2fcd82e9
OG		 1102 else {
1103 netdev_warn(priv->netdev,
1104 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 1105 return -EOPNOTSUPP;
2fcd82e9 1106 }
bbd00f7e
HHZ		 1107
1108 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1109 udp_dport, ntohs(mask->dst));
1110 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1111 udp_dport, ntohs(key->dst));
1112
cd377663
OG		 1113 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1114 udp_sport, ntohs(mask->src));
1115 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1116 udp_sport, ntohs(key->src));
bbd00f7e 1117 } else { /* udp dst port must be given */
2fcd82e9
OG		 1118vxlan_match_offload_err:
1119 netdev_warn(priv->netdev,
1120 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
1121 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1122 }
1123
2e72eb43 1124 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 1125 struct flow_dissector_key_ipv4_addrs *key =
1126 skb_flow_dissector_target(f->dissector,
1127 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1128 f->key);
1129 struct flow_dissector_key_ipv4_addrs *mask =
1130 skb_flow_dissector_target(f->dissector,
1131 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1132 f->mask);
1133 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1134 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1135 ntohl(mask->src));
1136 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1137 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1138 ntohl(key->src));
1139
1140 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1141 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1142 ntohl(mask->dst));
1143 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1144 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1145 ntohl(key->dst));
bbd00f7e 1146
2e72eb43
OG		 1147 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1148 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 1149 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1150 struct flow_dissector_key_ipv6_addrs *key =
1151 skb_flow_dissector_target(f->dissector,
1152 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1153 f->key);
1154 struct flow_dissector_key_ipv6_addrs *mask =
1155 skb_flow_dissector_target(f->dissector,
1156 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1157 f->mask);
1158
1159 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1160 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1161 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1162 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1163 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1164 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1165
1166 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1167 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1168 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1169 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1170 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1171 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1172
1173 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1174 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1175 }
bbd00f7e
HHZ		 1176
1177 /* Enforce DMAC when offloading incoming tunneled flows.
1178 * Flow counters require a match on the DMAC.
1179 */
1180 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1181 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1182 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1183 dmac_47_16), priv->netdev->dev_addr);
1184
1185 /* let software handle IP fragments */
1186 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1187 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1188
1189 return 0;
1190}
1191
de0af0bf
RD		 1192static int __parse_cls_flower(struct mlx5e_priv *priv,
1193 struct mlx5_flow_spec *spec,
1194 struct tc_cls_flower_offload *f,
d708f902 1195 u8 *match_level)
e3a2b7ed 1196{
c5bb1730
MG		 1197 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1198 outer_headers);
1199 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1200 outer_headers);
e3a2b7ed
AV		 1201 u16 addr_type = 0;
1202 u8 ip_proto = 0;
1203
d708f902 1204 *match_level = MLX5_MATCH_NONE;
de0af0bf 1205
e3a2b7ed
AV		 1206 if (f->dissector->used_keys &
1207 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1208 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1209 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1210 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV		 1211 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1212 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1213 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1214 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1215 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1216 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1217 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1218 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b
OG		 1219 BIT(FLOW_DISSECTOR_KEY_TCP) |
1220 BIT(FLOW_DISSECTOR_KEY_IP))) {
e3a2b7ed
AV		 1221 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1222 f->dissector->used_keys);
1223 return -EOPNOTSUPP;
1224 }
1225
bbd00f7e
HHZ		 1226 if ((dissector_uses_key(f->dissector,
1227 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1228 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1229 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1230 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1231 struct flow_dissector_key_control *key =
1232 skb_flow_dissector_target(f->dissector,
1233 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1234 f->key);
1235 switch (key->addr_type) {
1236 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1237 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 1238 if (parse_tunnel_attr(priv, spec, f))
1239 return -EOPNOTSUPP;
1240 break;
1241 default:
1242 return -EOPNOTSUPP;
1243 }
1244
1245 /* In decap flow, header pointers should point to the inner
1246 * headers, outer header were already set by parse_tunnel_attr
1247 */
1248 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1249 inner_headers);
1250 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1251 inner_headers);
1252 }
1253
e3a2b7ed
AV		 1254 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1255 struct flow_dissector_key_eth_addrs *key =
1256 skb_flow_dissector_target(f->dissector,
1257 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1258 f->key);
1259 struct flow_dissector_key_eth_addrs *mask =
1260 skb_flow_dissector_target(f->dissector,
1261 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1262 f->mask);
1263
1264 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1265 dmac_47_16),
1266 mask->dst);
1267 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1268 dmac_47_16),
1269 key->dst);
1270
1271 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1272 smac_47_16),
1273 mask->src);
1274 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1275 smac_47_16),
1276 key->src);
54782900
OG		 1277
1278 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
d708f902 1279 *match_level = MLX5_MATCH_L2;
e3a2b7ed
AV		 1280 }
1281
095b6cfd
OG		 1282 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1283 struct flow_dissector_key_vlan *key =
1284 skb_flow_dissector_target(f->dissector,
1285 FLOW_DISSECTOR_KEY_VLAN,
1286 f->key);
1287 struct flow_dissector_key_vlan *mask =
1288 skb_flow_dissector_target(f->dissector,
1289 FLOW_DISSECTOR_KEY_VLAN,
1290 f->mask);
358d79a4 1291 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY		 1292 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1293 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG		 1294
1295 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1296 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 1297
1298 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1299 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
54782900 1300
d708f902 1301 *match_level = MLX5_MATCH_L2;
54782900
OG		 1302 }
1303 }
1304
1305 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1306 struct flow_dissector_key_basic *key =
1307 skb_flow_dissector_target(f->dissector,
1308 FLOW_DISSECTOR_KEY_BASIC,
1309 f->key);
1310 struct flow_dissector_key_basic *mask =
1311 skb_flow_dissector_target(f->dissector,
1312 FLOW_DISSECTOR_KEY_BASIC,
1313 f->mask);
1314 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1315 ntohs(mask->n_proto));
1316 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1317 ntohs(key->n_proto));
1318
1319 if (mask->n_proto)
d708f902 1320 *match_level = MLX5_MATCH_L2;
54782900
OG		 1321 }
1322
1323 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1324 struct flow_dissector_key_control *key =
1325 skb_flow_dissector_target(f->dissector,
1326 FLOW_DISSECTOR_KEY_CONTROL,
1327 f->key);
1328
1329 struct flow_dissector_key_control *mask =
1330 skb_flow_dissector_target(f->dissector,
1331 FLOW_DISSECTOR_KEY_CONTROL,
1332 f->mask);
1333 addr_type = key->addr_type;
1334
1335 /* the HW doesn't support frag first/later */
1336 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1337 return -EOPNOTSUPP;
1338
1339 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1340 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1341 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1342 key->flags & FLOW_DIS_IS_FRAGMENT);
1343
1344 /* the HW doesn't need L3 inline to match on frag=no */
1345 if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
d708f902 1346 *match_level = MLX5_INLINE_MODE_L2;
54782900
OG		 1347 /* *** L2 attributes parsing up to here *** */
1348 else
d708f902 1349 *match_level = MLX5_INLINE_MODE_IP;
095b6cfd
OG		 1350 }
1351 }
1352
54782900
OG		 1353 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1354 struct flow_dissector_key_basic *key =
1355 skb_flow_dissector_target(f->dissector,
1356 FLOW_DISSECTOR_KEY_BASIC,
1357 f->key);
1358 struct flow_dissector_key_basic *mask =
1359 skb_flow_dissector_target(f->dissector,
1360 FLOW_DISSECTOR_KEY_BASIC,
1361 f->mask);
1362 ip_proto = key->ip_proto;
1363
1364 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1365 mask->ip_proto);
1366 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1367 key->ip_proto);
1368
1369 if (mask->ip_proto)
d708f902 1370 *match_level = MLX5_MATCH_L3;
54782900
OG		 1371 }
1372
e3a2b7ed
AV		 1373 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1374 struct flow_dissector_key_ipv4_addrs *key =
1375 skb_flow_dissector_target(f->dissector,
1376 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1377 f->key);
1378 struct flow_dissector_key_ipv4_addrs *mask =
1379 skb_flow_dissector_target(f->dissector,
1380 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1381 f->mask);
1382
1383 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1384 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1385 &mask->src, sizeof(mask->src));
1386 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1387 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1388 &key->src, sizeof(key->src));
1389 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1390 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1391 &mask->dst, sizeof(mask->dst));
1392 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1393 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1394 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1395
1396 if (mask->src || mask->dst)
d708f902 1397 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1398 }
1399
1400 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1401 struct flow_dissector_key_ipv6_addrs *key =
1402 skb_flow_dissector_target(f->dissector,
1403 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1404 f->key);
1405 struct flow_dissector_key_ipv6_addrs *mask =
1406 skb_flow_dissector_target(f->dissector,
1407 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1408 f->mask);
1409
1410 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1411 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1412 &mask->src, sizeof(mask->src));
1413 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1414 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1415 &key->src, sizeof(key->src));
1416
1417 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1418 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1419 &mask->dst, sizeof(mask->dst));
1420 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1421 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1422 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1423
1424 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1425 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
d708f902 1426 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1427 }
1428
1f97a526
OG		 1429 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1430 struct flow_dissector_key_ip *key =
1431 skb_flow_dissector_target(f->dissector,
1432 FLOW_DISSECTOR_KEY_IP,
1433 f->key);
1434 struct flow_dissector_key_ip *mask =
1435 skb_flow_dissector_target(f->dissector,
1436 FLOW_DISSECTOR_KEY_IP,
1437 f->mask);
1438
1439 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1440 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1441
1442 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1443 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1444
a8ade55f
OG		 1445 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1446 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 1447
a8ade55f
OG		 1448 if (mask->ttl &&
1449 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
1450 ft_field_support.outer_ipv4_ttl))
1f97a526 1451 return -EOPNOTSUPP;
a8ade55f
OG		 1452
1453 if (mask->tos || mask->ttl)
d708f902 1454 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1455 }
1456
54782900
OG		 1457 /* *** L3 attributes parsing up to here *** */
1458
e3a2b7ed
AV		 1459 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1460 struct flow_dissector_key_ports *key =
1461 skb_flow_dissector_target(f->dissector,
1462 FLOW_DISSECTOR_KEY_PORTS,
1463 f->key);
1464 struct flow_dissector_key_ports *mask =
1465 skb_flow_dissector_target(f->dissector,
1466 FLOW_DISSECTOR_KEY_PORTS,
1467 f->mask);
1468 switch (ip_proto) {
1469 case IPPROTO_TCP:
1470 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1471 tcp_sport, ntohs(mask->src));
1472 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1473 tcp_sport, ntohs(key->src));
1474
1475 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1476 tcp_dport, ntohs(mask->dst));
1477 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1478 tcp_dport, ntohs(key->dst));
1479 break;
1480
1481 case IPPROTO_UDP:
1482 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1483 udp_sport, ntohs(mask->src));
1484 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1485 udp_sport, ntohs(key->src));
1486
1487 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1488 udp_dport, ntohs(mask->dst));
1489 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1490 udp_dport, ntohs(key->dst));
1491 break;
1492 default:
1493 netdev_err(priv->netdev,
1494 "Only UDP and TCP transport are supported\n");
1495 return -EINVAL;
1496 }
de0af0bf
RD		 1497
1498 if (mask->src || mask->dst)
d708f902 1499 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1500 }
1501
e77834ec
OG		 1502 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1503 struct flow_dissector_key_tcp *key =
1504 skb_flow_dissector_target(f->dissector,
1505 FLOW_DISSECTOR_KEY_TCP,
1506 f->key);
1507 struct flow_dissector_key_tcp *mask =
1508 skb_flow_dissector_target(f->dissector,
1509 FLOW_DISSECTOR_KEY_TCP,
1510 f->mask);
1511
1512 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1513 ntohs(mask->flags));
1514 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1515 ntohs(key->flags));
1516
1517 if (mask->flags)
d708f902 1518 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1519 }
1520
e3a2b7ed
AV		 1521 return 0;
1522}
1523
de0af0bf 1524static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1525 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 1526 struct mlx5_flow_spec *spec,
1527 struct tc_cls_flower_offload *f)
1528{
1529 struct mlx5_core_dev *dev = priv->mdev;
1530 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1531 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1532 struct mlx5_eswitch_rep *rep;
d708f902 1533 u8 match_level;
de0af0bf
RD		 1534 int err;
1535
d708f902 1536 err = __parse_cls_flower(priv, spec, f, &match_level);
de0af0bf 1537
1d447a39
SM		 1538 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1539 rep = rpriv->rep;
1540 if (rep->vport != FDB_UPLINK_VPORT &&
1541 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1542 esw->offloads.inline_mode < match_level)) {
de0af0bf
RD		 1543 netdev_warn(priv->netdev,
1544 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1545 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1546 return -EOPNOTSUPP;
1547 }
1548 }
1549
1550 return err;
1551}
1552
d79b6df6
OG		 1553struct pedit_headers {
1554 struct ethhdr eth;
1555 struct iphdr ip4;
1556 struct ipv6hdr ip6;
1557 struct tcphdr tcp;
1558 struct udphdr udp;
1559};
1560
1561static int pedit_header_offsets[] = {
1562 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1563 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1564 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1565 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1566 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1567};
1568
1569#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1570
1571static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1572 struct pedit_headers *masks,
1573 struct pedit_headers *vals)
1574{
1575 u32 *curr_pmask, *curr_pval;
1576
1577 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1578 goto out_err;
1579
1580 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1581 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1582
1583 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1584 goto out_err;
1585
1586 *curr_pmask |= mask;
1587 *curr_pval |= (val & mask);
1588
1589 return 0;
1590
1591out_err:
1592 return -EOPNOTSUPP;
1593}
1594
1595struct mlx5_fields {
1596 u8 field;
1597 u8 size;
1598 u32 offset;
1599};
1600
a8e4f0c4
OG		 1601#define OFFLOAD(fw_field, size, field, off) \
1602 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1603
d79b6df6 1604static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1605 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1606 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1607 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1608 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1609 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1610
1611 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1612 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1613 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1614
1615 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1616 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1617 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1618 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1619 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1620 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1621 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1622 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1623 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1624
1625 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1626 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1627 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1628
1629 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1630 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1631};
1632
1633/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1634 * max from the SW pedit action. On success, it says how many HW actions were
1635 * actually parsed.
1636 */
1637static int offload_pedit_fields(struct pedit_headers *masks,
1638 struct pedit_headers *vals,
1639 struct mlx5e_tc_flow_parse_attr *parse_attr)
1640{
1641 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1642 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1643 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1644 struct mlx5_fields *f;
1645 u8 cmd, field_bsize;
e3ca4e05 1646 u32 s_mask, a_mask;
d79b6df6 1647 unsigned long mask;
2b64beba
OG		 1648 __be32 mask_be32;
1649 __be16 mask_be16;
d79b6df6
OG		 1650 void *action;
1651
1652 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1653 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1654 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1655 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1656
1657 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1658 action = parse_attr->mod_hdr_actions;
1659 max_actions = parse_attr->num_mod_hdr_actions;
1660 nactions = 0;
1661
1662 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1663 f = &fields[i];
1664 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1665 s_mask = 0;
1666 a_mask = 0;
d79b6df6
OG		 1667
1668 s_masks_p = (void *)set_masks + f->offset;
1669 a_masks_p = (void *)add_masks + f->offset;
1670
1671 memcpy(&s_mask, s_masks_p, f->size);
1672 memcpy(&a_mask, a_masks_p, f->size);
1673
1674 if (!s_mask && !a_mask) /* nothing to offload here */
1675 continue;
1676
1677 if (s_mask && a_mask) {
1678 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1679 return -EOPNOTSUPP;
1680 }
1681
1682 if (nactions == max_actions) {
1683 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1684 return -EOPNOTSUPP;
1685 }
1686
1687 if (s_mask) {
1688 cmd = MLX5_ACTION_TYPE_SET;
1689 mask = s_mask;
1690 vals_p = (void *)set_vals + f->offset;
1691 /* clear to denote we consumed this field */
1692 memset(s_masks_p, 0, f->size);
1693 } else {
1694 cmd = MLX5_ACTION_TYPE_ADD;
1695 mask = a_mask;
1696 vals_p = (void *)add_vals + f->offset;
1697 /* clear to denote we consumed this field */
1698 memset(a_masks_p, 0, f->size);
1699 }
1700
d79b6df6 1701 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1702
2b64beba
OG		 1703 if (field_bsize == 32) {
1704 mask_be32 = *(__be32 *)&mask;
1705 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1706 } else if (field_bsize == 16) {
1707 mask_be16 = *(__be16 *)&mask;
1708 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1709 }
1710
d79b6df6 1711 first = find_first_bit(&mask, field_bsize);
2b64beba 1712 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1713 last = find_last_bit(&mask, field_bsize);
2b64beba
OG		 1714 if (first < next_z && next_z < last) {
1715 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1716 mask);
1717 return -EOPNOTSUPP;
1718 }
1719
1720 MLX5_SET(set_action_in, action, action_type, cmd);
1721 MLX5_SET(set_action_in, action, field, f->field);
1722
1723 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1724 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1725 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1726 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1727 }
1728
1729 if (field_bsize == 32)
2b64beba 1730 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1731 else if (field_bsize == 16)
2b64beba 1732 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1733 else if (field_bsize == 8)
2b64beba 1734 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1735
1736 action += action_size;
1737 nactions++;
1738 }
1739
1740 parse_attr->num_mod_hdr_actions = nactions;
1741 return 0;
1742}
1743
1744static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1745 const struct tc_action *a, int namespace,
1746 struct mlx5e_tc_flow_parse_attr *parse_attr)
1747{
1748 int nkeys, action_size, max_actions;
1749
1750 nkeys = tcf_pedit_nkeys(a);
1751 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1752
1753 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1754 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1755 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1756 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1757
1758 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1759 max_actions = min(max_actions, nkeys * 16);
1760
1761 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1762 if (!parse_attr->mod_hdr_actions)
1763 return -ENOMEM;
1764
1765 parse_attr->num_mod_hdr_actions = max_actions;
1766 return 0;
1767}
1768
1769static const struct pedit_headers zero_masks = {};
1770
1771static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1772 const struct tc_action *a, int namespace,
1773 struct mlx5e_tc_flow_parse_attr *parse_attr)
1774{
1775 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1776 int nkeys, i, err = -EOPNOTSUPP;
1777 u32 mask, val, offset;
1778 u8 cmd, htype;
1779
1780 nkeys = tcf_pedit_nkeys(a);
1781
1782 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1783 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1784
1785 for (i = 0; i < nkeys; i++) {
1786 htype = tcf_pedit_htype(a, i);
1787 cmd = tcf_pedit_cmd(a, i);
1788 err = -EOPNOTSUPP; /* can't be all optimistic */
1789
1790 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
b3a433de 1791 netdev_warn(priv->netdev, "legacy pedit isn't offloaded\n");
d79b6df6
OG		 1792 goto out_err;
1793 }
1794
1795 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
b3a433de 1796 netdev_warn(priv->netdev, "pedit cmd %d isn't offloaded\n", cmd);
d79b6df6
OG		 1797 goto out_err;
1798 }
1799
1800 mask = tcf_pedit_mask(a, i);
1801 val = tcf_pedit_val(a, i);
1802 offset = tcf_pedit_offset(a, i);
1803
1804 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1805 if (err)
1806 goto out_err;
1807 }
1808
1809 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1810 if (err)
1811 goto out_err;
1812
1813 err = offload_pedit_fields(masks, vals, parse_attr);
1814 if (err < 0)
1815 goto out_dealloc_parsed_actions;
1816
1817 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1818 cmd_masks = &masks[cmd];
1819 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
b3a433de 1820 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 1821 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1822 16, 1, cmd_masks, sizeof(zero_masks), true);
1823 err = -EOPNOTSUPP;
1824 goto out_dealloc_parsed_actions;
1825 }
1826 }
1827
1828 return 0;
1829
1830out_dealloc_parsed_actions:
1831 kfree(parse_attr->mod_hdr_actions);
1832out_err:
1833 return err;
1834}
1835
26c02749
OG		 1836static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1837{
1838 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1839 TCA_CSUM_UPDATE_FLAG_UDP;
1840
1841 /* The HW recalcs checksums only if re-writing headers */
1842 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1843 netdev_warn(priv->netdev,
1844 "TC csum action is only offloaded with pedit\n");
1845 return false;
1846 }
1847
1848 if (update_flags & ~prot_flags) {
1849 netdev_warn(priv->netdev,
1850 "can't offload TC csum action for some header/s - flags %#x\n",
1851 update_flags);
1852 return false;
1853 }
1854
1855 return true;
1856}
1857
bdd66ac0
OG		 1858static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
1859 struct tcf_exts *exts)
1860{
1861 const struct tc_action *a;
1862 bool modify_ip_header;
1863 LIST_HEAD(actions);
1864 u8 htype, ip_proto;
1865 void *headers_v;
1866 u16 ethertype;
1867 int nkeys, i;
1868
1869 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1870 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1871
1872 /* for non-IP we only re-write MACs, so we're okay */
1873 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
1874 goto out_ok;
1875
1876 modify_ip_header = false;
1877 tcf_exts_to_list(exts, &actions);
1878 list_for_each_entry(a, &actions, list) {
1879 if (!is_tcf_pedit(a))
1880 continue;
1881
1882 nkeys = tcf_pedit_nkeys(a);
1883 for (i = 0; i < nkeys; i++) {
1884 htype = tcf_pedit_htype(a, i);
1885 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
1886 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
1887 modify_ip_header = true;
1888 break;
1889 }
1890 }
1891 }
1892
1893 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 1894 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
1895 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
bdd66ac0
OG		 1896 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
1897 return false;
1898 }
1899
1900out_ok:
1901 return true;
1902}
1903
1904static bool actions_match_supported(struct mlx5e_priv *priv,
1905 struct tcf_exts *exts,
1906 struct mlx5e_tc_flow_parse_attr *parse_attr,
1907 struct mlx5e_tc_flow *flow)
1908{
1909 u32 actions;
1910
1911 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1912 actions = flow->esw_attr->action;
1913 else
1914 actions = flow->nic_attr->action;
1915
1916 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1917 return modify_header_match_supported(&parse_attr->spec, exts);
1918
1919 return true;
1920}
1921
5c65c564
OG		 1922static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
1923{
1924 struct mlx5_core_dev *fmdev, *pmdev;
1925 u16 func_id, peer_id;
1926
1927 fmdev = priv->mdev;
1928 pmdev = peer_priv->mdev;
1929
1930 func_id = (u16)((fmdev->pdev->bus->number << 8) | PCI_SLOT(fmdev->pdev->devfn));
1931 peer_id = (u16)((pmdev->pdev->bus->number << 8) | PCI_SLOT(pmdev->pdev->devfn));
1932
1933 return (func_id == peer_id);
1934}
1935
5c40348c 1936static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG		 1937 struct mlx5e_tc_flow_parse_attr *parse_attr,
1938 struct mlx5e_tc_flow *flow)
e3a2b7ed 1939{
aa0cbbae 1940 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1941 const struct tc_action *a;
22dc13c8 1942 LIST_HEAD(actions);
1cab1cd7 1943 u32 action = 0;
2f4fe4ca 1944 int err;
e3a2b7ed 1945
3bcc0cec 1946 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 1947 return -EINVAL;
1948
3bc4b7bf 1949 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 1950
22dc13c8
WC		 1951 tcf_exts_to_list(exts, &actions);
1952 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1953 if (is_tcf_gact_shot(a)) {
1cab1cd7 1954 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 1955 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1956 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 1957 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 1958 continue;
1959 }
1960
2f4fe4ca
OG		 1961 if (is_tcf_pedit(a)) {
1962 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1963 parse_attr);
1964 if (err)
1965 return err;
1966
1cab1cd7
OG		 1967 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1968 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2f4fe4ca
OG		 1969 continue;
1970 }
1971
26c02749 1972 if (is_tcf_csum(a)) {
1cab1cd7 1973 if (csum_offload_supported(priv, action,
26c02749
OG		 1974 tcf_csum_update_flags(a)))
1975 continue;
1976
1977 return -EOPNOTSUPP;
1978 }
1979
5c65c564
OG		 1980 if (is_tcf_mirred_egress_redirect(a)) {
1981 struct net_device *peer_dev = tcf_mirred_dev(a);
1982
1983 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
1984 same_hw_devs(priv, netdev_priv(peer_dev))) {
1985 parse_attr->mirred_ifindex = peer_dev->ifindex;
1986 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 1987 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1988 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564
OG		 1989 } else {
1990 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
1991 peer_dev->name);
1992 return -EINVAL;
1993 }
1994 continue;
1995 }
1996
e3a2b7ed
AV		 1997 if (is_tcf_skbedit_mark(a)) {
1998 u32 mark = tcf_skbedit_mark(a);
1999
2000 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2001 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
2002 mark);
2003 return -EINVAL;
2004 }
2005
3bc4b7bf 2006 attr->flow_tag = mark;
1cab1cd7 2007 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 2008 continue;
2009 }
2010
2011 return -EINVAL;
2012 }
2013
1cab1cd7 2014 attr->action = action;
bdd66ac0
OG		 2015 if (!actions_match_supported(priv, exts, parse_attr, flow))
2016 return -EOPNOTSUPP;
2017
e3a2b7ed
AV		 2018 return 0;
2019}
2020
76f7444d
OG		 2021static inline int cmp_encap_info(struct ip_tunnel_key *a,
2022 struct ip_tunnel_key *b)
a54e20b4
HHZ		 2023{
2024 return memcmp(a, b, sizeof(*a));
2025}
2026
76f7444d 2027static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2028{
76f7444d 2029 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2030}
2031
2032static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
2033 struct net_device *mirred_dev,
2034 struct net_device **out_dev,
2035 struct flowi4 *fl4,
2036 struct neighbour **out_n,
a54e20b4
HHZ		 2037 int *out_ttl)
2038{
3e621b19 2039 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5ed99fb4 2040 struct mlx5e_rep_priv *uplink_rpriv;
a54e20b4
HHZ		 2041 struct rtable *rt;
2042 struct neighbour *n = NULL;
a54e20b4
HHZ		 2043
2044#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 2045 int ret;
2046
a54e20b4 2047 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 2048 ret = PTR_ERR_OR_ZERO(rt);
2049 if (ret)
2050 return ret;
a54e20b4
HHZ		 2051#else
2052 return -EOPNOTSUPP;
2053#endif
a4b97ab4 2054 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3e621b19
HHZ		 2055 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2056 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
5ed99fb4 2057 *out_dev = uplink_rpriv->netdev;
3e621b19
HHZ		 2058 else
2059 *out_dev = rt->dst.dev;
a54e20b4 2060
75c33da8 2061 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 2062 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
2063 ip_rt_put(rt);
2064 if (!n)
2065 return -ENOMEM;
2066
2067 *out_n = n;
a54e20b4
HHZ		 2068 return 0;
2069}
2070
ce99f6b9
OG		 2071static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
2072 struct net_device *mirred_dev,
2073 struct net_device **out_dev,
2074 struct flowi6 *fl6,
2075 struct neighbour **out_n,
2076 int *out_ttl)
2077{
2078 struct neighbour *n = NULL;
2079 struct dst_entry *dst;
2080
2081#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
74bd5d56 2082 struct mlx5e_rep_priv *uplink_rpriv;
ce99f6b9
OG		 2083 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2084 int ret;
2085
08820528
PB		 2086 ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
2087 fl6);
2088 if (ret < 0)
ce99f6b9 2089 return ret;
ce99f6b9
OG		 2090
2091 *out_ttl = ip6_dst_hoplimit(dst);
2092
a4b97ab4 2093 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ce99f6b9
OG		 2094 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2095 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
5ed99fb4 2096 *out_dev = uplink_rpriv->netdev;
ce99f6b9
OG		 2097 else
2098 *out_dev = dst->dev;
2099#else
2100 return -EOPNOTSUPP;
2101#endif
2102
2103 n = dst_neigh_lookup(dst, &fl6->daddr);
2104 dst_release(dst);
2105 if (!n)
2106 return -ENOMEM;
2107
2108 *out_n = n;
2109 return 0;
2110}
2111
32f3671f
OG		 2112static void gen_vxlan_header_ipv4(struct net_device *out_dev,
2113 char buf[], int encap_size,
2114 unsigned char h_dest[ETH_ALEN],
2115 int ttl,
2116 __be32 daddr,
2117 __be32 saddr,
2118 __be16 udp_dst_port,
2119 __be32 vx_vni)
a54e20b4 2120{
a54e20b4
HHZ		 2121 struct ethhdr *eth = (struct ethhdr *)buf;
2122 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
2123 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
2124 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2125
2126 memset(buf, 0, encap_size);
2127
2128 ether_addr_copy(eth->h_dest, h_dest);
2129 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2130 eth->h_proto = htons(ETH_P_IP);
2131
2132 ip->daddr = daddr;
2133 ip->saddr = saddr;
2134
2135 ip->ttl = ttl;
2136 ip->protocol = IPPROTO_UDP;
2137 ip->version = 0x4;
2138 ip->ihl = 0x5;
2139
2140 udp->dest = udp_dst_port;
2141 vxh->vx_flags = VXLAN_HF_VNI;
2142 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 2143}
2144
225aabaf
OG		 2145static void gen_vxlan_header_ipv6(struct net_device *out_dev,
2146 char buf[], int encap_size,
2147 unsigned char h_dest[ETH_ALEN],
2148 int ttl,
2149 struct in6_addr *daddr,
2150 struct in6_addr *saddr,
2151 __be16 udp_dst_port,
2152 __be32 vx_vni)
ce99f6b9 2153{
ce99f6b9
OG		 2154 struct ethhdr *eth = (struct ethhdr *)buf;
2155 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
2156 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
2157 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2158
2159 memset(buf, 0, encap_size);
2160
2161 ether_addr_copy(eth->h_dest, h_dest);
2162 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2163 eth->h_proto = htons(ETH_P_IPV6);
2164
2165 ip6_flow_hdr(ip6h, 0, 0);
2166 /* the HW fills up ipv6 payload len */
2167 ip6h->nexthdr = IPPROTO_UDP;
2168 ip6h->hop_limit = ttl;
2169 ip6h->daddr = *daddr;
2170 ip6h->saddr = *saddr;
2171
2172 udp->dest = udp_dst_port;
2173 vxh->vx_flags = VXLAN_HF_VNI;
2174 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 2175}
2176
a54e20b4
HHZ		 2177static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
2178 struct net_device *mirred_dev,
1a8552bd 2179 struct mlx5e_encap_entry *e)
a54e20b4
HHZ		 2180{
2181 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 2182 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 2183 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2184 struct net_device *out_dev;
a42485eb 2185 struct neighbour *n = NULL;
a54e20b4 2186 struct flowi4 fl4 = {};
a54e20b4 2187 char *encap_header;
32f3671f 2188 int ttl, err;
033354d5 2189 u8 nud_state;
32f3671f
OG		 2190
2191 if (max_encap_size < ipv4_encap_size) {
2192 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2193 ipv4_encap_size, max_encap_size);
2194 return -EOPNOTSUPP;
2195 }
a54e20b4 2196
32f3671f 2197 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 2198 if (!encap_header)
2199 return -ENOMEM;
2200
2201 switch (e->tunnel_type) {
2202 case MLX5_HEADER_TYPE_VXLAN:
2203 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 2204 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 2205 break;
2206 default:
2207 err = -EOPNOTSUPP;
ace74321 2208 goto free_encap;
a54e20b4 2209 }
9a941117 2210 fl4.flowi4_tos = tun_key->tos;
76f7444d 2211 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 2212 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 2213
1a8552bd 2214 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 2215 &fl4, &n, &ttl);
a54e20b4 2216 if (err)
ace74321 2217 goto free_encap;
a54e20b4 2218
232c0013
HHZ		 2219 /* used by mlx5e_detach_encap to lookup a neigh hash table
2220 * entry in the neigh hash table when a user deletes a rule
2221 */
2222 e->m_neigh.dev = n->dev;
f6dfb4c3 2223 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2224 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2225 e->out_dev = out_dev;
2226
2227 /* It's importent to add the neigh to the hash table before checking
2228 * the neigh validity state. So if we'll get a notification, in case the
2229 * neigh changes it's validity state, we would find the relevant neigh
2230 * in the hash.
2231 */
2232 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2233 if (err)
ace74321 2234 goto free_encap;
232c0013 2235
033354d5
HHZ		 2236 read_lock_bh(&n->lock);
2237 nud_state = n->nud_state;
2238 ether_addr_copy(e->h_dest, n->ha);
2239 read_unlock_bh(&n->lock);
2240
a54e20b4
HHZ		 2241 switch (e->tunnel_type) {
2242 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 2243 gen_vxlan_header_ipv4(out_dev, encap_header,
32f3671f
OG		 2244 ipv4_encap_size, e->h_dest, ttl,
2245 fl4.daddr,
2246 fl4.saddr, tun_key->tp_dst,
2247 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 2248 break;
2249 default:
2250 err = -EOPNOTSUPP;
232c0013
HHZ		 2251 goto destroy_neigh_entry;
2252 }
2253 e->encap_size = ipv4_encap_size;
2254 e->encap_header = encap_header;
2255
2256 if (!(nud_state & NUD_VALID)) {
2257 neigh_event_send(n, NULL);
27902f08
WY		 2258 err = -EAGAIN;
2259 goto out;
a54e20b4
HHZ		 2260 }
2261
2262 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 2263 ipv4_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 2264 if (err)
2265 goto destroy_neigh_entry;
2266
2267 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2268 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2269 neigh_release(n);
2270 return err;
2271
2272destroy_neigh_entry:
2273 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2274free_encap:
a54e20b4 2275 kfree(encap_header);
ace74321 2276out:
232c0013
HHZ		 2277 if (n)
2278 neigh_release(n);
a54e20b4
HHZ		 2279 return err;
2280}
2281
ce99f6b9
OG		 2282static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2283 struct net_device *mirred_dev,
1a8552bd 2284 struct mlx5e_encap_entry *e)
ce99f6b9
OG		 2285{
2286 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 2287 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 2288 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2289 struct net_device *out_dev;
ce99f6b9
OG		 2290 struct neighbour *n = NULL;
2291 struct flowi6 fl6 = {};
2292 char *encap_header;
225aabaf 2293 int err, ttl = 0;
033354d5 2294 u8 nud_state;
ce99f6b9 2295
225aabaf
OG		 2296 if (max_encap_size < ipv6_encap_size) {
2297 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2298 ipv6_encap_size, max_encap_size);
2299 return -EOPNOTSUPP;
2300 }
ce99f6b9 2301
225aabaf 2302 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 2303 if (!encap_header)
2304 return -ENOMEM;
2305
2306 switch (e->tunnel_type) {
2307 case MLX5_HEADER_TYPE_VXLAN:
2308 fl6.flowi6_proto = IPPROTO_UDP;
2309 fl6.fl6_dport = tun_key->tp_dst;
2310 break;
2311 default:
2312 err = -EOPNOTSUPP;
ace74321 2313 goto free_encap;
ce99f6b9
OG		 2314 }
2315
2316 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2317 fl6.daddr = tun_key->u.ipv6.dst;
2318 fl6.saddr = tun_key->u.ipv6.src;
2319
1a8552bd 2320 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG		 2321 &fl6, &n, &ttl);
2322 if (err)
ace74321 2323 goto free_encap;
ce99f6b9 2324
232c0013
HHZ		 2325 /* used by mlx5e_detach_encap to lookup a neigh hash table
2326 * entry in the neigh hash table when a user deletes a rule
2327 */
2328 e->m_neigh.dev = n->dev;
f6dfb4c3 2329 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2330 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2331 e->out_dev = out_dev;
2332
2333 /* It's importent to add the neigh to the hash table before checking
2334 * the neigh validity state. So if we'll get a notification, in case the
2335 * neigh changes it's validity state, we would find the relevant neigh
2336 * in the hash.
2337 */
2338 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2339 if (err)
ace74321 2340 goto free_encap;
232c0013 2341
033354d5
HHZ		 2342 read_lock_bh(&n->lock);
2343 nud_state = n->nud_state;
2344 ether_addr_copy(e->h_dest, n->ha);
2345 read_unlock_bh(&n->lock);
2346
ce99f6b9
OG		 2347 switch (e->tunnel_type) {
2348 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 2349 gen_vxlan_header_ipv6(out_dev, encap_header,
225aabaf
OG		 2350 ipv6_encap_size, e->h_dest, ttl,
2351 &fl6.daddr,
2352 &fl6.saddr, tun_key->tp_dst,
2353 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 2354 break;
2355 default:
2356 err = -EOPNOTSUPP;
232c0013
HHZ		 2357 goto destroy_neigh_entry;
2358 }
2359
2360 e->encap_size = ipv6_encap_size;
2361 e->encap_header = encap_header;
2362
2363 if (!(nud_state & NUD_VALID)) {
2364 neigh_event_send(n, NULL);
27902f08
WY		 2365 err = -EAGAIN;
2366 goto out;
ce99f6b9
OG		 2367 }
2368
2369 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 2370 ipv6_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 2371 if (err)
2372 goto destroy_neigh_entry;
2373
2374 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2375 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2376 neigh_release(n);
2377 return err;
2378
2379destroy_neigh_entry:
2380 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2381free_encap:
ce99f6b9 2382 kfree(encap_header);
ace74321 2383out:
232c0013
HHZ		 2384 if (n)
2385 neigh_release(n);
ce99f6b9
OG		 2386 return err;
2387}
2388
a54e20b4
HHZ		 2389static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2390 struct ip_tunnel_info *tun_info,
2391 struct net_device *mirred_dev,
45247bf2
OG		 2392 struct net_device **encap_dev,
2393 struct mlx5e_tc_flow *flow)
a54e20b4
HHZ		 2394{
2395 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4
MB		 2396 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw,
2397 REP_ETH);
5ed99fb4 2398 struct net_device *up_dev = uplink_rpriv->netdev;
a54e20b4 2399 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2
OG		 2400 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
2401 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2402 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2403 struct mlx5e_encap_entry *e;
45247bf2 2404 int tunnel_type, err = 0;
a54e20b4
HHZ		 2405 uintptr_t hash_key;
2406 bool found = false;
a54e20b4 2407
2fcd82e9 2408 /* udp dst port must be set */
a54e20b4 2409 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 2410 goto vxlan_encap_offload_err;
a54e20b4 2411
cd377663 2412 /* setting udp src port isn't supported */
2fcd82e9
OG		 2413 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2414vxlan_encap_offload_err:
2415 netdev_warn(priv->netdev,
2416 "must set udp dst port and not set udp src port\n");
cd377663 2417 return -EOPNOTSUPP;
2fcd82e9 2418 }
cd377663 2419
1ad9a00a 2420 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 2421 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ		 2422 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
2423 } else {
2fcd82e9
OG		 2424 netdev_warn(priv->netdev,
2425 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 2426 return -EOPNOTSUPP;
2427 }
2428
76f7444d 2429 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2430
2431 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2432 encap_hlist, hash_key) {
76f7444d 2433 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2434 found = true;
2435 break;
2436 }
2437 }
2438
b2812089 2439 /* must verify if encap is valid or not */
45247bf2
OG		 2440 if (found)
2441 goto attach_flow;
a54e20b4
HHZ		 2442
2443 e = kzalloc(sizeof(*e), GFP_KERNEL);
2444 if (!e)
2445 return -ENOMEM;
2446
76f7444d 2447 e->tun_info = *tun_info;
a54e20b4
HHZ		 2448 e->tunnel_type = tunnel_type;
2449 INIT_LIST_HEAD(&e->flows);
2450
ce99f6b9 2451 if (family == AF_INET)
1a8552bd 2452 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2453 else if (family == AF_INET6)
1a8552bd 2454 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2455
232c0013 2456 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2457 goto out_err;
2458
a54e20b4
HHZ		 2459 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2460
45247bf2
OG		 2461attach_flow:
2462 list_add(&flow->encap, &e->flows);
2463 *encap_dev = e->out_dev;
232c0013
HHZ		 2464 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2465 attr->encap_id = e->encap_id;
b2812089
VB		 2466 else
2467 err = -EAGAIN;
45247bf2 2468
232c0013 2469 return err;
a54e20b4
HHZ		 2470
2471out_err:
2472 kfree(e);
2473 return err;
2474}
2475
03a9d11e 2476static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 2477 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 2478 struct mlx5e_tc_flow *flow)
03a9d11e 2479{
ecf5bb79 2480 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2481 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 2482 struct ip_tunnel_info *info = NULL;
03a9d11e 2483 const struct tc_action *a;
22dc13c8 2484 LIST_HEAD(actions);
a54e20b4 2485 bool encap = false;
1cab1cd7 2486 u32 action = 0;
03a9d11e 2487
3bcc0cec 2488 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 2489 return -EINVAL;
2490
1d447a39 2491 attr->in_rep = rpriv->rep;
03a9d11e 2492
22dc13c8
WC		 2493 tcf_exts_to_list(exts, &actions);
2494 list_for_each_entry(a, &actions, list) {
03a9d11e 2495 if (is_tcf_gact_shot(a)) {
1cab1cd7
OG		 2496 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2497 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 2498 continue;
2499 }
2500
d7e75a32 2501 if (is_tcf_pedit(a)) {
31c8eba5
OG		 2502 int err;
2503
d7e75a32
OG		 2504 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
2505 parse_attr);
2506 if (err)
2507 return err;
2508
1cab1cd7 2509 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
d7e75a32
OG		 2510 continue;
2511 }
2512
26c02749 2513 if (is_tcf_csum(a)) {
1cab1cd7 2514 if (csum_offload_supported(priv, action,
26c02749
OG		 2515 tcf_csum_update_flags(a)))
2516 continue;
2517
2518 return -EOPNOTSUPP;
2519 }
2520
5724b8b5 2521 if (is_tcf_mirred_egress_redirect(a)) {
3c37745e 2522 struct net_device *out_dev;
03a9d11e 2523 struct mlx5e_priv *out_priv;
03a9d11e 2524
9f8a739e 2525 out_dev = tcf_mirred_dev(a);
03a9d11e 2526
a54e20b4
HHZ		 2527 if (switchdev_port_same_parent_id(priv->netdev,
2528 out_dev)) {
1cab1cd7
OG		 2529 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2530 MLX5_FLOW_CONTEXT_ACTION_COUNT;
a54e20b4 2531 out_priv = netdev_priv(out_dev);
1d447a39
SM		 2532 rpriv = out_priv->ppriv;
2533 attr->out_rep = rpriv->rep;
a54e20b4 2534 } else if (encap) {
9f8a739e 2535 parse_attr->mirred_ifindex = out_dev->ifindex;
3c37745e
OG		 2536 parse_attr->tun_info = *info;
2537 attr->parse_attr = parse_attr;
1cab1cd7
OG		 2538 action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
2539 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2540 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3c37745e 2541 /* attr->out_rep is resolved when we handle encap */
a54e20b4 2542 } else {
03a9d11e
OG		 2543 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2544 priv->netdev->name, out_dev->name);
2545 return -EINVAL;
2546 }
a54e20b4
HHZ		 2547 continue;
2548 }
03a9d11e 2549
a54e20b4
HHZ		 2550 if (is_tcf_tunnel_set(a)) {
2551 info = tcf_tunnel_info(a);
2552 if (info)
2553 encap = true;
2554 else
2555 return -EOPNOTSUPP;
03a9d11e
OG		 2556 continue;
2557 }
2558
8b32580d 2559 if (is_tcf_vlan(a)) {
09c91ddf 2560 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
1cab1cd7 2561 action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 2562 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
1cab1cd7 2563 action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
6acfbf38
OG		 2564 attr->vlan_vid = tcf_vlan_push_vid(a);
2565 if (mlx5_eswitch_vlan_actions_supported(priv->mdev)) {
2566 attr->vlan_prio = tcf_vlan_push_prio(a);
2567 attr->vlan_proto = tcf_vlan_push_proto(a);
2568 if (!attr->vlan_proto)
2569 attr->vlan_proto = htons(ETH_P_8021Q);
2570 } else if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2571 tcf_vlan_push_prio(a)) {
2572 return -EOPNOTSUPP;
2573 }
09c91ddf
OG		 2574 } else { /* action is TCA_VLAN_ACT_MODIFY */
2575 return -EOPNOTSUPP;
8b32580d
OG		 2576 }
2577 continue;
2578 }
2579
bbd00f7e 2580 if (is_tcf_tunnel_release(a)) {
1cab1cd7 2581 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bbd00f7e
HHZ		 2582 continue;
2583 }
2584
03a9d11e
OG		 2585 return -EINVAL;
2586 }
bdd66ac0 2587
1cab1cd7 2588 attr->action = action;
bdd66ac0
OG		 2589 if (!actions_match_supported(priv, exts, parse_attr, flow))
2590 return -EOPNOTSUPP;
2591
31c8eba5 2592 return 0;
03a9d11e
OG		 2593}
2594
5fd9fc4e 2595int mlx5e_configure_flower(struct mlx5e_priv *priv,
e3a2b7ed
AV		 2596 struct tc_cls_flower_offload *f)
2597{
3bc4b7bf 2598 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 2599 struct mlx5e_tc_flow_parse_attr *parse_attr;
acff797c 2600 struct mlx5e_tc_table *tc = &priv->fs.tc;
3bc4b7bf
OG		 2601 struct mlx5e_tc_flow *flow;
2602 int attr_size, err = 0;
65ba8fb7 2603 u8 flow_flags = 0;
e3a2b7ed 2604
65ba8fb7
OG		 2605 if (esw && esw->mode == SRIOV_OFFLOADS) {
2606 flow_flags = MLX5E_TC_FLOW_ESWITCH;
2607 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf
OG		 2608 } else {
2609 flow_flags = MLX5E_TC_FLOW_NIC;
2610 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 2611 }
e3a2b7ed 2612
65ba8fb7 2613 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2614 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2615 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2616 err = -ENOMEM;
2617 goto err_free;
2618 }
2619
2620 flow->cookie = f->cookie;
65ba8fb7 2621 flow->flags = flow_flags;
e3a2b7ed 2622
17091853 2623 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV		 2624 if (err < 0)
2625 goto err_free;
2626
65ba8fb7 2627 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 2628 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123 2629 if (err < 0)
3c37745e 2630 goto err_free;
aa0cbbae 2631 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 2632 } else {
aa0cbbae 2633 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG		 2634 if (err < 0)
2635 goto err_free;
aa0cbbae 2636 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 2637 }
e3a2b7ed 2638
e3a2b7ed
AV		 2639 if (IS_ERR(flow->rule)) {
2640 err = PTR_ERR(flow->rule);
3c37745e
OG		 2641 if (err != -EAGAIN)
2642 goto err_free;
e3a2b7ed
AV		 2643 }
2644
3c37745e
OG		 2645 if (err != -EAGAIN)
2646 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2647
af1607c3
JL		 2648 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
2649 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
2650 kvfree(parse_attr);
2651
5c40348c
OG		 2652 err = rhashtable_insert_fast(&tc->ht, &flow->node,
2653 tc->ht_params);
af1607c3
JL		 2654 if (err) {
2655 mlx5e_tc_del_flow(priv, flow);
2656 kfree(flow);
2657 }
5c40348c 2658
232c0013 2659 return err;
e3a2b7ed 2660
e3a2b7ed 2661err_free:
17091853 2662 kvfree(parse_attr);
232c0013 2663 kfree(flow);
e3a2b7ed
AV		 2664 return err;
2665}
2666
2667int mlx5e_delete_flower(struct mlx5e_priv *priv,
2668 struct tc_cls_flower_offload *f)
2669{
2670 struct mlx5e_tc_flow *flow;
acff797c 2671 struct mlx5e_tc_table *tc = &priv->fs.tc;
e3a2b7ed
AV		 2672
2673 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2674 tc->ht_params);
2675 if (!flow)
2676 return -EINVAL;
2677
2678 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
2679
961e8979 2680 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 2681
2682 kfree(flow);
2683
2684 return 0;
2685}
2686
aad7e08d
AV		 2687int mlx5e_stats_flower(struct mlx5e_priv *priv,
2688 struct tc_cls_flower_offload *f)
2689{
2690 struct mlx5e_tc_table *tc = &priv->fs.tc;
2691 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 2692 struct mlx5_fc *counter;
2693 u64 bytes;
2694 u64 packets;
2695 u64 lastuse;
2696
2697 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2698 tc->ht_params);
2699 if (!flow)
2700 return -EINVAL;
2701
0b67a38f
HHZ		 2702 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2703 return 0;
2704
aad7e08d
AV		 2705 counter = mlx5_flow_rule_counter(flow->rule);
2706 if (!counter)
2707 return 0;
2708
2709 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2710
d897a638 2711 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 2712
aad7e08d
AV		 2713 return 0;
2714}
2715
e8f887ac
AV		 2716static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
2717 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2718 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2719 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2720 .automatic_shrinking = true,
2721};
2722
2723int mlx5e_tc_init(struct mlx5e_priv *priv)
2724{
acff797c 2725 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 2726
11c9c548 2727 hash_init(tc->mod_hdr_tbl);
5c65c564 2728 hash_init(tc->hairpin_tbl);
11c9c548 2729
e8f887ac
AV		 2730 tc->ht_params = mlx5e_tc_flow_ht_params;
2731 return rhashtable_init(&tc->ht, &tc->ht_params);
2732}
2733
2734static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2735{
2736 struct mlx5e_tc_flow *flow = ptr;
2737 struct mlx5e_priv *priv = arg;
2738
961e8979 2739 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 2740 kfree(flow);
2741}
2742
2743void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
2744{
acff797c 2745 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV		 2746
2747 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
2748
acff797c
MG		 2749 if (!IS_ERR_OR_NULL(tc->t)) {
2750 mlx5_destroy_flow_table(tc->t);
2751 tc->t = NULL;
e8f887ac
AV		 2752 }
2753}
Linux 6.x block layer and io_uring tree(s)