net/sched: act_csum: Add accessors for offloading drivers
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV
1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV
35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV
38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG
41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
a54e20b4 46#include <net/vxlan.h>
f6dfb4c3 47#include <net/arp.h>
e8f887ac 48#include "en.h"
1d447a39 49#include "en_rep.h"
232c0013 50#include "en_tc.h"
03a9d11e 51#include "eswitch.h"
bbd00f7e 52#include "vxlan.h"
e8f887ac 53
3bc4b7bf
OG
54struct mlx5_nic_flow_attr {
55 u32 action;
56 u32 flow_tag;
2f4fe4ca 57 u32 mod_hdr_id;
3bc4b7bf
OG
58};
59
65ba8fb7
OG
60enum {
61 MLX5E_TC_FLOW_ESWITCH = BIT(0),
3bc4b7bf 62 MLX5E_TC_FLOW_NIC = BIT(1),
0b67a38f 63 MLX5E_TC_FLOW_OFFLOADED = BIT(2),
65ba8fb7
OG
64};
65
e8f887ac
AV
66struct mlx5e_tc_flow {
67 struct rhash_head node;
68 u64 cookie;
65ba8fb7 69 u8 flags;
74491de9 70 struct mlx5_flow_handle *rule;
a54e20b4 71 struct list_head encap; /* flows sharing the same encap */
3bc4b7bf
OG
72 union {
73 struct mlx5_esw_flow_attr esw_attr[0];
74 struct mlx5_nic_flow_attr nic_attr[0];
75 };
e8f887ac
AV
76};
77
17091853
OG
78struct mlx5e_tc_flow_parse_attr {
79 struct mlx5_flow_spec spec;
d79b6df6
OG
80 int num_mod_hdr_actions;
81 void *mod_hdr_actions;
17091853
OG
82};
83
a54e20b4
HHZ
84enum {
85 MLX5_HEADER_TYPE_VXLAN = 0x0,
86 MLX5_HEADER_TYPE_NVGRE = 0x1,
87};
88
acff797c
MG
89#define MLX5E_TC_TABLE_NUM_ENTRIES 1024
90#define MLX5E_TC_TABLE_NUM_GROUPS 4
e8f887ac 91
74491de9
MB
92static struct mlx5_flow_handle *
93mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 94 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 95 struct mlx5e_tc_flow *flow)
e8f887ac 96{
aa0cbbae 97 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 98 struct mlx5_core_dev *dev = priv->mdev;
aa0cbbae 99 struct mlx5_flow_destination dest = {};
66958ed9 100 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG
101 .action = attr->action,
102 .flow_tag = attr->flow_tag,
66958ed9
HHZ
103 .encap_id = 0,
104 };
aad7e08d 105 struct mlx5_fc *counter = NULL;
74491de9 106 struct mlx5_flow_handle *rule;
e8f887ac 107 bool table_created = false;
2f4fe4ca 108 int err;
e8f887ac 109
3bc4b7bf 110 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
aad7e08d
AV
111 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
112 dest.ft = priv->fs.vlan.ft.t;
3bc4b7bf 113 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
aad7e08d
AV
114 counter = mlx5_fc_create(dev, true);
115 if (IS_ERR(counter))
116 return ERR_CAST(counter);
117
118 dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
119 dest.counter = counter;
120 }
121
2f4fe4ca
OG
122 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
123 err = mlx5_modify_header_alloc(dev, MLX5_FLOW_NAMESPACE_KERNEL,
124 parse_attr->num_mod_hdr_actions,
125 parse_attr->mod_hdr_actions,
126 &attr->mod_hdr_id);
d7e75a32 127 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG
128 kfree(parse_attr->mod_hdr_actions);
129 if (err) {
130 rule = ERR_PTR(err);
131 goto err_create_mod_hdr_id;
132 }
133 }
134
acff797c
MG
135 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
136 priv->fs.tc.t =
137 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
138 MLX5E_TC_PRIO,
139 MLX5E_TC_TABLE_NUM_ENTRIES,
140 MLX5E_TC_TABLE_NUM_GROUPS,
c9f1b073 141 0, 0);
acff797c 142 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV
143 netdev_err(priv->netdev,
144 "Failed to create tc offload table\n");
aad7e08d
AV
145 rule = ERR_CAST(priv->fs.tc.t);
146 goto err_create_ft;
e8f887ac
AV
147 }
148
149 table_created = true;
150 }
151
17091853
OG
152 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
153 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
154 &flow_act, &dest, 1);
aad7e08d
AV
155
156 if (IS_ERR(rule))
157 goto err_add_rule;
158
159 return rule;
e8f887ac 160
aad7e08d
AV
161err_add_rule:
162 if (table_created) {
acff797c
MG
163 mlx5_destroy_flow_table(priv->fs.tc.t);
164 priv->fs.tc.t = NULL;
e8f887ac 165 }
aad7e08d 166err_create_ft:
2f4fe4ca
OG
167 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
168 mlx5_modify_header_dealloc(priv->mdev,
169 attr->mod_hdr_id);
170err_create_mod_hdr_id:
aad7e08d 171 mlx5_fc_destroy(dev, counter);
e8f887ac
AV
172
173 return rule;
174}
175
d85cdccb
OG
176static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
177 struct mlx5e_tc_flow *flow)
178{
179 struct mlx5_fc *counter = NULL;
180
aa0cbbae
OG
181 counter = mlx5_flow_rule_counter(flow->rule);
182 mlx5_del_flow_rules(flow->rule);
183 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb
OG
184
185 if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
186 mlx5_destroy_flow_table(priv->fs.tc.t);
187 priv->fs.tc.t = NULL;
188 }
2f4fe4ca
OG
189
190 if (flow->nic_attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
191 mlx5_modify_header_dealloc(priv->mdev,
192 flow->nic_attr->mod_hdr_id);
d85cdccb
OG
193}
194
aa0cbbae
OG
195static void mlx5e_detach_encap(struct mlx5e_priv *priv,
196 struct mlx5e_tc_flow *flow);
197
74491de9
MB
198static struct mlx5_flow_handle *
199mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 200 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 201 struct mlx5e_tc_flow *flow)
adb4c123
OG
202{
203 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae
OG
204 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
205 struct mlx5_flow_handle *rule;
8b32580d
OG
206 int err;
207
208 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG
209 if (err) {
210 rule = ERR_PTR(err);
211 goto err_add_vlan;
212 }
adb4c123 213
d7e75a32
OG
214 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
215 err = mlx5_modify_header_alloc(priv->mdev, MLX5_FLOW_NAMESPACE_FDB,
216 parse_attr->num_mod_hdr_actions,
217 parse_attr->mod_hdr_actions,
218 &attr->mod_hdr_id);
219 kfree(parse_attr->mod_hdr_actions);
220 if (err) {
221 rule = ERR_PTR(err);
222 goto err_mod_hdr;
223 }
224 }
225
aa0cbbae
OG
226 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
227 if (IS_ERR(rule))
228 goto err_add_rule;
adb4c123 229
aa0cbbae
OG
230 return rule;
231
232err_add_rule:
d7e75a32
OG
233 if (flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
234 mlx5_modify_header_dealloc(priv->mdev,
235 attr->mod_hdr_id);
236err_mod_hdr:
aa0cbbae
OG
237 mlx5_eswitch_del_vlan_action(esw, attr);
238err_add_vlan:
239 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
240 mlx5e_detach_encap(priv, flow);
aa0cbbae
OG
241 return rule;
242}
d85cdccb
OG
243
244static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
245 struct mlx5e_tc_flow *flow)
246{
247 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 248 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 249
232c0013
HHZ
250 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
251 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
0b67a38f 252 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, flow->esw_attr);
232c0013 253 }
d85cdccb 254
ecf5bb79 255 mlx5_eswitch_del_vlan_action(esw, flow->esw_attr);
d85cdccb 256
232c0013 257 if (flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
d85cdccb 258 mlx5e_detach_encap(priv, flow);
232c0013
HHZ
259 kvfree(flow->esw_attr->parse_attr);
260 }
d7e75a32
OG
261
262 if (flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
263 mlx5_modify_header_dealloc(priv->mdev,
264 attr->mod_hdr_id);
d85cdccb
OG
265}
266
232c0013
HHZ
267void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
268 struct mlx5e_encap_entry *e)
269{
270 struct mlx5e_tc_flow *flow;
271 int err;
272
273 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
274 e->encap_size, e->encap_header,
275 &e->encap_id);
276 if (err) {
277 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
278 err);
279 return;
280 }
281 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 282 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ
283
284 list_for_each_entry(flow, &e->flows, encap) {
285 flow->esw_attr->encap_id = e->encap_id;
286 flow->rule = mlx5e_tc_add_fdb_flow(priv,
287 flow->esw_attr->parse_attr,
288 flow);
289 if (IS_ERR(flow->rule)) {
290 err = PTR_ERR(flow->rule);
291 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
292 err);
293 continue;
294 }
295 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
296 }
297}
298
299void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
300 struct mlx5e_encap_entry *e)
301{
302 struct mlx5e_tc_flow *flow;
303 struct mlx5_fc *counter;
304
305 list_for_each_entry(flow, &e->flows, encap) {
306 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
307 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
308 counter = mlx5_flow_rule_counter(flow->rule);
309 mlx5_del_flow_rules(flow->rule);
310 mlx5_fc_destroy(priv->mdev, counter);
311 }
312 }
313
314 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
315 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
316 mlx5_encap_dealloc(priv->mdev, e->encap_id);
317 }
318}
319
f6dfb4c3
HHZ
320void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
321{
322 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
323 u64 bytes, packets, lastuse = 0;
324 struct mlx5e_tc_flow *flow;
325 struct mlx5e_encap_entry *e;
326 struct mlx5_fc *counter;
327 struct neigh_table *tbl;
328 bool neigh_used = false;
329 struct neighbour *n;
330
331 if (m_neigh->family == AF_INET)
332 tbl = &arp_tbl;
333#if IS_ENABLED(CONFIG_IPV6)
334 else if (m_neigh->family == AF_INET6)
335 tbl = ipv6_stub->nd_tbl;
336#endif
337 else
338 return;
339
340 list_for_each_entry(e, &nhe->encap_list, encap_list) {
341 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
342 continue;
343 list_for_each_entry(flow, &e->flows, encap) {
344 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
345 counter = mlx5_flow_rule_counter(flow->rule);
346 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
347 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
348 neigh_used = true;
349 break;
350 }
351 }
352 }
353 }
354
355 if (neigh_used) {
356 nhe->reported_lastuse = jiffies;
357
358 /* find the relevant neigh according to the cached device and
359 * dst ip pair
360 */
361 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
362 if (!n) {
363 WARN(1, "The neighbour already freed\n");
364 return;
365 }
366
367 neigh_event_send(n, NULL);
368 neigh_release(n);
369 }
370}
371
d85cdccb
OG
372static void mlx5e_detach_encap(struct mlx5e_priv *priv,
373 struct mlx5e_tc_flow *flow)
374{
5067b602
RD
375 struct list_head *next = flow->encap.next;
376
377 list_del(&flow->encap);
378 if (list_empty(next)) {
c1ae1152 379 struct mlx5e_encap_entry *e;
5067b602 380
c1ae1152 381 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ
382 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
383
384 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
5067b602 385 mlx5_encap_dealloc(priv->mdev, e->encap_id);
232c0013 386
cdc5a7f3 387 hash_del_rcu(&e->encap_hlist);
232c0013 388 kfree(e->encap_header);
5067b602
RD
389 kfree(e);
390 }
391}
392
e8f887ac 393static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 394 struct mlx5e_tc_flow *flow)
e8f887ac 395{
d85cdccb
OG
396 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
397 mlx5e_tc_del_fdb_flow(priv, flow);
398 else
399 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV
400}
401
bbd00f7e
HHZ
402static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
403 struct tc_cls_flower_offload *f)
404{
405 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
406 outer_headers);
407 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
408 outer_headers);
409 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
410 misc_parameters);
411 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
412 misc_parameters);
413
414 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
415 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
416
417 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
418 struct flow_dissector_key_keyid *key =
419 skb_flow_dissector_target(f->dissector,
420 FLOW_DISSECTOR_KEY_ENC_KEYID,
421 f->key);
422 struct flow_dissector_key_keyid *mask =
423 skb_flow_dissector_target(f->dissector,
424 FLOW_DISSECTOR_KEY_ENC_KEYID,
425 f->mask);
426 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
427 be32_to_cpu(mask->keyid));
428 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
429 be32_to_cpu(key->keyid));
430 }
431}
432
433static int parse_tunnel_attr(struct mlx5e_priv *priv,
434 struct mlx5_flow_spec *spec,
435 struct tc_cls_flower_offload *f)
436{
437 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
438 outer_headers);
439 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
440 outer_headers);
441
2e72eb43
OG
442 struct flow_dissector_key_control *enc_control =
443 skb_flow_dissector_target(f->dissector,
444 FLOW_DISSECTOR_KEY_ENC_CONTROL,
445 f->key);
446
bbd00f7e
HHZ
447 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
448 struct flow_dissector_key_ports *key =
449 skb_flow_dissector_target(f->dissector,
450 FLOW_DISSECTOR_KEY_ENC_PORTS,
451 f->key);
452 struct flow_dissector_key_ports *mask =
453 skb_flow_dissector_target(f->dissector,
454 FLOW_DISSECTOR_KEY_ENC_PORTS,
455 f->mask);
1ad9a00a
PB
456 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
457 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
458 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ
459
460 /* Full udp dst port must be given */
461 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 462 goto vxlan_match_offload_err;
bbd00f7e 463
1ad9a00a 464 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ
465 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
466 parse_vxlan_attr(spec, f);
2fcd82e9
OG
467 else {
468 netdev_warn(priv->netdev,
469 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 470 return -EOPNOTSUPP;
2fcd82e9 471 }
bbd00f7e
HHZ
472
473 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
474 udp_dport, ntohs(mask->dst));
475 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
476 udp_dport, ntohs(key->dst));
477
cd377663
OG
478 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
479 udp_sport, ntohs(mask->src));
480 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
481 udp_sport, ntohs(key->src));
bbd00f7e 482 } else { /* udp dst port must be given */
2fcd82e9
OG
483vxlan_match_offload_err:
484 netdev_warn(priv->netdev,
485 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
486 return -EOPNOTSUPP;
bbd00f7e
HHZ
487 }
488
2e72eb43 489 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ
490 struct flow_dissector_key_ipv4_addrs *key =
491 skb_flow_dissector_target(f->dissector,
492 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
493 f->key);
494 struct flow_dissector_key_ipv4_addrs *mask =
495 skb_flow_dissector_target(f->dissector,
496 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
497 f->mask);
498 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
499 src_ipv4_src_ipv6.ipv4_layout.ipv4,
500 ntohl(mask->src));
501 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
502 src_ipv4_src_ipv6.ipv4_layout.ipv4,
503 ntohl(key->src));
504
505 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
506 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
507 ntohl(mask->dst));
508 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
509 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
510 ntohl(key->dst));
bbd00f7e 511
2e72eb43
OG
512 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
513 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG
514 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
515 struct flow_dissector_key_ipv6_addrs *key =
516 skb_flow_dissector_target(f->dissector,
517 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
518 f->key);
519 struct flow_dissector_key_ipv6_addrs *mask =
520 skb_flow_dissector_target(f->dissector,
521 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
522 f->mask);
523
524 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
525 src_ipv4_src_ipv6.ipv6_layout.ipv6),
526 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
527 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
528 src_ipv4_src_ipv6.ipv6_layout.ipv6),
529 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
530
531 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
532 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
533 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
534 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
535 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
536 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
537
538 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
539 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 540 }
bbd00f7e
HHZ
541
542 /* Enforce DMAC when offloading incoming tunneled flows.
543 * Flow counters require a match on the DMAC.
544 */
545 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
546 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
547 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
548 dmac_47_16), priv->netdev->dev_addr);
549
550 /* let software handle IP fragments */
551 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
552 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
553
554 return 0;
555}
556
de0af0bf
RD
557static int __parse_cls_flower(struct mlx5e_priv *priv,
558 struct mlx5_flow_spec *spec,
559 struct tc_cls_flower_offload *f,
560 u8 *min_inline)
e3a2b7ed 561{
c5bb1730
MG
562 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
563 outer_headers);
564 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
565 outer_headers);
e3a2b7ed
AV
566 u16 addr_type = 0;
567 u8 ip_proto = 0;
568
de0af0bf
RD
569 *min_inline = MLX5_INLINE_MODE_L2;
570
e3a2b7ed
AV
571 if (f->dissector->used_keys &
572 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
573 BIT(FLOW_DISSECTOR_KEY_BASIC) |
574 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 575 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV
576 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
577 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ
578 BIT(FLOW_DISSECTOR_KEY_PORTS) |
579 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
580 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
581 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
582 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
583 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL))) {
e3a2b7ed
AV
584 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
585 f->dissector->used_keys);
586 return -EOPNOTSUPP;
587 }
588
bbd00f7e
HHZ
589 if ((dissector_uses_key(f->dissector,
590 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
591 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
592 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
593 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
594 struct flow_dissector_key_control *key =
595 skb_flow_dissector_target(f->dissector,
596 FLOW_DISSECTOR_KEY_ENC_CONTROL,
597 f->key);
598 switch (key->addr_type) {
599 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 600 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ
601 if (parse_tunnel_attr(priv, spec, f))
602 return -EOPNOTSUPP;
603 break;
604 default:
605 return -EOPNOTSUPP;
606 }
607
608 /* In decap flow, header pointers should point to the inner
609 * headers, outer header were already set by parse_tunnel_attr
610 */
611 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
612 inner_headers);
613 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
614 inner_headers);
615 }
616
e3a2b7ed
AV
617 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
618 struct flow_dissector_key_control *key =
619 skb_flow_dissector_target(f->dissector,
1dbd0d37 620 FLOW_DISSECTOR_KEY_CONTROL,
e3a2b7ed 621 f->key);
3f7d0eb4
OG
622
623 struct flow_dissector_key_control *mask =
624 skb_flow_dissector_target(f->dissector,
625 FLOW_DISSECTOR_KEY_CONTROL,
626 f->mask);
e3a2b7ed 627 addr_type = key->addr_type;
3f7d0eb4
OG
628
629 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
630 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
631 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
632 key->flags & FLOW_DIS_IS_FRAGMENT);
0827444d
OG
633
634 /* the HW doesn't need L3 inline to match on frag=no */
635 if (key->flags & FLOW_DIS_IS_FRAGMENT)
636 *min_inline = MLX5_INLINE_MODE_IP;
3f7d0eb4 637 }
e3a2b7ed
AV
638 }
639
640 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
641 struct flow_dissector_key_basic *key =
642 skb_flow_dissector_target(f->dissector,
643 FLOW_DISSECTOR_KEY_BASIC,
644 f->key);
645 struct flow_dissector_key_basic *mask =
646 skb_flow_dissector_target(f->dissector,
647 FLOW_DISSECTOR_KEY_BASIC,
648 f->mask);
649 ip_proto = key->ip_proto;
650
651 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
652 ntohs(mask->n_proto));
653 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
654 ntohs(key->n_proto));
655
656 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
657 mask->ip_proto);
658 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
659 key->ip_proto);
de0af0bf
RD
660
661 if (mask->ip_proto)
662 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV
663 }
664
665 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
666 struct flow_dissector_key_eth_addrs *key =
667 skb_flow_dissector_target(f->dissector,
668 FLOW_DISSECTOR_KEY_ETH_ADDRS,
669 f->key);
670 struct flow_dissector_key_eth_addrs *mask =
671 skb_flow_dissector_target(f->dissector,
672 FLOW_DISSECTOR_KEY_ETH_ADDRS,
673 f->mask);
674
675 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
676 dmac_47_16),
677 mask->dst);
678 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
679 dmac_47_16),
680 key->dst);
681
682 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
683 smac_47_16),
684 mask->src);
685 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
686 smac_47_16),
687 key->src);
688 }
689
095b6cfd
OG
690 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
691 struct flow_dissector_key_vlan *key =
692 skb_flow_dissector_target(f->dissector,
693 FLOW_DISSECTOR_KEY_VLAN,
694 f->key);
695 struct flow_dissector_key_vlan *mask =
696 skb_flow_dissector_target(f->dissector,
697 FLOW_DISSECTOR_KEY_VLAN,
698 f->mask);
358d79a4 699 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY
700 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
701 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG
702
703 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
704 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG
705
706 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
707 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
095b6cfd
OG
708 }
709 }
710
e3a2b7ed
AV
711 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
712 struct flow_dissector_key_ipv4_addrs *key =
713 skb_flow_dissector_target(f->dissector,
714 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
715 f->key);
716 struct flow_dissector_key_ipv4_addrs *mask =
717 skb_flow_dissector_target(f->dissector,
718 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
719 f->mask);
720
721 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
722 src_ipv4_src_ipv6.ipv4_layout.ipv4),
723 &mask->src, sizeof(mask->src));
724 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
725 src_ipv4_src_ipv6.ipv4_layout.ipv4),
726 &key->src, sizeof(key->src));
727 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
728 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
729 &mask->dst, sizeof(mask->dst));
730 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
731 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
732 &key->dst, sizeof(key->dst));
de0af0bf
RD
733
734 if (mask->src || mask->dst)
735 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV
736 }
737
738 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
739 struct flow_dissector_key_ipv6_addrs *key =
740 skb_flow_dissector_target(f->dissector,
741 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
742 f->key);
743 struct flow_dissector_key_ipv6_addrs *mask =
744 skb_flow_dissector_target(f->dissector,
745 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
746 f->mask);
747
748 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
749 src_ipv4_src_ipv6.ipv6_layout.ipv6),
750 &mask->src, sizeof(mask->src));
751 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
752 src_ipv4_src_ipv6.ipv6_layout.ipv6),
753 &key->src, sizeof(key->src));
754
755 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
756 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
757 &mask->dst, sizeof(mask->dst));
758 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
759 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
760 &key->dst, sizeof(key->dst));
de0af0bf
RD
761
762 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
763 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
764 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV
765 }
766
767 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
768 struct flow_dissector_key_ports *key =
769 skb_flow_dissector_target(f->dissector,
770 FLOW_DISSECTOR_KEY_PORTS,
771 f->key);
772 struct flow_dissector_key_ports *mask =
773 skb_flow_dissector_target(f->dissector,
774 FLOW_DISSECTOR_KEY_PORTS,
775 f->mask);
776 switch (ip_proto) {
777 case IPPROTO_TCP:
778 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
779 tcp_sport, ntohs(mask->src));
780 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
781 tcp_sport, ntohs(key->src));
782
783 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
784 tcp_dport, ntohs(mask->dst));
785 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
786 tcp_dport, ntohs(key->dst));
787 break;
788
789 case IPPROTO_UDP:
790 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
791 udp_sport, ntohs(mask->src));
792 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
793 udp_sport, ntohs(key->src));
794
795 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
796 udp_dport, ntohs(mask->dst));
797 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
798 udp_dport, ntohs(key->dst));
799 break;
800 default:
801 netdev_err(priv->netdev,
802 "Only UDP and TCP transport are supported\n");
803 return -EINVAL;
804 }
de0af0bf
RD
805
806 if (mask->src || mask->dst)
807 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
e3a2b7ed
AV
808 }
809
810 return 0;
811}
812
de0af0bf 813static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 814 struct mlx5e_tc_flow *flow,
de0af0bf
RD
815 struct mlx5_flow_spec *spec,
816 struct tc_cls_flower_offload *f)
817{
818 struct mlx5_core_dev *dev = priv->mdev;
819 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM
820 struct mlx5e_rep_priv *rpriv = priv->ppriv;
821 struct mlx5_eswitch_rep *rep;
de0af0bf
RD
822 u8 min_inline;
823 int err;
824
825 err = __parse_cls_flower(priv, spec, f, &min_inline);
826
1d447a39
SM
827 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
828 rep = rpriv->rep;
829 if (rep->vport != FDB_UPLINK_VPORT &&
830 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
831 esw->offloads.inline_mode < min_inline)) {
de0af0bf
RD
832 netdev_warn(priv->netdev,
833 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
834 min_inline, esw->offloads.inline_mode);
835 return -EOPNOTSUPP;
836 }
837 }
838
839 return err;
840}
841
d79b6df6
OG
842struct pedit_headers {
843 struct ethhdr eth;
844 struct iphdr ip4;
845 struct ipv6hdr ip6;
846 struct tcphdr tcp;
847 struct udphdr udp;
848};
849
850static int pedit_header_offsets[] = {
851 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
852 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
853 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
854 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
855 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
856};
857
858#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
859
860static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
861 struct pedit_headers *masks,
862 struct pedit_headers *vals)
863{
864 u32 *curr_pmask, *curr_pval;
865
866 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
867 goto out_err;
868
869 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
870 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
871
872 if (*curr_pmask & mask) /* disallow acting twice on the same location */
873 goto out_err;
874
875 *curr_pmask |= mask;
876 *curr_pval |= (val & mask);
877
878 return 0;
879
880out_err:
881 return -EOPNOTSUPP;
882}
883
884struct mlx5_fields {
885 u8 field;
886 u8 size;
887 u32 offset;
888};
889
890static struct mlx5_fields fields[] = {
891 {MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_dest[0])},
892 {MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_dest[4])},
893 {MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_source[0])},
894 {MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_source[4])},
895 {MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE, 2, offsetof(struct pedit_headers, eth.h_proto)},
896
897 {MLX5_ACTION_IN_FIELD_OUT_IP_DSCP, 1, offsetof(struct pedit_headers, ip4.tos)},
898 {MLX5_ACTION_IN_FIELD_OUT_IP_TTL, 1, offsetof(struct pedit_headers, ip4.ttl)},
899 {MLX5_ACTION_IN_FIELD_OUT_SIPV4, 4, offsetof(struct pedit_headers, ip4.saddr)},
900 {MLX5_ACTION_IN_FIELD_OUT_DIPV4, 4, offsetof(struct pedit_headers, ip4.daddr)},
901
902 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[0])},
903 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[1])},
904 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[2])},
905 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[3])},
906 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[0])},
907 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[1])},
908 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[2])},
909 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[3])},
910
911 {MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT, 2, offsetof(struct pedit_headers, tcp.source)},
912 {MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT, 2, offsetof(struct pedit_headers, tcp.dest)},
913 {MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS, 1, offsetof(struct pedit_headers, tcp.ack_seq) + 5},
914
915 {MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT, 2, offsetof(struct pedit_headers, udp.source)},
916 {MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT, 2, offsetof(struct pedit_headers, udp.dest)},
917};
918
919/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
920 * max from the SW pedit action. On success, it says how many HW actions were
921 * actually parsed.
922 */
923static int offload_pedit_fields(struct pedit_headers *masks,
924 struct pedit_headers *vals,
925 struct mlx5e_tc_flow_parse_attr *parse_attr)
926{
927 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
928 int i, action_size, nactions, max_actions, first, last;
929 void *s_masks_p, *a_masks_p, *vals_p;
930 u32 s_mask, a_mask, val;
931 struct mlx5_fields *f;
932 u8 cmd, field_bsize;
933 unsigned long mask;
934 void *action;
935
936 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
937 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
938 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
939 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
940
941 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
942 action = parse_attr->mod_hdr_actions;
943 max_actions = parse_attr->num_mod_hdr_actions;
944 nactions = 0;
945
946 for (i = 0; i < ARRAY_SIZE(fields); i++) {
947 f = &fields[i];
948 /* avoid seeing bits set from previous iterations */
949 s_mask = a_mask = mask = val = 0;
950
951 s_masks_p = (void *)set_masks + f->offset;
952 a_masks_p = (void *)add_masks + f->offset;
953
954 memcpy(&s_mask, s_masks_p, f->size);
955 memcpy(&a_mask, a_masks_p, f->size);
956
957 if (!s_mask && !a_mask) /* nothing to offload here */
958 continue;
959
960 if (s_mask && a_mask) {
961 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
962 return -EOPNOTSUPP;
963 }
964
965 if (nactions == max_actions) {
966 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
967 return -EOPNOTSUPP;
968 }
969
970 if (s_mask) {
971 cmd = MLX5_ACTION_TYPE_SET;
972 mask = s_mask;
973 vals_p = (void *)set_vals + f->offset;
974 /* clear to denote we consumed this field */
975 memset(s_masks_p, 0, f->size);
976 } else {
977 cmd = MLX5_ACTION_TYPE_ADD;
978 mask = a_mask;
979 vals_p = (void *)add_vals + f->offset;
980 /* clear to denote we consumed this field */
981 memset(a_masks_p, 0, f->size);
982 }
983
984 memcpy(&val, vals_p, f->size);
985
986 field_bsize = f->size * BITS_PER_BYTE;
987 first = find_first_bit(&mask, field_bsize);
988 last = find_last_bit(&mask, field_bsize);
989 if (first > 0 || last != (field_bsize - 1)) {
990 printk(KERN_WARNING "mlx5: partial rewrite (mask %lx) is currently not offloaded\n",
991 mask);
992 return -EOPNOTSUPP;
993 }
994
995 MLX5_SET(set_action_in, action, action_type, cmd);
996 MLX5_SET(set_action_in, action, field, f->field);
997
998 if (cmd == MLX5_ACTION_TYPE_SET) {
999 MLX5_SET(set_action_in, action, offset, 0);
1000 /* length is num of bits to be written, zero means length of 32 */
1001 MLX5_SET(set_action_in, action, length, field_bsize);
1002 }
1003
1004 if (field_bsize == 32)
1005 MLX5_SET(set_action_in, action, data, ntohl(val));
1006 else if (field_bsize == 16)
1007 MLX5_SET(set_action_in, action, data, ntohs(val));
1008 else if (field_bsize == 8)
1009 MLX5_SET(set_action_in, action, data, val);
1010
1011 action += action_size;
1012 nactions++;
1013 }
1014
1015 parse_attr->num_mod_hdr_actions = nactions;
1016 return 0;
1017}
1018
1019static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1020 const struct tc_action *a, int namespace,
1021 struct mlx5e_tc_flow_parse_attr *parse_attr)
1022{
1023 int nkeys, action_size, max_actions;
1024
1025 nkeys = tcf_pedit_nkeys(a);
1026 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1027
1028 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1029 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1030 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1031 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1032
1033 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1034 max_actions = min(max_actions, nkeys * 16);
1035
1036 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1037 if (!parse_attr->mod_hdr_actions)
1038 return -ENOMEM;
1039
1040 parse_attr->num_mod_hdr_actions = max_actions;
1041 return 0;
1042}
1043
1044static const struct pedit_headers zero_masks = {};
1045
1046static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1047 const struct tc_action *a, int namespace,
1048 struct mlx5e_tc_flow_parse_attr *parse_attr)
1049{
1050 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1051 int nkeys, i, err = -EOPNOTSUPP;
1052 u32 mask, val, offset;
1053 u8 cmd, htype;
1054
1055 nkeys = tcf_pedit_nkeys(a);
1056
1057 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1058 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1059
1060 for (i = 0; i < nkeys; i++) {
1061 htype = tcf_pedit_htype(a, i);
1062 cmd = tcf_pedit_cmd(a, i);
1063 err = -EOPNOTSUPP; /* can't be all optimistic */
1064
1065 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
1066 printk(KERN_WARNING "mlx5: legacy pedit isn't offloaded\n");
1067 goto out_err;
1068 }
1069
1070 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
1071 printk(KERN_WARNING "mlx5: pedit cmd %d isn't offloaded\n", cmd);
1072 goto out_err;
1073 }
1074
1075 mask = tcf_pedit_mask(a, i);
1076 val = tcf_pedit_val(a, i);
1077 offset = tcf_pedit_offset(a, i);
1078
1079 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1080 if (err)
1081 goto out_err;
1082 }
1083
1084 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1085 if (err)
1086 goto out_err;
1087
1088 err = offload_pedit_fields(masks, vals, parse_attr);
1089 if (err < 0)
1090 goto out_dealloc_parsed_actions;
1091
1092 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1093 cmd_masks = &masks[cmd];
1094 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
1095 printk(KERN_WARNING "mlx5: attempt to offload an unsupported field (cmd %d)\n",
1096 cmd);
1097 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1098 16, 1, cmd_masks, sizeof(zero_masks), true);
1099 err = -EOPNOTSUPP;
1100 goto out_dealloc_parsed_actions;
1101 }
1102 }
1103
1104 return 0;
1105
1106out_dealloc_parsed_actions:
1107 kfree(parse_attr->mod_hdr_actions);
1108out_err:
1109 return err;
1110}
1111
5c40348c 1112static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG
1113 struct mlx5e_tc_flow_parse_attr *parse_attr,
1114 struct mlx5e_tc_flow *flow)
e3a2b7ed 1115{
aa0cbbae 1116 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1117 const struct tc_action *a;
22dc13c8 1118 LIST_HEAD(actions);
2f4fe4ca 1119 int err;
e3a2b7ed
AV
1120
1121 if (tc_no_actions(exts))
1122 return -EINVAL;
1123
3bc4b7bf
OG
1124 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1125 attr->action = 0;
e3a2b7ed 1126
22dc13c8
WC
1127 tcf_exts_to_list(exts, &actions);
1128 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1129 /* Only support a single action per rule */
3bc4b7bf 1130 if (attr->action)
e3a2b7ed
AV
1131 return -EINVAL;
1132
1133 if (is_tcf_gact_shot(a)) {
3bc4b7bf 1134 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV
1135 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1136 flow_table_properties_nic_receive.flow_counter))
3bc4b7bf 1137 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV
1138 continue;
1139 }
1140
2f4fe4ca
OG
1141 if (is_tcf_pedit(a)) {
1142 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1143 parse_attr);
1144 if (err)
1145 return err;
1146
1147 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1148 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1149 continue;
1150 }
1151
e3a2b7ed
AV
1152 if (is_tcf_skbedit_mark(a)) {
1153 u32 mark = tcf_skbedit_mark(a);
1154
1155 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
1156 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
1157 mark);
1158 return -EINVAL;
1159 }
1160
3bc4b7bf
OG
1161 attr->flow_tag = mark;
1162 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV
1163 continue;
1164 }
1165
1166 return -EINVAL;
1167 }
1168
1169 return 0;
1170}
1171
76f7444d
OG
1172static inline int cmp_encap_info(struct ip_tunnel_key *a,
1173 struct ip_tunnel_key *b)
a54e20b4
HHZ
1174{
1175 return memcmp(a, b, sizeof(*a));
1176}
1177
76f7444d 1178static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 1179{
76f7444d 1180 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ
1181}
1182
1183static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
1184 struct net_device *mirred_dev,
1185 struct net_device **out_dev,
1186 struct flowi4 *fl4,
1187 struct neighbour **out_n,
a54e20b4
HHZ
1188 int *out_ttl)
1189{
3e621b19 1190 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a54e20b4
HHZ
1191 struct rtable *rt;
1192 struct neighbour *n = NULL;
a54e20b4
HHZ
1193
1194#if IS_ENABLED(CONFIG_INET)
abeffce9
AB
1195 int ret;
1196
a54e20b4 1197 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB
1198 ret = PTR_ERR_OR_ZERO(rt);
1199 if (ret)
1200 return ret;
a54e20b4
HHZ
1201#else
1202 return -EOPNOTSUPP;
1203#endif
3e621b19
HHZ
1204 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1205 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
1206 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1207 else
1208 *out_dev = rt->dst.dev;
a54e20b4 1209
75c33da8 1210 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ
1211 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
1212 ip_rt_put(rt);
1213 if (!n)
1214 return -ENOMEM;
1215
1216 *out_n = n;
a54e20b4
HHZ
1217 return 0;
1218}
1219
ce99f6b9
OG
1220static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
1221 struct net_device *mirred_dev,
1222 struct net_device **out_dev,
1223 struct flowi6 *fl6,
1224 struct neighbour **out_n,
1225 int *out_ttl)
1226{
1227 struct neighbour *n = NULL;
1228 struct dst_entry *dst;
1229
1230#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
1231 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1232 int ret;
1233
1234 dst = ip6_route_output(dev_net(mirred_dev), NULL, fl6);
321fa4ff
AB
1235 ret = dst->error;
1236 if (ret) {
ce99f6b9
OG
1237 dst_release(dst);
1238 return ret;
1239 }
1240
1241 *out_ttl = ip6_dst_hoplimit(dst);
1242
1243 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1244 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
1245 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1246 else
1247 *out_dev = dst->dev;
1248#else
1249 return -EOPNOTSUPP;
1250#endif
1251
1252 n = dst_neigh_lookup(dst, &fl6->daddr);
1253 dst_release(dst);
1254 if (!n)
1255 return -ENOMEM;
1256
1257 *out_n = n;
1258 return 0;
1259}
1260
32f3671f
OG
1261static void gen_vxlan_header_ipv4(struct net_device *out_dev,
1262 char buf[], int encap_size,
1263 unsigned char h_dest[ETH_ALEN],
1264 int ttl,
1265 __be32 daddr,
1266 __be32 saddr,
1267 __be16 udp_dst_port,
1268 __be32 vx_vni)
a54e20b4 1269{
a54e20b4
HHZ
1270 struct ethhdr *eth = (struct ethhdr *)buf;
1271 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
1272 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
1273 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1274
1275 memset(buf, 0, encap_size);
1276
1277 ether_addr_copy(eth->h_dest, h_dest);
1278 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1279 eth->h_proto = htons(ETH_P_IP);
1280
1281 ip->daddr = daddr;
1282 ip->saddr = saddr;
1283
1284 ip->ttl = ttl;
1285 ip->protocol = IPPROTO_UDP;
1286 ip->version = 0x4;
1287 ip->ihl = 0x5;
1288
1289 udp->dest = udp_dst_port;
1290 vxh->vx_flags = VXLAN_HF_VNI;
1291 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ
1292}
1293
225aabaf
OG
1294static void gen_vxlan_header_ipv6(struct net_device *out_dev,
1295 char buf[], int encap_size,
1296 unsigned char h_dest[ETH_ALEN],
1297 int ttl,
1298 struct in6_addr *daddr,
1299 struct in6_addr *saddr,
1300 __be16 udp_dst_port,
1301 __be32 vx_vni)
ce99f6b9 1302{
ce99f6b9
OG
1303 struct ethhdr *eth = (struct ethhdr *)buf;
1304 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
1305 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
1306 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1307
1308 memset(buf, 0, encap_size);
1309
1310 ether_addr_copy(eth->h_dest, h_dest);
1311 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1312 eth->h_proto = htons(ETH_P_IPV6);
1313
1314 ip6_flow_hdr(ip6h, 0, 0);
1315 /* the HW fills up ipv6 payload len */
1316 ip6h->nexthdr = IPPROTO_UDP;
1317 ip6h->hop_limit = ttl;
1318 ip6h->daddr = *daddr;
1319 ip6h->saddr = *saddr;
1320
1321 udp->dest = udp_dst_port;
1322 vxh->vx_flags = VXLAN_HF_VNI;
1323 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG
1324}
1325
a54e20b4
HHZ
1326static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
1327 struct net_device *mirred_dev,
1a8552bd 1328 struct mlx5e_encap_entry *e)
a54e20b4
HHZ
1329{
1330 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 1331 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 1332 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1333 struct net_device *out_dev;
a42485eb 1334 struct neighbour *n = NULL;
a54e20b4 1335 struct flowi4 fl4 = {};
a54e20b4 1336 char *encap_header;
32f3671f 1337 int ttl, err;
033354d5 1338 u8 nud_state;
32f3671f
OG
1339
1340 if (max_encap_size < ipv4_encap_size) {
1341 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1342 ipv4_encap_size, max_encap_size);
1343 return -EOPNOTSUPP;
1344 }
a54e20b4 1345
32f3671f 1346 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ
1347 if (!encap_header)
1348 return -ENOMEM;
1349
1350 switch (e->tunnel_type) {
1351 case MLX5_HEADER_TYPE_VXLAN:
1352 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 1353 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ
1354 break;
1355 default:
1356 err = -EOPNOTSUPP;
1357 goto out;
1358 }
9a941117 1359 fl4.flowi4_tos = tun_key->tos;
76f7444d 1360 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 1361 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 1362
1a8552bd 1363 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 1364 &fl4, &n, &ttl);
a54e20b4
HHZ
1365 if (err)
1366 goto out;
1367
232c0013
HHZ
1368 /* used by mlx5e_detach_encap to lookup a neigh hash table
1369 * entry in the neigh hash table when a user deletes a rule
1370 */
1371 e->m_neigh.dev = n->dev;
f6dfb4c3 1372 e->m_neigh.family = n->ops->family;
232c0013
HHZ
1373 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1374 e->out_dev = out_dev;
1375
1376 /* It's importent to add the neigh to the hash table before checking
1377 * the neigh validity state. So if we'll get a notification, in case the
1378 * neigh changes it's validity state, we would find the relevant neigh
1379 * in the hash.
1380 */
1381 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1382 if (err)
1383 goto out;
1384
033354d5
HHZ
1385 read_lock_bh(&n->lock);
1386 nud_state = n->nud_state;
1387 ether_addr_copy(e->h_dest, n->ha);
1388 read_unlock_bh(&n->lock);
1389
a54e20b4
HHZ
1390 switch (e->tunnel_type) {
1391 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1392 gen_vxlan_header_ipv4(out_dev, encap_header,
32f3671f
OG
1393 ipv4_encap_size, e->h_dest, ttl,
1394 fl4.daddr,
1395 fl4.saddr, tun_key->tp_dst,
1396 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ
1397 break;
1398 default:
1399 err = -EOPNOTSUPP;
232c0013
HHZ
1400 goto destroy_neigh_entry;
1401 }
1402 e->encap_size = ipv4_encap_size;
1403 e->encap_header = encap_header;
1404
1405 if (!(nud_state & NUD_VALID)) {
1406 neigh_event_send(n, NULL);
1407 neigh_release(n);
1408 return -EAGAIN;
a54e20b4
HHZ
1409 }
1410
1411 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 1412 ipv4_encap_size, encap_header, &e->encap_id);
232c0013
HHZ
1413 if (err)
1414 goto destroy_neigh_entry;
1415
1416 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1417 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ
1418 neigh_release(n);
1419 return err;
1420
1421destroy_neigh_entry:
1422 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
a54e20b4
HHZ
1423out:
1424 kfree(encap_header);
232c0013
HHZ
1425 if (n)
1426 neigh_release(n);
a54e20b4
HHZ
1427 return err;
1428}
1429
ce99f6b9
OG
1430static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
1431 struct net_device *mirred_dev,
1a8552bd 1432 struct mlx5e_encap_entry *e)
ce99f6b9
OG
1433{
1434 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 1435 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 1436 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1437 struct net_device *out_dev;
ce99f6b9
OG
1438 struct neighbour *n = NULL;
1439 struct flowi6 fl6 = {};
1440 char *encap_header;
225aabaf 1441 int err, ttl = 0;
033354d5 1442 u8 nud_state;
ce99f6b9 1443
225aabaf
OG
1444 if (max_encap_size < ipv6_encap_size) {
1445 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1446 ipv6_encap_size, max_encap_size);
1447 return -EOPNOTSUPP;
1448 }
ce99f6b9 1449
225aabaf 1450 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG
1451 if (!encap_header)
1452 return -ENOMEM;
1453
1454 switch (e->tunnel_type) {
1455 case MLX5_HEADER_TYPE_VXLAN:
1456 fl6.flowi6_proto = IPPROTO_UDP;
1457 fl6.fl6_dport = tun_key->tp_dst;
1458 break;
1459 default:
1460 err = -EOPNOTSUPP;
1461 goto out;
1462 }
1463
1464 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
1465 fl6.daddr = tun_key->u.ipv6.dst;
1466 fl6.saddr = tun_key->u.ipv6.src;
1467
1a8552bd 1468 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG
1469 &fl6, &n, &ttl);
1470 if (err)
1471 goto out;
1472
232c0013
HHZ
1473 /* used by mlx5e_detach_encap to lookup a neigh hash table
1474 * entry in the neigh hash table when a user deletes a rule
1475 */
1476 e->m_neigh.dev = n->dev;
f6dfb4c3 1477 e->m_neigh.family = n->ops->family;
232c0013
HHZ
1478 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1479 e->out_dev = out_dev;
1480
1481 /* It's importent to add the neigh to the hash table before checking
1482 * the neigh validity state. So if we'll get a notification, in case the
1483 * neigh changes it's validity state, we would find the relevant neigh
1484 * in the hash.
1485 */
1486 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1487 if (err)
1488 goto out;
1489
033354d5
HHZ
1490 read_lock_bh(&n->lock);
1491 nud_state = n->nud_state;
1492 ether_addr_copy(e->h_dest, n->ha);
1493 read_unlock_bh(&n->lock);
1494
ce99f6b9
OG
1495 switch (e->tunnel_type) {
1496 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1497 gen_vxlan_header_ipv6(out_dev, encap_header,
225aabaf
OG
1498 ipv6_encap_size, e->h_dest, ttl,
1499 &fl6.daddr,
1500 &fl6.saddr, tun_key->tp_dst,
1501 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG
1502 break;
1503 default:
1504 err = -EOPNOTSUPP;
232c0013
HHZ
1505 goto destroy_neigh_entry;
1506 }
1507
1508 e->encap_size = ipv6_encap_size;
1509 e->encap_header = encap_header;
1510
1511 if (!(nud_state & NUD_VALID)) {
1512 neigh_event_send(n, NULL);
1513 neigh_release(n);
1514 return -EAGAIN;
ce99f6b9
OG
1515 }
1516
1517 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 1518 ipv6_encap_size, encap_header, &e->encap_id);
232c0013
HHZ
1519 if (err)
1520 goto destroy_neigh_entry;
1521
1522 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1523 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ
1524 neigh_release(n);
1525 return err;
1526
1527destroy_neigh_entry:
1528 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ce99f6b9 1529out:
ce99f6b9 1530 kfree(encap_header);
232c0013
HHZ
1531 if (n)
1532 neigh_release(n);
ce99f6b9
OG
1533 return err;
1534}
1535
a54e20b4
HHZ
1536static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1537 struct ip_tunnel_info *tun_info,
1538 struct net_device *mirred_dev,
45247bf2
OG
1539 struct net_device **encap_dev,
1540 struct mlx5e_tc_flow *flow)
a54e20b4
HHZ
1541{
1542 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1ad9a00a 1543 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
a54e20b4 1544 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2
OG
1545 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
1546 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 1547 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 1548 struct mlx5e_encap_entry *e;
45247bf2 1549 int tunnel_type, err = 0;
a54e20b4
HHZ
1550 uintptr_t hash_key;
1551 bool found = false;
a54e20b4 1552
2fcd82e9 1553 /* udp dst port must be set */
a54e20b4 1554 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 1555 goto vxlan_encap_offload_err;
a54e20b4 1556
cd377663 1557 /* setting udp src port isn't supported */
2fcd82e9
OG
1558 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
1559vxlan_encap_offload_err:
1560 netdev_warn(priv->netdev,
1561 "must set udp dst port and not set udp src port\n");
cd377663 1562 return -EOPNOTSUPP;
2fcd82e9 1563 }
cd377663 1564
1ad9a00a 1565 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 1566 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ
1567 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
1568 } else {
2fcd82e9
OG
1569 netdev_warn(priv->netdev,
1570 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ
1571 return -EOPNOTSUPP;
1572 }
1573
76f7444d 1574 hash_key = hash_encap_info(key);
a54e20b4
HHZ
1575
1576 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
1577 encap_hlist, hash_key) {
76f7444d 1578 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ
1579 found = true;
1580 break;
1581 }
1582 }
1583
45247bf2
OG
1584 if (found)
1585 goto attach_flow;
a54e20b4
HHZ
1586
1587 e = kzalloc(sizeof(*e), GFP_KERNEL);
1588 if (!e)
1589 return -ENOMEM;
1590
76f7444d 1591 e->tun_info = *tun_info;
a54e20b4
HHZ
1592 e->tunnel_type = tunnel_type;
1593 INIT_LIST_HEAD(&e->flows);
1594
ce99f6b9 1595 if (family == AF_INET)
1a8552bd 1596 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 1597 else if (family == AF_INET6)
1a8552bd 1598 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 1599
232c0013 1600 if (err && err != -EAGAIN)
a54e20b4
HHZ
1601 goto out_err;
1602
a54e20b4
HHZ
1603 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
1604
45247bf2
OG
1605attach_flow:
1606 list_add(&flow->encap, &e->flows);
1607 *encap_dev = e->out_dev;
232c0013
HHZ
1608 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1609 attr->encap_id = e->encap_id;
45247bf2 1610
232c0013 1611 return err;
a54e20b4
HHZ
1612
1613out_err:
1614 kfree(e);
1615 return err;
1616}
1617
03a9d11e 1618static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 1619 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 1620 struct mlx5e_tc_flow *flow)
03a9d11e 1621{
ecf5bb79 1622 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 1623 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 1624 struct ip_tunnel_info *info = NULL;
03a9d11e 1625 const struct tc_action *a;
22dc13c8 1626 LIST_HEAD(actions);
a54e20b4 1627 bool encap = false;
232c0013 1628 int err = 0;
03a9d11e
OG
1629
1630 if (tc_no_actions(exts))
1631 return -EINVAL;
1632
776b12b6 1633 memset(attr, 0, sizeof(*attr));
1d447a39 1634 attr->in_rep = rpriv->rep;
03a9d11e 1635
22dc13c8
WC
1636 tcf_exts_to_list(exts, &actions);
1637 list_for_each_entry(a, &actions, list) {
03a9d11e 1638 if (is_tcf_gact_shot(a)) {
8b32580d
OG
1639 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
1640 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG
1641 continue;
1642 }
1643
d7e75a32
OG
1644 if (is_tcf_pedit(a)) {
1645 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
1646 parse_attr);
1647 if (err)
1648 return err;
1649
1650 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1651 continue;
1652 }
1653
5724b8b5 1654 if (is_tcf_mirred_egress_redirect(a)) {
03a9d11e 1655 int ifindex = tcf_mirred_ifindex(a);
45247bf2 1656 struct net_device *out_dev, *encap_dev = NULL;
03a9d11e 1657 struct mlx5e_priv *out_priv;
03a9d11e
OG
1658
1659 out_dev = __dev_get_by_index(dev_net(priv->netdev), ifindex);
1660
a54e20b4
HHZ
1661 if (switchdev_port_same_parent_id(priv->netdev,
1662 out_dev)) {
1663 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1664 MLX5_FLOW_CONTEXT_ACTION_COUNT;
1665 out_priv = netdev_priv(out_dev);
1d447a39
SM
1666 rpriv = out_priv->ppriv;
1667 attr->out_rep = rpriv->rep;
a54e20b4
HHZ
1668 } else if (encap) {
1669 err = mlx5e_attach_encap(priv, info,
45247bf2 1670 out_dev, &encap_dev, flow);
232c0013 1671 if (err && err != -EAGAIN)
a54e20b4 1672 return err;
a54e20b4
HHZ
1673 attr->action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
1674 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1675 MLX5_FLOW_CONTEXT_ACTION_COUNT;
45247bf2 1676 out_priv = netdev_priv(encap_dev);
1d447a39
SM
1677 rpriv = out_priv->ppriv;
1678 attr->out_rep = rpriv->rep;
232c0013 1679 attr->parse_attr = parse_attr;
a54e20b4 1680 } else {
03a9d11e
OG
1681 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
1682 priv->netdev->name, out_dev->name);
1683 return -EINVAL;
1684 }
a54e20b4
HHZ
1685 continue;
1686 }
03a9d11e 1687
a54e20b4
HHZ
1688 if (is_tcf_tunnel_set(a)) {
1689 info = tcf_tunnel_info(a);
1690 if (info)
1691 encap = true;
1692 else
1693 return -EOPNOTSUPP;
03a9d11e
OG
1694 continue;
1695 }
1696
8b32580d 1697 if (is_tcf_vlan(a)) {
09c91ddf 1698 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
8b32580d 1699 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 1700 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
8b32580d
OG
1701 if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q))
1702 return -EOPNOTSUPP;
1703
1704 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1705 attr->vlan = tcf_vlan_push_vid(a);
09c91ddf
OG
1706 } else { /* action is TCA_VLAN_ACT_MODIFY */
1707 return -EOPNOTSUPP;
8b32580d
OG
1708 }
1709 continue;
1710 }
1711
bbd00f7e
HHZ
1712 if (is_tcf_tunnel_release(a)) {
1713 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
1714 continue;
1715 }
1716
03a9d11e
OG
1717 return -EINVAL;
1718 }
232c0013 1719 return err;
03a9d11e
OG
1720}
1721
e3a2b7ed
AV
1722int mlx5e_configure_flower(struct mlx5e_priv *priv, __be16 protocol,
1723 struct tc_cls_flower_offload *f)
1724{
3bc4b7bf 1725 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 1726 struct mlx5e_tc_flow_parse_attr *parse_attr;
acff797c 1727 struct mlx5e_tc_table *tc = &priv->fs.tc;
3bc4b7bf
OG
1728 struct mlx5e_tc_flow *flow;
1729 int attr_size, err = 0;
65ba8fb7 1730 u8 flow_flags = 0;
e3a2b7ed 1731
65ba8fb7
OG
1732 if (esw && esw->mode == SRIOV_OFFLOADS) {
1733 flow_flags = MLX5E_TC_FLOW_ESWITCH;
1734 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf
OG
1735 } else {
1736 flow_flags = MLX5E_TC_FLOW_NIC;
1737 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 1738 }
e3a2b7ed 1739
65ba8fb7 1740 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
17091853
OG
1741 parse_attr = mlx5_vzalloc(sizeof(*parse_attr));
1742 if (!parse_attr || !flow) {
e3a2b7ed
AV
1743 err = -ENOMEM;
1744 goto err_free;
1745 }
1746
1747 flow->cookie = f->cookie;
65ba8fb7 1748 flow->flags = flow_flags;
e3a2b7ed 1749
17091853 1750 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV
1751 if (err < 0)
1752 goto err_free;
1753
65ba8fb7 1754 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 1755 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123 1756 if (err < 0)
232c0013 1757 goto err_handle_encap_flow;
aa0cbbae 1758 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 1759 } else {
aa0cbbae 1760 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG
1761 if (err < 0)
1762 goto err_free;
aa0cbbae 1763 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 1764 }
e3a2b7ed 1765
e3a2b7ed
AV
1766 if (IS_ERR(flow->rule)) {
1767 err = PTR_ERR(flow->rule);
aa0cbbae 1768 goto err_free;
e3a2b7ed
AV
1769 }
1770
0b67a38f 1771 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
5c40348c
OG
1772 err = rhashtable_insert_fast(&tc->ht, &flow->node,
1773 tc->ht_params);
1774 if (err)
1775 goto err_del_rule;
1776
232c0013
HHZ
1777 if (flow->flags & MLX5E_TC_FLOW_ESWITCH &&
1778 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
1779 kvfree(parse_attr);
1780 return err;
e3a2b7ed 1781
5c40348c 1782err_del_rule:
5e86397a 1783 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed 1784
232c0013
HHZ
1785err_handle_encap_flow:
1786 if (err == -EAGAIN) {
1787 err = rhashtable_insert_fast(&tc->ht, &flow->node,
1788 tc->ht_params);
1789 if (err)
1790 mlx5e_tc_del_flow(priv, flow);
1791 else
1792 return 0;
1793 }
1794
e3a2b7ed 1795err_free:
17091853 1796 kvfree(parse_attr);
232c0013 1797 kfree(flow);
e3a2b7ed
AV
1798 return err;
1799}
1800
1801int mlx5e_delete_flower(struct mlx5e_priv *priv,
1802 struct tc_cls_flower_offload *f)
1803{
1804 struct mlx5e_tc_flow *flow;
acff797c 1805 struct mlx5e_tc_table *tc = &priv->fs.tc;
e3a2b7ed
AV
1806
1807 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
1808 tc->ht_params);
1809 if (!flow)
1810 return -EINVAL;
1811
1812 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
1813
961e8979 1814 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV
1815
1816 kfree(flow);
1817
1818 return 0;
1819}
1820
aad7e08d
AV
1821int mlx5e_stats_flower(struct mlx5e_priv *priv,
1822 struct tc_cls_flower_offload *f)
1823{
1824 struct mlx5e_tc_table *tc = &priv->fs.tc;
1825 struct mlx5e_tc_flow *flow;
1826 struct tc_action *a;
1827 struct mlx5_fc *counter;
22dc13c8 1828 LIST_HEAD(actions);
aad7e08d
AV
1829 u64 bytes;
1830 u64 packets;
1831 u64 lastuse;
1832
1833 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
1834 tc->ht_params);
1835 if (!flow)
1836 return -EINVAL;
1837
0b67a38f
HHZ
1838 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
1839 return 0;
1840
aad7e08d
AV
1841 counter = mlx5_flow_rule_counter(flow->rule);
1842 if (!counter)
1843 return 0;
1844
1845 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1846
fed06ee8
OG
1847 preempt_disable();
1848
22dc13c8
WC
1849 tcf_exts_to_list(f->exts, &actions);
1850 list_for_each_entry(a, &actions, list)
aad7e08d
AV
1851 tcf_action_stats_update(a, bytes, packets, lastuse);
1852
fed06ee8
OG
1853 preempt_enable();
1854
aad7e08d
AV
1855 return 0;
1856}
1857
e8f887ac
AV
1858static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
1859 .head_offset = offsetof(struct mlx5e_tc_flow, node),
1860 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
1861 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
1862 .automatic_shrinking = true,
1863};
1864
1865int mlx5e_tc_init(struct mlx5e_priv *priv)
1866{
acff797c 1867 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV
1868
1869 tc->ht_params = mlx5e_tc_flow_ht_params;
1870 return rhashtable_init(&tc->ht, &tc->ht_params);
1871}
1872
1873static void _mlx5e_tc_del_flow(void *ptr, void *arg)
1874{
1875 struct mlx5e_tc_flow *flow = ptr;
1876 struct mlx5e_priv *priv = arg;
1877
961e8979 1878 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV
1879 kfree(flow);
1880}
1881
1882void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
1883{
acff797c 1884 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV
1885
1886 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
1887
acff797c
MG
1888 if (!IS_ERR_OR_NULL(tc->t)) {
1889 mlx5_destroy_flow_table(tc->t);
1890 tc->t = NULL;
e8f887ac
AV
1891 }
1892}