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net/mlx5e: Add cache for HW modify header IDs
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
bbd00f7e 53#include "vxlan.h"
e8f887ac 54
3bc4b7bf
OG		 55struct mlx5_nic_flow_attr {
56 u32 action;
57 u32 flow_tag;
2f4fe4ca 58 u32 mod_hdr_id;
3bc4b7bf
OG		 59};
60
65ba8fb7
OG		 61enum {
62 MLX5E_TC_FLOW_ESWITCH = BIT(0),
3bc4b7bf 63 MLX5E_TC_FLOW_NIC = BIT(1),
0b67a38f 64 MLX5E_TC_FLOW_OFFLOADED = BIT(2),
65ba8fb7
OG		 65};
66
e8f887ac
AV		 67struct mlx5e_tc_flow {
68 struct rhash_head node;
69 u64 cookie;
65ba8fb7 70 u8 flags;
74491de9 71 struct mlx5_flow_handle *rule;
11c9c548
OG		 72 struct list_head encap; /* flows sharing the same encap ID */
73 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
3bc4b7bf
OG		 74 union {
75 struct mlx5_esw_flow_attr esw_attr[0];
76 struct mlx5_nic_flow_attr nic_attr[0];
77 };
e8f887ac
AV		 78};
79
17091853
OG		 80struct mlx5e_tc_flow_parse_attr {
81 struct mlx5_flow_spec spec;
d79b6df6
OG		 82 int num_mod_hdr_actions;
83 void *mod_hdr_actions;
17091853
OG		 84};
85
a54e20b4
HHZ		 86enum {
87 MLX5_HEADER_TYPE_VXLAN = 0x0,
88 MLX5_HEADER_TYPE_NVGRE = 0x1,
89};
90
acff797c
MG		 91#define MLX5E_TC_TABLE_NUM_ENTRIES 1024
92#define MLX5E_TC_TABLE_NUM_GROUPS 4
e8f887ac 93
11c9c548
OG		 94struct mod_hdr_key {
95 int num_actions;
96 void *actions;
97};
98
99struct mlx5e_mod_hdr_entry {
100 /* a node of a hash table which keeps all the mod_hdr entries */
101 struct hlist_node mod_hdr_hlist;
102
103 /* flows sharing the same mod_hdr entry */
104 struct list_head flows;
105
106 struct mod_hdr_key key;
107
108 u32 mod_hdr_id;
109};
110
111#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
112
113static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
114{
115 return jhash(key->actions,
116 key->num_actions * MLX5_MH_ACT_SZ, 0);
117}
118
119static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
120 struct mod_hdr_key *b)
121{
122 if (a->num_actions != b->num_actions)
123 return 1;
124
125 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
126}
127
128static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
129 struct mlx5e_tc_flow *flow,
130 struct mlx5e_tc_flow_parse_attr *parse_attr)
131{
132 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
133 int num_actions, actions_size, namespace, err;
134 struct mlx5e_mod_hdr_entry *mh;
135 struct mod_hdr_key key;
136 bool found = false;
137 u32 hash_key;
138
139 num_actions = parse_attr->num_mod_hdr_actions;
140 actions_size = MLX5_MH_ACT_SZ * num_actions;
141
142 key.actions = parse_attr->mod_hdr_actions;
143 key.num_actions = num_actions;
144
145 hash_key = hash_mod_hdr_info(&key);
146
147 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
148 namespace = MLX5_FLOW_NAMESPACE_FDB;
149 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
150 mod_hdr_hlist, hash_key) {
151 if (!cmp_mod_hdr_info(&mh->key, &key)) {
152 found = true;
153 break;
154 }
155 }
156 } else {
157 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
158 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
159 mod_hdr_hlist, hash_key) {
160 if (!cmp_mod_hdr_info(&mh->key, &key)) {
161 found = true;
162 break;
163 }
164 }
165 }
166
167 if (found)
168 goto attach_flow;
169
170 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
171 if (!mh)
172 return -ENOMEM;
173
174 mh->key.actions = (void *)mh + sizeof(*mh);
175 memcpy(mh->key.actions, key.actions, actions_size);
176 mh->key.num_actions = num_actions;
177 INIT_LIST_HEAD(&mh->flows);
178
179 err = mlx5_modify_header_alloc(priv->mdev, namespace,
180 mh->key.num_actions,
181 mh->key.actions,
182 &mh->mod_hdr_id);
183 if (err)
184 goto out_err;
185
186 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
187 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
188 else
189 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
190
191attach_flow:
192 list_add(&flow->mod_hdr, &mh->flows);
193 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
194 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
195 else
196 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
197
198 return 0;
199
200out_err:
201 kfree(mh);
202 return err;
203}
204
205static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
206 struct mlx5e_tc_flow *flow)
207{
208 struct list_head *next = flow->mod_hdr.next;
209
210 list_del(&flow->mod_hdr);
211
212 if (list_empty(next)) {
213 struct mlx5e_mod_hdr_entry *mh;
214
215 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
216
217 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
218 hash_del(&mh->mod_hdr_hlist);
219 kfree(mh);
220 }
221}
222
74491de9
MB		 223static struct mlx5_flow_handle *
224mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 225 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 226 struct mlx5e_tc_flow *flow)
e8f887ac 227{
aa0cbbae 228 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 229 struct mlx5_core_dev *dev = priv->mdev;
aa0cbbae 230 struct mlx5_flow_destination dest = {};
66958ed9 231 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 232 .action = attr->action,
233 .flow_tag = attr->flow_tag,
66958ed9
HHZ		 234 .encap_id = 0,
235 };
aad7e08d 236 struct mlx5_fc *counter = NULL;
74491de9 237 struct mlx5_flow_handle *rule;
e8f887ac 238 bool table_created = false;
2f4fe4ca 239 int err;
e8f887ac 240
3bc4b7bf 241 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
aad7e08d
AV		 242 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
243 dest.ft = priv->fs.vlan.ft.t;
3bc4b7bf 244 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
aad7e08d
AV		 245 counter = mlx5_fc_create(dev, true);
246 if (IS_ERR(counter))
247 return ERR_CAST(counter);
248
249 dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
250 dest.counter = counter;
251 }
252
2f4fe4ca
OG		 253 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
254 err = mlx5_modify_header_alloc(dev, MLX5_FLOW_NAMESPACE_KERNEL,
255 parse_attr->num_mod_hdr_actions,
256 parse_attr->mod_hdr_actions,
257 &attr->mod_hdr_id);
d7e75a32 258 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG		 259 kfree(parse_attr->mod_hdr_actions);
260 if (err) {
261 rule = ERR_PTR(err);
262 goto err_create_mod_hdr_id;
263 }
264 }
265
acff797c
MG		 266 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
267 priv->fs.tc.t =
268 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
269 MLX5E_TC_PRIO,
270 MLX5E_TC_TABLE_NUM_ENTRIES,
271 MLX5E_TC_TABLE_NUM_GROUPS,
c9f1b073 272 0, 0);
acff797c 273 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV		 274 netdev_err(priv->netdev,
275 "Failed to create tc offload table\n");
aad7e08d
AV		 276 rule = ERR_CAST(priv->fs.tc.t);
277 goto err_create_ft;
e8f887ac
AV		 278 }
279
280 table_created = true;
281 }
282
17091853
OG		 283 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
284 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
285 &flow_act, &dest, 1);
aad7e08d
AV		 286
287 if (IS_ERR(rule))
288 goto err_add_rule;
289
290 return rule;
e8f887ac 291
aad7e08d
AV		 292err_add_rule:
293 if (table_created) {
acff797c
MG		 294 mlx5_destroy_flow_table(priv->fs.tc.t);
295 priv->fs.tc.t = NULL;
e8f887ac 296 }
aad7e08d 297err_create_ft:
2f4fe4ca
OG		 298 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
299 mlx5_modify_header_dealloc(priv->mdev,
300 attr->mod_hdr_id);
301err_create_mod_hdr_id:
aad7e08d 302 mlx5_fc_destroy(dev, counter);
e8f887ac
AV		 303
304 return rule;
305}
306
d85cdccb
OG		 307static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
308 struct mlx5e_tc_flow *flow)
309{
513f8f7f 310 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 311 struct mlx5_fc *counter = NULL;
312
aa0cbbae
OG		 313 counter = mlx5_flow_rule_counter(flow->rule);
314 mlx5_del_flow_rules(flow->rule);
315 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb
OG		 316
317 if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
318 mlx5_destroy_flow_table(priv->fs.tc.t);
319 priv->fs.tc.t = NULL;
320 }
2f4fe4ca 321
513f8f7f 322 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2f4fe4ca 323 mlx5_modify_header_dealloc(priv->mdev,
513f8f7f 324 attr->mod_hdr_id);
d85cdccb
OG		 325}
326
aa0cbbae
OG		 327static void mlx5e_detach_encap(struct mlx5e_priv *priv,
328 struct mlx5e_tc_flow *flow);
329
74491de9
MB		 330static struct mlx5_flow_handle *
331mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 332 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 333 struct mlx5e_tc_flow *flow)
adb4c123
OG		 334{
335 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae
OG		 336 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
337 struct mlx5_flow_handle *rule;
8b32580d
OG		 338 int err;
339
340 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG		 341 if (err) {
342 rule = ERR_PTR(err);
343 goto err_add_vlan;
344 }
adb4c123 345
d7e75a32
OG		 346 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
347 err = mlx5_modify_header_alloc(priv->mdev, MLX5_FLOW_NAMESPACE_FDB,
348 parse_attr->num_mod_hdr_actions,
349 parse_attr->mod_hdr_actions,
350 &attr->mod_hdr_id);
351 kfree(parse_attr->mod_hdr_actions);
352 if (err) {
353 rule = ERR_PTR(err);
354 goto err_mod_hdr;
355 }
356 }
357
aa0cbbae
OG		 358 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
359 if (IS_ERR(rule))
360 goto err_add_rule;
adb4c123 361
aa0cbbae
OG		 362 return rule;
363
364err_add_rule:
513f8f7f 365 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
d7e75a32
OG		 366 mlx5_modify_header_dealloc(priv->mdev,
367 attr->mod_hdr_id);
368err_mod_hdr:
aa0cbbae
OG		 369 mlx5_eswitch_del_vlan_action(esw, attr);
370err_add_vlan:
371 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
372 mlx5e_detach_encap(priv, flow);
aa0cbbae
OG		 373 return rule;
374}
d85cdccb
OG		 375
376static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
377 struct mlx5e_tc_flow *flow)
378{
379 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 380 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 381
232c0013
HHZ		 382 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
383 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
513f8f7f 384 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, attr);
232c0013 385 }
d85cdccb 386
513f8f7f 387 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 388
513f8f7f 389 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
d85cdccb 390 mlx5e_detach_encap(priv, flow);
513f8f7f 391 kvfree(attr->parse_attr);
232c0013 392 }
d7e75a32 393
513f8f7f 394 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
d7e75a32
OG		 395 mlx5_modify_header_dealloc(priv->mdev,
396 attr->mod_hdr_id);
d85cdccb
OG		 397}
398
232c0013
HHZ		 399void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
400 struct mlx5e_encap_entry *e)
401{
402 struct mlx5e_tc_flow *flow;
403 int err;
404
405 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
406 e->encap_size, e->encap_header,
407 &e->encap_id);
408 if (err) {
409 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
410 err);
411 return;
412 }
413 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 414 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 415
416 list_for_each_entry(flow, &e->flows, encap) {
417 flow->esw_attr->encap_id = e->encap_id;
418 flow->rule = mlx5e_tc_add_fdb_flow(priv,
419 flow->esw_attr->parse_attr,
420 flow);
421 if (IS_ERR(flow->rule)) {
422 err = PTR_ERR(flow->rule);
423 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
424 err);
425 continue;
426 }
427 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
428 }
429}
430
431void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
432 struct mlx5e_encap_entry *e)
433{
434 struct mlx5e_tc_flow *flow;
435 struct mlx5_fc *counter;
436
437 list_for_each_entry(flow, &e->flows, encap) {
438 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
439 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
440 counter = mlx5_flow_rule_counter(flow->rule);
441 mlx5_del_flow_rules(flow->rule);
442 mlx5_fc_destroy(priv->mdev, counter);
443 }
444 }
445
446 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
447 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
448 mlx5_encap_dealloc(priv->mdev, e->encap_id);
449 }
450}
451
f6dfb4c3
HHZ		 452void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
453{
454 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
455 u64 bytes, packets, lastuse = 0;
456 struct mlx5e_tc_flow *flow;
457 struct mlx5e_encap_entry *e;
458 struct mlx5_fc *counter;
459 struct neigh_table *tbl;
460 bool neigh_used = false;
461 struct neighbour *n;
462
463 if (m_neigh->family == AF_INET)
464 tbl = &arp_tbl;
465#if IS_ENABLED(CONFIG_IPV6)
466 else if (m_neigh->family == AF_INET6)
467 tbl = ipv6_stub->nd_tbl;
468#endif
469 else
470 return;
471
472 list_for_each_entry(e, &nhe->encap_list, encap_list) {
473 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
474 continue;
475 list_for_each_entry(flow, &e->flows, encap) {
476 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
477 counter = mlx5_flow_rule_counter(flow->rule);
478 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
479 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
480 neigh_used = true;
481 break;
482 }
483 }
484 }
485 }
486
487 if (neigh_used) {
488 nhe->reported_lastuse = jiffies;
489
490 /* find the relevant neigh according to the cached device and
491 * dst ip pair
492 */
493 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
494 if (!n) {
495 WARN(1, "The neighbour already freed\n");
496 return;
497 }
498
499 neigh_event_send(n, NULL);
500 neigh_release(n);
501 }
502}
503
d85cdccb
OG		 504static void mlx5e_detach_encap(struct mlx5e_priv *priv,
505 struct mlx5e_tc_flow *flow)
506{
5067b602
RD		 507 struct list_head *next = flow->encap.next;
508
509 list_del(&flow->encap);
510 if (list_empty(next)) {
c1ae1152 511 struct mlx5e_encap_entry *e;
5067b602 512
c1ae1152 513 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 514 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
515
516 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
5067b602 517 mlx5_encap_dealloc(priv->mdev, e->encap_id);
232c0013 518
cdc5a7f3 519 hash_del_rcu(&e->encap_hlist);
232c0013 520 kfree(e->encap_header);
5067b602
RD		 521 kfree(e);
522 }
523}
524
e8f887ac 525static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 526 struct mlx5e_tc_flow *flow)
e8f887ac 527{
d85cdccb
OG		 528 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
529 mlx5e_tc_del_fdb_flow(priv, flow);
530 else
531 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 532}
533
bbd00f7e
HHZ		 534static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
535 struct tc_cls_flower_offload *f)
536{
537 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
538 outer_headers);
539 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
540 outer_headers);
541 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
542 misc_parameters);
543 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
544 misc_parameters);
545
546 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
547 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
548
549 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
550 struct flow_dissector_key_keyid *key =
551 skb_flow_dissector_target(f->dissector,
552 FLOW_DISSECTOR_KEY_ENC_KEYID,
553 f->key);
554 struct flow_dissector_key_keyid *mask =
555 skb_flow_dissector_target(f->dissector,
556 FLOW_DISSECTOR_KEY_ENC_KEYID,
557 f->mask);
558 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
559 be32_to_cpu(mask->keyid));
560 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
561 be32_to_cpu(key->keyid));
562 }
563}
564
565static int parse_tunnel_attr(struct mlx5e_priv *priv,
566 struct mlx5_flow_spec *spec,
567 struct tc_cls_flower_offload *f)
568{
569 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
570 outer_headers);
571 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
572 outer_headers);
573
2e72eb43
OG		 574 struct flow_dissector_key_control *enc_control =
575 skb_flow_dissector_target(f->dissector,
576 FLOW_DISSECTOR_KEY_ENC_CONTROL,
577 f->key);
578
bbd00f7e
HHZ		 579 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
580 struct flow_dissector_key_ports *key =
581 skb_flow_dissector_target(f->dissector,
582 FLOW_DISSECTOR_KEY_ENC_PORTS,
583 f->key);
584 struct flow_dissector_key_ports *mask =
585 skb_flow_dissector_target(f->dissector,
586 FLOW_DISSECTOR_KEY_ENC_PORTS,
587 f->mask);
1ad9a00a
PB		 588 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
589 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
590 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ		 591
592 /* Full udp dst port must be given */
593 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 594 goto vxlan_match_offload_err;
bbd00f7e 595
1ad9a00a 596 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 597 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
598 parse_vxlan_attr(spec, f);
2fcd82e9
OG		 599 else {
600 netdev_warn(priv->netdev,
601 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 602 return -EOPNOTSUPP;
2fcd82e9 603 }
bbd00f7e
HHZ		 604
605 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
606 udp_dport, ntohs(mask->dst));
607 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
608 udp_dport, ntohs(key->dst));
609
cd377663
OG		 610 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
611 udp_sport, ntohs(mask->src));
612 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
613 udp_sport, ntohs(key->src));
bbd00f7e 614 } else { /* udp dst port must be given */
2fcd82e9
OG		 615vxlan_match_offload_err:
616 netdev_warn(priv->netdev,
617 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
618 return -EOPNOTSUPP;
bbd00f7e
HHZ		 619 }
620
2e72eb43 621 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 622 struct flow_dissector_key_ipv4_addrs *key =
623 skb_flow_dissector_target(f->dissector,
624 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
625 f->key);
626 struct flow_dissector_key_ipv4_addrs *mask =
627 skb_flow_dissector_target(f->dissector,
628 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
629 f->mask);
630 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
631 src_ipv4_src_ipv6.ipv4_layout.ipv4,
632 ntohl(mask->src));
633 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
634 src_ipv4_src_ipv6.ipv4_layout.ipv4,
635 ntohl(key->src));
636
637 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
638 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
639 ntohl(mask->dst));
640 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
641 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
642 ntohl(key->dst));
bbd00f7e 643
2e72eb43
OG		 644 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
645 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 646 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
647 struct flow_dissector_key_ipv6_addrs *key =
648 skb_flow_dissector_target(f->dissector,
649 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
650 f->key);
651 struct flow_dissector_key_ipv6_addrs *mask =
652 skb_flow_dissector_target(f->dissector,
653 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
654 f->mask);
655
656 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
657 src_ipv4_src_ipv6.ipv6_layout.ipv6),
658 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
659 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
660 src_ipv4_src_ipv6.ipv6_layout.ipv6),
661 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
662
663 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
664 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
665 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
666 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
667 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
668 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
669
670 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 672 }
bbd00f7e
HHZ		 673
674 /* Enforce DMAC when offloading incoming tunneled flows.
675 * Flow counters require a match on the DMAC.
676 */
677 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
678 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
679 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
680 dmac_47_16), priv->netdev->dev_addr);
681
682 /* let software handle IP fragments */
683 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
684 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
685
686 return 0;
687}
688
de0af0bf
RD		 689static int __parse_cls_flower(struct mlx5e_priv *priv,
690 struct mlx5_flow_spec *spec,
691 struct tc_cls_flower_offload *f,
692 u8 *min_inline)
e3a2b7ed 693{
c5bb1730
MG		 694 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
695 outer_headers);
696 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
697 outer_headers);
e3a2b7ed
AV		 698 u16 addr_type = 0;
699 u8 ip_proto = 0;
700
de0af0bf
RD		 701 *min_inline = MLX5_INLINE_MODE_L2;
702
e3a2b7ed
AV		 703 if (f->dissector->used_keys &
704 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
705 BIT(FLOW_DISSECTOR_KEY_BASIC) |
706 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 707 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV		 708 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
709 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 710 BIT(FLOW_DISSECTOR_KEY_PORTS) |
711 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
712 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
713 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
714 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 715 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b
OG		 716 BIT(FLOW_DISSECTOR_KEY_TCP) |
717 BIT(FLOW_DISSECTOR_KEY_IP))) {
e3a2b7ed
AV		 718 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
719 f->dissector->used_keys);
720 return -EOPNOTSUPP;
721 }
722
bbd00f7e
HHZ		 723 if ((dissector_uses_key(f->dissector,
724 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
725 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
726 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
727 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
728 struct flow_dissector_key_control *key =
729 skb_flow_dissector_target(f->dissector,
730 FLOW_DISSECTOR_KEY_ENC_CONTROL,
731 f->key);
732 switch (key->addr_type) {
733 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 734 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 735 if (parse_tunnel_attr(priv, spec, f))
736 return -EOPNOTSUPP;
737 break;
738 default:
739 return -EOPNOTSUPP;
740 }
741
742 /* In decap flow, header pointers should point to the inner
743 * headers, outer header were already set by parse_tunnel_attr
744 */
745 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
746 inner_headers);
747 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
748 inner_headers);
749 }
750
e3a2b7ed
AV		 751 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
752 struct flow_dissector_key_control *key =
753 skb_flow_dissector_target(f->dissector,
1dbd0d37 754 FLOW_DISSECTOR_KEY_CONTROL,
e3a2b7ed 755 f->key);
3f7d0eb4
OG		 756
757 struct flow_dissector_key_control *mask =
758 skb_flow_dissector_target(f->dissector,
759 FLOW_DISSECTOR_KEY_CONTROL,
760 f->mask);
e3a2b7ed 761 addr_type = key->addr_type;
3f7d0eb4
OG		 762
763 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
764 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
765 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
766 key->flags & FLOW_DIS_IS_FRAGMENT);
0827444d
OG		 767
768 /* the HW doesn't need L3 inline to match on frag=no */
769 if (key->flags & FLOW_DIS_IS_FRAGMENT)
770 *min_inline = MLX5_INLINE_MODE_IP;
3f7d0eb4 771 }
e3a2b7ed
AV		 772 }
773
774 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
775 struct flow_dissector_key_basic *key =
776 skb_flow_dissector_target(f->dissector,
777 FLOW_DISSECTOR_KEY_BASIC,
778 f->key);
779 struct flow_dissector_key_basic *mask =
780 skb_flow_dissector_target(f->dissector,
781 FLOW_DISSECTOR_KEY_BASIC,
782 f->mask);
783 ip_proto = key->ip_proto;
784
785 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
786 ntohs(mask->n_proto));
787 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
788 ntohs(key->n_proto));
789
790 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
791 mask->ip_proto);
792 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
793 key->ip_proto);
de0af0bf
RD		 794
795 if (mask->ip_proto)
796 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 797 }
798
799 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
800 struct flow_dissector_key_eth_addrs *key =
801 skb_flow_dissector_target(f->dissector,
802 FLOW_DISSECTOR_KEY_ETH_ADDRS,
803 f->key);
804 struct flow_dissector_key_eth_addrs *mask =
805 skb_flow_dissector_target(f->dissector,
806 FLOW_DISSECTOR_KEY_ETH_ADDRS,
807 f->mask);
808
809 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
810 dmac_47_16),
811 mask->dst);
812 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
813 dmac_47_16),
814 key->dst);
815
816 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
817 smac_47_16),
818 mask->src);
819 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
820 smac_47_16),
821 key->src);
822 }
823
095b6cfd
OG		 824 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
825 struct flow_dissector_key_vlan *key =
826 skb_flow_dissector_target(f->dissector,
827 FLOW_DISSECTOR_KEY_VLAN,
828 f->key);
829 struct flow_dissector_key_vlan *mask =
830 skb_flow_dissector_target(f->dissector,
831 FLOW_DISSECTOR_KEY_VLAN,
832 f->mask);
358d79a4 833 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY		 834 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
835 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG		 836
837 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
838 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 839
840 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
841 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
095b6cfd
OG		 842 }
843 }
844
e3a2b7ed
AV		 845 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
846 struct flow_dissector_key_ipv4_addrs *key =
847 skb_flow_dissector_target(f->dissector,
848 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
849 f->key);
850 struct flow_dissector_key_ipv4_addrs *mask =
851 skb_flow_dissector_target(f->dissector,
852 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
853 f->mask);
854
855 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
856 src_ipv4_src_ipv6.ipv4_layout.ipv4),
857 &mask->src, sizeof(mask->src));
858 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
859 src_ipv4_src_ipv6.ipv4_layout.ipv4),
860 &key->src, sizeof(key->src));
861 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
862 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
863 &mask->dst, sizeof(mask->dst));
864 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
865 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
866 &key->dst, sizeof(key->dst));
de0af0bf
RD		 867
868 if (mask->src || mask->dst)
869 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 870 }
871
872 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
873 struct flow_dissector_key_ipv6_addrs *key =
874 skb_flow_dissector_target(f->dissector,
875 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
876 f->key);
877 struct flow_dissector_key_ipv6_addrs *mask =
878 skb_flow_dissector_target(f->dissector,
879 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
880 f->mask);
881
882 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
883 src_ipv4_src_ipv6.ipv6_layout.ipv6),
884 &mask->src, sizeof(mask->src));
885 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
886 src_ipv4_src_ipv6.ipv6_layout.ipv6),
887 &key->src, sizeof(key->src));
888
889 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
890 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
891 &mask->dst, sizeof(mask->dst));
892 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
893 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
894 &key->dst, sizeof(key->dst));
de0af0bf
RD		 895
896 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
897 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
898 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 899 }
900
901 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
902 struct flow_dissector_key_ports *key =
903 skb_flow_dissector_target(f->dissector,
904 FLOW_DISSECTOR_KEY_PORTS,
905 f->key);
906 struct flow_dissector_key_ports *mask =
907 skb_flow_dissector_target(f->dissector,
908 FLOW_DISSECTOR_KEY_PORTS,
909 f->mask);
910 switch (ip_proto) {
911 case IPPROTO_TCP:
912 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
913 tcp_sport, ntohs(mask->src));
914 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
915 tcp_sport, ntohs(key->src));
916
917 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
918 tcp_dport, ntohs(mask->dst));
919 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
920 tcp_dport, ntohs(key->dst));
921 break;
922
923 case IPPROTO_UDP:
924 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
925 udp_sport, ntohs(mask->src));
926 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
927 udp_sport, ntohs(key->src));
928
929 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
930 udp_dport, ntohs(mask->dst));
931 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
932 udp_dport, ntohs(key->dst));
933 break;
934 default:
935 netdev_err(priv->netdev,
936 "Only UDP and TCP transport are supported\n");
937 return -EINVAL;
938 }
de0af0bf
RD		 939
940 if (mask->src || mask->dst)
941 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
e3a2b7ed
AV		 942 }
943
fd7da28b
OG		 944 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
945 struct flow_dissector_key_ip *key =
946 skb_flow_dissector_target(f->dissector,
947 FLOW_DISSECTOR_KEY_IP,
948 f->key);
949 struct flow_dissector_key_ip *mask =
950 skb_flow_dissector_target(f->dissector,
951 FLOW_DISSECTOR_KEY_IP,
952 f->mask);
953
954 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
955 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
956
957 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
958 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
959
960 if (mask->tos)
961 *min_inline = MLX5_INLINE_MODE_IP;
962
963 if (mask->ttl) /* currently not supported */
964 return -EOPNOTSUPP;
965 }
966
e77834ec
OG		 967 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
968 struct flow_dissector_key_tcp *key =
969 skb_flow_dissector_target(f->dissector,
970 FLOW_DISSECTOR_KEY_TCP,
971 f->key);
972 struct flow_dissector_key_tcp *mask =
973 skb_flow_dissector_target(f->dissector,
974 FLOW_DISSECTOR_KEY_TCP,
975 f->mask);
976
977 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
978 ntohs(mask->flags));
979 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
980 ntohs(key->flags));
981
982 if (mask->flags)
983 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
984 }
985
e3a2b7ed
AV		 986 return 0;
987}
988
de0af0bf 989static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 990 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 991 struct mlx5_flow_spec *spec,
992 struct tc_cls_flower_offload *f)
993{
994 struct mlx5_core_dev *dev = priv->mdev;
995 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 996 struct mlx5e_rep_priv *rpriv = priv->ppriv;
997 struct mlx5_eswitch_rep *rep;
de0af0bf
RD		 998 u8 min_inline;
999 int err;
1000
1001 err = __parse_cls_flower(priv, spec, f, &min_inline);
1002
1d447a39
SM		 1003 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1004 rep = rpriv->rep;
1005 if (rep->vport != FDB_UPLINK_VPORT &&
1006 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
1007 esw->offloads.inline_mode < min_inline)) {
de0af0bf
RD		 1008 netdev_warn(priv->netdev,
1009 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
1010 min_inline, esw->offloads.inline_mode);
1011 return -EOPNOTSUPP;
1012 }
1013 }
1014
1015 return err;
1016}
1017
d79b6df6
OG		 1018struct pedit_headers {
1019 struct ethhdr eth;
1020 struct iphdr ip4;
1021 struct ipv6hdr ip6;
1022 struct tcphdr tcp;
1023 struct udphdr udp;
1024};
1025
1026static int pedit_header_offsets[] = {
1027 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1028 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1029 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1030 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1031 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1032};
1033
1034#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1035
1036static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1037 struct pedit_headers *masks,
1038 struct pedit_headers *vals)
1039{
1040 u32 *curr_pmask, *curr_pval;
1041
1042 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1043 goto out_err;
1044
1045 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1046 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1047
1048 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1049 goto out_err;
1050
1051 *curr_pmask |= mask;
1052 *curr_pval |= (val & mask);
1053
1054 return 0;
1055
1056out_err:
1057 return -EOPNOTSUPP;
1058}
1059
1060struct mlx5_fields {
1061 u8 field;
1062 u8 size;
1063 u32 offset;
1064};
1065
1066static struct mlx5_fields fields[] = {
1067 {MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_dest[0])},
1068 {MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_dest[4])},
1069 {MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_source[0])},
1070 {MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_source[4])},
1071 {MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE, 2, offsetof(struct pedit_headers, eth.h_proto)},
1072
1073 {MLX5_ACTION_IN_FIELD_OUT_IP_DSCP, 1, offsetof(struct pedit_headers, ip4.tos)},
1074 {MLX5_ACTION_IN_FIELD_OUT_IP_TTL, 1, offsetof(struct pedit_headers, ip4.ttl)},
1075 {MLX5_ACTION_IN_FIELD_OUT_SIPV4, 4, offsetof(struct pedit_headers, ip4.saddr)},
1076 {MLX5_ACTION_IN_FIELD_OUT_DIPV4, 4, offsetof(struct pedit_headers, ip4.daddr)},
1077
1078 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[0])},
1079 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[1])},
1080 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[2])},
1081 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[3])},
1082 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[0])},
1083 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[1])},
1084 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[2])},
1085 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[3])},
1086
1087 {MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT, 2, offsetof(struct pedit_headers, tcp.source)},
1088 {MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT, 2, offsetof(struct pedit_headers, tcp.dest)},
1089 {MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS, 1, offsetof(struct pedit_headers, tcp.ack_seq) + 5},
1090
1091 {MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT, 2, offsetof(struct pedit_headers, udp.source)},
1092 {MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT, 2, offsetof(struct pedit_headers, udp.dest)},
1093};
1094
1095/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1096 * max from the SW pedit action. On success, it says how many HW actions were
1097 * actually parsed.
1098 */
1099static int offload_pedit_fields(struct pedit_headers *masks,
1100 struct pedit_headers *vals,
1101 struct mlx5e_tc_flow_parse_attr *parse_attr)
1102{
1103 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
d824bf3f 1104 int i, action_size, nactions, max_actions, first, last, first_z;
d79b6df6 1105 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1106 struct mlx5_fields *f;
1107 u8 cmd, field_bsize;
e3ca4e05 1108 u32 s_mask, a_mask;
d79b6df6
OG		 1109 unsigned long mask;
1110 void *action;
1111
1112 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1113 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1114 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1115 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1116
1117 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1118 action = parse_attr->mod_hdr_actions;
1119 max_actions = parse_attr->num_mod_hdr_actions;
1120 nactions = 0;
1121
1122 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1123 f = &fields[i];
1124 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1125 s_mask = 0;
1126 a_mask = 0;
d79b6df6
OG		 1127
1128 s_masks_p = (void *)set_masks + f->offset;
1129 a_masks_p = (void *)add_masks + f->offset;
1130
1131 memcpy(&s_mask, s_masks_p, f->size);
1132 memcpy(&a_mask, a_masks_p, f->size);
1133
1134 if (!s_mask && !a_mask) /* nothing to offload here */
1135 continue;
1136
1137 if (s_mask && a_mask) {
1138 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1139 return -EOPNOTSUPP;
1140 }
1141
1142 if (nactions == max_actions) {
1143 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1144 return -EOPNOTSUPP;
1145 }
1146
1147 if (s_mask) {
1148 cmd = MLX5_ACTION_TYPE_SET;
1149 mask = s_mask;
1150 vals_p = (void *)set_vals + f->offset;
1151 /* clear to denote we consumed this field */
1152 memset(s_masks_p, 0, f->size);
1153 } else {
1154 cmd = MLX5_ACTION_TYPE_ADD;
1155 mask = a_mask;
1156 vals_p = (void *)add_vals + f->offset;
1157 /* clear to denote we consumed this field */
1158 memset(a_masks_p, 0, f->size);
1159 }
1160
d79b6df6 1161 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1162
d824bf3f 1163 first_z = find_first_zero_bit(&mask, field_bsize);
d79b6df6
OG		 1164 first = find_first_bit(&mask, field_bsize);
1165 last = find_last_bit(&mask, field_bsize);
d824bf3f 1166 if (first > 0 || last != (field_bsize - 1) || first_z < last) {
d79b6df6
OG		 1167 printk(KERN_WARNING "mlx5: partial rewrite (mask %lx) is currently not offloaded\n",
1168 mask);
1169 return -EOPNOTSUPP;
1170 }
1171
1172 MLX5_SET(set_action_in, action, action_type, cmd);
1173 MLX5_SET(set_action_in, action, field, f->field);
1174
1175 if (cmd == MLX5_ACTION_TYPE_SET) {
1176 MLX5_SET(set_action_in, action, offset, 0);
1177 /* length is num of bits to be written, zero means length of 32 */
1178 MLX5_SET(set_action_in, action, length, field_bsize);
1179 }
1180
1181 if (field_bsize == 32)
e3ca4e05 1182 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p));
d79b6df6 1183 else if (field_bsize == 16)
e3ca4e05 1184 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p));
d79b6df6 1185 else if (field_bsize == 8)
e3ca4e05 1186 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p);
d79b6df6
OG		 1187
1188 action += action_size;
1189 nactions++;
1190 }
1191
1192 parse_attr->num_mod_hdr_actions = nactions;
1193 return 0;
1194}
1195
1196static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1197 const struct tc_action *a, int namespace,
1198 struct mlx5e_tc_flow_parse_attr *parse_attr)
1199{
1200 int nkeys, action_size, max_actions;
1201
1202 nkeys = tcf_pedit_nkeys(a);
1203 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1204
1205 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1206 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1207 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1208 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1209
1210 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1211 max_actions = min(max_actions, nkeys * 16);
1212
1213 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1214 if (!parse_attr->mod_hdr_actions)
1215 return -ENOMEM;
1216
1217 parse_attr->num_mod_hdr_actions = max_actions;
1218 return 0;
1219}
1220
1221static const struct pedit_headers zero_masks = {};
1222
1223static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1224 const struct tc_action *a, int namespace,
1225 struct mlx5e_tc_flow_parse_attr *parse_attr)
1226{
1227 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1228 int nkeys, i, err = -EOPNOTSUPP;
1229 u32 mask, val, offset;
1230 u8 cmd, htype;
1231
1232 nkeys = tcf_pedit_nkeys(a);
1233
1234 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1235 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1236
1237 for (i = 0; i < nkeys; i++) {
1238 htype = tcf_pedit_htype(a, i);
1239 cmd = tcf_pedit_cmd(a, i);
1240 err = -EOPNOTSUPP; /* can't be all optimistic */
1241
1242 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
1243 printk(KERN_WARNING "mlx5: legacy pedit isn't offloaded\n");
1244 goto out_err;
1245 }
1246
1247 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
1248 printk(KERN_WARNING "mlx5: pedit cmd %d isn't offloaded\n", cmd);
1249 goto out_err;
1250 }
1251
1252 mask = tcf_pedit_mask(a, i);
1253 val = tcf_pedit_val(a, i);
1254 offset = tcf_pedit_offset(a, i);
1255
1256 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1257 if (err)
1258 goto out_err;
1259 }
1260
1261 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1262 if (err)
1263 goto out_err;
1264
1265 err = offload_pedit_fields(masks, vals, parse_attr);
1266 if (err < 0)
1267 goto out_dealloc_parsed_actions;
1268
1269 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1270 cmd_masks = &masks[cmd];
1271 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
1272 printk(KERN_WARNING "mlx5: attempt to offload an unsupported field (cmd %d)\n",
1273 cmd);
1274 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1275 16, 1, cmd_masks, sizeof(zero_masks), true);
1276 err = -EOPNOTSUPP;
1277 goto out_dealloc_parsed_actions;
1278 }
1279 }
1280
1281 return 0;
1282
1283out_dealloc_parsed_actions:
1284 kfree(parse_attr->mod_hdr_actions);
1285out_err:
1286 return err;
1287}
1288
26c02749
OG		 1289static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1290{
1291 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1292 TCA_CSUM_UPDATE_FLAG_UDP;
1293
1294 /* The HW recalcs checksums only if re-writing headers */
1295 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1296 netdev_warn(priv->netdev,
1297 "TC csum action is only offloaded with pedit\n");
1298 return false;
1299 }
1300
1301 if (update_flags & ~prot_flags) {
1302 netdev_warn(priv->netdev,
1303 "can't offload TC csum action for some header/s - flags %#x\n",
1304 update_flags);
1305 return false;
1306 }
1307
1308 return true;
1309}
1310
5c40348c 1311static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG		 1312 struct mlx5e_tc_flow_parse_attr *parse_attr,
1313 struct mlx5e_tc_flow *flow)
e3a2b7ed 1314{
aa0cbbae 1315 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1316 const struct tc_action *a;
22dc13c8 1317 LIST_HEAD(actions);
2f4fe4ca 1318 int err;
e3a2b7ed
AV		 1319
1320 if (tc_no_actions(exts))
1321 return -EINVAL;
1322
3bc4b7bf
OG		 1323 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1324 attr->action = 0;
e3a2b7ed 1325
22dc13c8
WC		 1326 tcf_exts_to_list(exts, &actions);
1327 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1328 if (is_tcf_gact_shot(a)) {
3bc4b7bf 1329 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 1330 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1331 flow_table_properties_nic_receive.flow_counter))
3bc4b7bf 1332 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 1333 continue;
1334 }
1335
2f4fe4ca
OG		 1336 if (is_tcf_pedit(a)) {
1337 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1338 parse_attr);
1339 if (err)
1340 return err;
1341
1342 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1343 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1344 continue;
1345 }
1346
26c02749
OG		 1347 if (is_tcf_csum(a)) {
1348 if (csum_offload_supported(priv, attr->action,
1349 tcf_csum_update_flags(a)))
1350 continue;
1351
1352 return -EOPNOTSUPP;
1353 }
1354
e3a2b7ed
AV		 1355 if (is_tcf_skbedit_mark(a)) {
1356 u32 mark = tcf_skbedit_mark(a);
1357
1358 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
1359 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
1360 mark);
1361 return -EINVAL;
1362 }
1363
3bc4b7bf
OG		 1364 attr->flow_tag = mark;
1365 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 1366 continue;
1367 }
1368
1369 return -EINVAL;
1370 }
1371
1372 return 0;
1373}
1374
76f7444d
OG		 1375static inline int cmp_encap_info(struct ip_tunnel_key *a,
1376 struct ip_tunnel_key *b)
a54e20b4
HHZ		 1377{
1378 return memcmp(a, b, sizeof(*a));
1379}
1380
76f7444d 1381static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 1382{
76f7444d 1383 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 1384}
1385
1386static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
1387 struct net_device *mirred_dev,
1388 struct net_device **out_dev,
1389 struct flowi4 *fl4,
1390 struct neighbour **out_n,
a54e20b4
HHZ		 1391 int *out_ttl)
1392{
3e621b19 1393 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a54e20b4
HHZ		 1394 struct rtable *rt;
1395 struct neighbour *n = NULL;
a54e20b4
HHZ		 1396
1397#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 1398 int ret;
1399
a54e20b4 1400 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 1401 ret = PTR_ERR_OR_ZERO(rt);
1402 if (ret)
1403 return ret;
a54e20b4
HHZ		 1404#else
1405 return -EOPNOTSUPP;
1406#endif
3e621b19
HHZ		 1407 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1408 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
1409 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1410 else
1411 *out_dev = rt->dst.dev;
a54e20b4 1412
75c33da8 1413 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 1414 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
1415 ip_rt_put(rt);
1416 if (!n)
1417 return -ENOMEM;
1418
1419 *out_n = n;
a54e20b4
HHZ		 1420 return 0;
1421}
1422
ce99f6b9
OG		 1423static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
1424 struct net_device *mirred_dev,
1425 struct net_device **out_dev,
1426 struct flowi6 *fl6,
1427 struct neighbour **out_n,
1428 int *out_ttl)
1429{
1430 struct neighbour *n = NULL;
1431 struct dst_entry *dst;
1432
1433#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
1434 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1435 int ret;
1436
1437 dst = ip6_route_output(dev_net(mirred_dev), NULL, fl6);
321fa4ff
AB		 1438 ret = dst->error;
1439 if (ret) {
ce99f6b9
OG		 1440 dst_release(dst);
1441 return ret;
1442 }
1443
1444 *out_ttl = ip6_dst_hoplimit(dst);
1445
1446 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1447 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
1448 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1449 else
1450 *out_dev = dst->dev;
1451#else
1452 return -EOPNOTSUPP;
1453#endif
1454
1455 n = dst_neigh_lookup(dst, &fl6->daddr);
1456 dst_release(dst);
1457 if (!n)
1458 return -ENOMEM;
1459
1460 *out_n = n;
1461 return 0;
1462}
1463
32f3671f
OG		 1464static void gen_vxlan_header_ipv4(struct net_device *out_dev,
1465 char buf[], int encap_size,
1466 unsigned char h_dest[ETH_ALEN],
1467 int ttl,
1468 __be32 daddr,
1469 __be32 saddr,
1470 __be16 udp_dst_port,
1471 __be32 vx_vni)
a54e20b4 1472{
a54e20b4
HHZ		 1473 struct ethhdr *eth = (struct ethhdr *)buf;
1474 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
1475 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
1476 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1477
1478 memset(buf, 0, encap_size);
1479
1480 ether_addr_copy(eth->h_dest, h_dest);
1481 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1482 eth->h_proto = htons(ETH_P_IP);
1483
1484 ip->daddr = daddr;
1485 ip->saddr = saddr;
1486
1487 ip->ttl = ttl;
1488 ip->protocol = IPPROTO_UDP;
1489 ip->version = 0x4;
1490 ip->ihl = 0x5;
1491
1492 udp->dest = udp_dst_port;
1493 vxh->vx_flags = VXLAN_HF_VNI;
1494 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 1495}
1496
225aabaf
OG		 1497static void gen_vxlan_header_ipv6(struct net_device *out_dev,
1498 char buf[], int encap_size,
1499 unsigned char h_dest[ETH_ALEN],
1500 int ttl,
1501 struct in6_addr *daddr,
1502 struct in6_addr *saddr,
1503 __be16 udp_dst_port,
1504 __be32 vx_vni)
ce99f6b9 1505{
ce99f6b9
OG		 1506 struct ethhdr *eth = (struct ethhdr *)buf;
1507 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
1508 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
1509 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1510
1511 memset(buf, 0, encap_size);
1512
1513 ether_addr_copy(eth->h_dest, h_dest);
1514 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1515 eth->h_proto = htons(ETH_P_IPV6);
1516
1517 ip6_flow_hdr(ip6h, 0, 0);
1518 /* the HW fills up ipv6 payload len */
1519 ip6h->nexthdr = IPPROTO_UDP;
1520 ip6h->hop_limit = ttl;
1521 ip6h->daddr = *daddr;
1522 ip6h->saddr = *saddr;
1523
1524 udp->dest = udp_dst_port;
1525 vxh->vx_flags = VXLAN_HF_VNI;
1526 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 1527}
1528
a54e20b4
HHZ		 1529static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
1530 struct net_device *mirred_dev,
1a8552bd 1531 struct mlx5e_encap_entry *e)
a54e20b4
HHZ		 1532{
1533 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 1534 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 1535 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1536 struct net_device *out_dev;
a42485eb 1537 struct neighbour *n = NULL;
a54e20b4 1538 struct flowi4 fl4 = {};
a54e20b4 1539 char *encap_header;
32f3671f 1540 int ttl, err;
033354d5 1541 u8 nud_state;
32f3671f
OG		 1542
1543 if (max_encap_size < ipv4_encap_size) {
1544 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1545 ipv4_encap_size, max_encap_size);
1546 return -EOPNOTSUPP;
1547 }
a54e20b4 1548
32f3671f 1549 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 1550 if (!encap_header)
1551 return -ENOMEM;
1552
1553 switch (e->tunnel_type) {
1554 case MLX5_HEADER_TYPE_VXLAN:
1555 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 1556 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 1557 break;
1558 default:
1559 err = -EOPNOTSUPP;
1560 goto out;
1561 }
9a941117 1562 fl4.flowi4_tos = tun_key->tos;
76f7444d 1563 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 1564 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 1565
1a8552bd 1566 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 1567 &fl4, &n, &ttl);
a54e20b4
HHZ		 1568 if (err)
1569 goto out;
1570
232c0013
HHZ		 1571 /* used by mlx5e_detach_encap to lookup a neigh hash table
1572 * entry in the neigh hash table when a user deletes a rule
1573 */
1574 e->m_neigh.dev = n->dev;
f6dfb4c3 1575 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 1576 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1577 e->out_dev = out_dev;
1578
1579 /* It's importent to add the neigh to the hash table before checking
1580 * the neigh validity state. So if we'll get a notification, in case the
1581 * neigh changes it's validity state, we would find the relevant neigh
1582 * in the hash.
1583 */
1584 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1585 if (err)
1586 goto out;
1587
033354d5
HHZ		 1588 read_lock_bh(&n->lock);
1589 nud_state = n->nud_state;
1590 ether_addr_copy(e->h_dest, n->ha);
1591 read_unlock_bh(&n->lock);
1592
a54e20b4
HHZ		 1593 switch (e->tunnel_type) {
1594 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1595 gen_vxlan_header_ipv4(out_dev, encap_header,
32f3671f
OG		 1596 ipv4_encap_size, e->h_dest, ttl,
1597 fl4.daddr,
1598 fl4.saddr, tun_key->tp_dst,
1599 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 1600 break;
1601 default:
1602 err = -EOPNOTSUPP;
232c0013
HHZ		 1603 goto destroy_neigh_entry;
1604 }
1605 e->encap_size = ipv4_encap_size;
1606 e->encap_header = encap_header;
1607
1608 if (!(nud_state & NUD_VALID)) {
1609 neigh_event_send(n, NULL);
27902f08
WY		 1610 err = -EAGAIN;
1611 goto out;
a54e20b4
HHZ		 1612 }
1613
1614 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 1615 ipv4_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 1616 if (err)
1617 goto destroy_neigh_entry;
1618
1619 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1620 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 1621 neigh_release(n);
1622 return err;
1623
1624destroy_neigh_entry:
1625 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
a54e20b4
HHZ		 1626out:
1627 kfree(encap_header);
232c0013
HHZ		 1628 if (n)
1629 neigh_release(n);
a54e20b4
HHZ		 1630 return err;
1631}
1632
ce99f6b9
OG		 1633static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
1634 struct net_device *mirred_dev,
1a8552bd 1635 struct mlx5e_encap_entry *e)
ce99f6b9
OG		 1636{
1637 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 1638 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 1639 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1640 struct net_device *out_dev;
ce99f6b9
OG		 1641 struct neighbour *n = NULL;
1642 struct flowi6 fl6 = {};
1643 char *encap_header;
225aabaf 1644 int err, ttl = 0;
033354d5 1645 u8 nud_state;
ce99f6b9 1646
225aabaf
OG		 1647 if (max_encap_size < ipv6_encap_size) {
1648 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1649 ipv6_encap_size, max_encap_size);
1650 return -EOPNOTSUPP;
1651 }
ce99f6b9 1652
225aabaf 1653 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 1654 if (!encap_header)
1655 return -ENOMEM;
1656
1657 switch (e->tunnel_type) {
1658 case MLX5_HEADER_TYPE_VXLAN:
1659 fl6.flowi6_proto = IPPROTO_UDP;
1660 fl6.fl6_dport = tun_key->tp_dst;
1661 break;
1662 default:
1663 err = -EOPNOTSUPP;
1664 goto out;
1665 }
1666
1667 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
1668 fl6.daddr = tun_key->u.ipv6.dst;
1669 fl6.saddr = tun_key->u.ipv6.src;
1670
1a8552bd 1671 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG		 1672 &fl6, &n, &ttl);
1673 if (err)
1674 goto out;
1675
232c0013
HHZ		 1676 /* used by mlx5e_detach_encap to lookup a neigh hash table
1677 * entry in the neigh hash table when a user deletes a rule
1678 */
1679 e->m_neigh.dev = n->dev;
f6dfb4c3 1680 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 1681 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1682 e->out_dev = out_dev;
1683
1684 /* It's importent to add the neigh to the hash table before checking
1685 * the neigh validity state. So if we'll get a notification, in case the
1686 * neigh changes it's validity state, we would find the relevant neigh
1687 * in the hash.
1688 */
1689 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1690 if (err)
1691 goto out;
1692
033354d5
HHZ		 1693 read_lock_bh(&n->lock);
1694 nud_state = n->nud_state;
1695 ether_addr_copy(e->h_dest, n->ha);
1696 read_unlock_bh(&n->lock);
1697
ce99f6b9
OG		 1698 switch (e->tunnel_type) {
1699 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1700 gen_vxlan_header_ipv6(out_dev, encap_header,
225aabaf
OG		 1701 ipv6_encap_size, e->h_dest, ttl,
1702 &fl6.daddr,
1703 &fl6.saddr, tun_key->tp_dst,
1704 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 1705 break;
1706 default:
1707 err = -EOPNOTSUPP;
232c0013
HHZ		 1708 goto destroy_neigh_entry;
1709 }
1710
1711 e->encap_size = ipv6_encap_size;
1712 e->encap_header = encap_header;
1713
1714 if (!(nud_state & NUD_VALID)) {
1715 neigh_event_send(n, NULL);
27902f08
WY		 1716 err = -EAGAIN;
1717 goto out;
ce99f6b9
OG		 1718 }
1719
1720 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 1721 ipv6_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 1722 if (err)
1723 goto destroy_neigh_entry;
1724
1725 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1726 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 1727 neigh_release(n);
1728 return err;
1729
1730destroy_neigh_entry:
1731 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ce99f6b9 1732out:
ce99f6b9 1733 kfree(encap_header);
232c0013
HHZ		 1734 if (n)
1735 neigh_release(n);
ce99f6b9
OG		 1736 return err;
1737}
1738
a54e20b4
HHZ		 1739static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1740 struct ip_tunnel_info *tun_info,
1741 struct net_device *mirred_dev,
45247bf2
OG		 1742 struct net_device **encap_dev,
1743 struct mlx5e_tc_flow *flow)
a54e20b4
HHZ		 1744{
1745 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1ad9a00a 1746 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
a54e20b4 1747 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2
OG		 1748 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
1749 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 1750 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 1751 struct mlx5e_encap_entry *e;
45247bf2 1752 int tunnel_type, err = 0;
a54e20b4
HHZ		 1753 uintptr_t hash_key;
1754 bool found = false;
a54e20b4 1755
2fcd82e9 1756 /* udp dst port must be set */
a54e20b4 1757 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 1758 goto vxlan_encap_offload_err;
a54e20b4 1759
cd377663 1760 /* setting udp src port isn't supported */
2fcd82e9
OG		 1761 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
1762vxlan_encap_offload_err:
1763 netdev_warn(priv->netdev,
1764 "must set udp dst port and not set udp src port\n");
cd377663 1765 return -EOPNOTSUPP;
2fcd82e9 1766 }
cd377663 1767
1ad9a00a 1768 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 1769 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ		 1770 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
1771 } else {
2fcd82e9
OG		 1772 netdev_warn(priv->netdev,
1773 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 1774 return -EOPNOTSUPP;
1775 }
1776
76f7444d 1777 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 1778
1779 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
1780 encap_hlist, hash_key) {
76f7444d 1781 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 1782 found = true;
1783 break;
1784 }
1785 }
1786
45247bf2
OG		 1787 if (found)
1788 goto attach_flow;
a54e20b4
HHZ		 1789
1790 e = kzalloc(sizeof(*e), GFP_KERNEL);
1791 if (!e)
1792 return -ENOMEM;
1793
76f7444d 1794 e->tun_info = *tun_info;
a54e20b4
HHZ		 1795 e->tunnel_type = tunnel_type;
1796 INIT_LIST_HEAD(&e->flows);
1797
ce99f6b9 1798 if (family == AF_INET)
1a8552bd 1799 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 1800 else if (family == AF_INET6)
1a8552bd 1801 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 1802
232c0013 1803 if (err && err != -EAGAIN)
a54e20b4
HHZ		 1804 goto out_err;
1805
a54e20b4
HHZ		 1806 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
1807
45247bf2
OG		 1808attach_flow:
1809 list_add(&flow->encap, &e->flows);
1810 *encap_dev = e->out_dev;
232c0013
HHZ		 1811 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1812 attr->encap_id = e->encap_id;
45247bf2 1813
232c0013 1814 return err;
a54e20b4
HHZ		 1815
1816out_err:
1817 kfree(e);
1818 return err;
1819}
1820
03a9d11e 1821static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 1822 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 1823 struct mlx5e_tc_flow *flow)
03a9d11e 1824{
ecf5bb79 1825 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 1826 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 1827 struct ip_tunnel_info *info = NULL;
03a9d11e 1828 const struct tc_action *a;
22dc13c8 1829 LIST_HEAD(actions);
a54e20b4 1830 bool encap = false;
232c0013 1831 int err = 0;
03a9d11e
OG		 1832
1833 if (tc_no_actions(exts))
1834 return -EINVAL;
1835
776b12b6 1836 memset(attr, 0, sizeof(*attr));
1d447a39 1837 attr->in_rep = rpriv->rep;
03a9d11e 1838
22dc13c8
WC		 1839 tcf_exts_to_list(exts, &actions);
1840 list_for_each_entry(a, &actions, list) {
03a9d11e 1841 if (is_tcf_gact_shot(a)) {
8b32580d
OG		 1842 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
1843 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 1844 continue;
1845 }
1846
d7e75a32
OG		 1847 if (is_tcf_pedit(a)) {
1848 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
1849 parse_attr);
1850 if (err)
1851 return err;
1852
1853 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1854 continue;
1855 }
1856
26c02749
OG		 1857 if (is_tcf_csum(a)) {
1858 if (csum_offload_supported(priv, attr->action,
1859 tcf_csum_update_flags(a)))
1860 continue;
1861
1862 return -EOPNOTSUPP;
1863 }
1864
5724b8b5 1865 if (is_tcf_mirred_egress_redirect(a)) {
03a9d11e 1866 int ifindex = tcf_mirred_ifindex(a);
45247bf2 1867 struct net_device *out_dev, *encap_dev = NULL;
03a9d11e 1868 struct mlx5e_priv *out_priv;
03a9d11e
OG		 1869
1870 out_dev = __dev_get_by_index(dev_net(priv->netdev), ifindex);
1871
a54e20b4
HHZ		 1872 if (switchdev_port_same_parent_id(priv->netdev,
1873 out_dev)) {
1874 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1875 MLX5_FLOW_CONTEXT_ACTION_COUNT;
1876 out_priv = netdev_priv(out_dev);
1d447a39
SM		 1877 rpriv = out_priv->ppriv;
1878 attr->out_rep = rpriv->rep;
a54e20b4
HHZ		 1879 } else if (encap) {
1880 err = mlx5e_attach_encap(priv, info,
45247bf2 1881 out_dev, &encap_dev, flow);
232c0013 1882 if (err && err != -EAGAIN)
a54e20b4 1883 return err;
a54e20b4
HHZ		 1884 attr->action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
1885 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1886 MLX5_FLOW_CONTEXT_ACTION_COUNT;
45247bf2 1887 out_priv = netdev_priv(encap_dev);
1d447a39
SM		 1888 rpriv = out_priv->ppriv;
1889 attr->out_rep = rpriv->rep;
232c0013 1890 attr->parse_attr = parse_attr;
a54e20b4 1891 } else {
03a9d11e
OG		 1892 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
1893 priv->netdev->name, out_dev->name);
1894 return -EINVAL;
1895 }
a54e20b4
HHZ		 1896 continue;
1897 }
03a9d11e 1898
a54e20b4
HHZ		 1899 if (is_tcf_tunnel_set(a)) {
1900 info = tcf_tunnel_info(a);
1901 if (info)
1902 encap = true;
1903 else
1904 return -EOPNOTSUPP;
03a9d11e
OG		 1905 continue;
1906 }
1907
8b32580d 1908 if (is_tcf_vlan(a)) {
09c91ddf 1909 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
8b32580d 1910 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 1911 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
8b32580d
OG		 1912 if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q))
1913 return -EOPNOTSUPP;
1914
1915 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1916 attr->vlan = tcf_vlan_push_vid(a);
09c91ddf
OG		 1917 } else { /* action is TCA_VLAN_ACT_MODIFY */
1918 return -EOPNOTSUPP;
8b32580d
OG		 1919 }
1920 continue;
1921 }
1922
bbd00f7e
HHZ		 1923 if (is_tcf_tunnel_release(a)) {
1924 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
1925 continue;
1926 }
1927
03a9d11e
OG		 1928 return -EINVAL;
1929 }
232c0013 1930 return err;
03a9d11e
OG		 1931}
1932
e3a2b7ed
AV		 1933int mlx5e_configure_flower(struct mlx5e_priv *priv, __be16 protocol,
1934 struct tc_cls_flower_offload *f)
1935{
3bc4b7bf 1936 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 1937 struct mlx5e_tc_flow_parse_attr *parse_attr;
acff797c 1938 struct mlx5e_tc_table *tc = &priv->fs.tc;
3bc4b7bf
OG		 1939 struct mlx5e_tc_flow *flow;
1940 int attr_size, err = 0;
65ba8fb7 1941 u8 flow_flags = 0;
e3a2b7ed 1942
65ba8fb7
OG		 1943 if (esw && esw->mode == SRIOV_OFFLOADS) {
1944 flow_flags = MLX5E_TC_FLOW_ESWITCH;
1945 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf
OG		 1946 } else {
1947 flow_flags = MLX5E_TC_FLOW_NIC;
1948 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 1949 }
e3a2b7ed 1950
65ba8fb7 1951 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 1952 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 1953 if (!parse_attr || !flow) {
e3a2b7ed
AV		 1954 err = -ENOMEM;
1955 goto err_free;
1956 }
1957
1958 flow->cookie = f->cookie;
65ba8fb7 1959 flow->flags = flow_flags;
e3a2b7ed 1960
17091853 1961 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV		 1962 if (err < 0)
1963 goto err_free;
1964
65ba8fb7 1965 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 1966 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123 1967 if (err < 0)
232c0013 1968 goto err_handle_encap_flow;
aa0cbbae 1969 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 1970 } else {
aa0cbbae 1971 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG		 1972 if (err < 0)
1973 goto err_free;
aa0cbbae 1974 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 1975 }
e3a2b7ed 1976
e3a2b7ed
AV		 1977 if (IS_ERR(flow->rule)) {
1978 err = PTR_ERR(flow->rule);
aa0cbbae 1979 goto err_free;
e3a2b7ed
AV		 1980 }
1981
0b67a38f 1982 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
5c40348c
OG		 1983 err = rhashtable_insert_fast(&tc->ht, &flow->node,
1984 tc->ht_params);
1985 if (err)
1986 goto err_del_rule;
1987
232c0013
HHZ		 1988 if (flow->flags & MLX5E_TC_FLOW_ESWITCH &&
1989 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
1990 kvfree(parse_attr);
1991 return err;
e3a2b7ed 1992
5c40348c 1993err_del_rule:
5e86397a 1994 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed 1995
232c0013
HHZ		 1996err_handle_encap_flow:
1997 if (err == -EAGAIN) {
1998 err = rhashtable_insert_fast(&tc->ht, &flow->node,
1999 tc->ht_params);
2000 if (err)
2001 mlx5e_tc_del_flow(priv, flow);
2002 else
2003 return 0;
2004 }
2005
e3a2b7ed 2006err_free:
17091853 2007 kvfree(parse_attr);
232c0013 2008 kfree(flow);
e3a2b7ed
AV		 2009 return err;
2010}
2011
2012int mlx5e_delete_flower(struct mlx5e_priv *priv,
2013 struct tc_cls_flower_offload *f)
2014{
2015 struct mlx5e_tc_flow *flow;
acff797c 2016 struct mlx5e_tc_table *tc = &priv->fs.tc;
e3a2b7ed
AV		 2017
2018 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2019 tc->ht_params);
2020 if (!flow)
2021 return -EINVAL;
2022
2023 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
2024
961e8979 2025 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 2026
2027 kfree(flow);
2028
2029 return 0;
2030}
2031
aad7e08d
AV		 2032int mlx5e_stats_flower(struct mlx5e_priv *priv,
2033 struct tc_cls_flower_offload *f)
2034{
2035 struct mlx5e_tc_table *tc = &priv->fs.tc;
2036 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 2037 struct mlx5_fc *counter;
2038 u64 bytes;
2039 u64 packets;
2040 u64 lastuse;
2041
2042 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2043 tc->ht_params);
2044 if (!flow)
2045 return -EINVAL;
2046
0b67a38f
HHZ		 2047 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2048 return 0;
2049
aad7e08d
AV		 2050 counter = mlx5_flow_rule_counter(flow->rule);
2051 if (!counter)
2052 return 0;
2053
2054 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2055
d897a638 2056 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 2057
aad7e08d
AV		 2058 return 0;
2059}
2060
e8f887ac
AV		 2061static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
2062 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2063 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2064 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2065 .automatic_shrinking = true,
2066};
2067
2068int mlx5e_tc_init(struct mlx5e_priv *priv)
2069{
acff797c 2070 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 2071
11c9c548
OG		 2072 hash_init(tc->mod_hdr_tbl);
2073
e8f887ac
AV		 2074 tc->ht_params = mlx5e_tc_flow_ht_params;
2075 return rhashtable_init(&tc->ht, &tc->ht_params);
2076}
2077
2078static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2079{
2080 struct mlx5e_tc_flow *flow = ptr;
2081 struct mlx5e_priv *priv = arg;
2082
961e8979 2083 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 2084 kfree(flow);
2085}
2086
2087void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
2088{
acff797c 2089 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV		 2090
2091 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
2092
acff797c
MG		 2093 if (!IS_ERR_OR_NULL(tc->t)) {
2094 mlx5_destroy_flow_table(tc->t);
2095 tc->t = NULL;
e8f887ac
AV		 2096 }
2097}
Linux 6.x block layer and io_uring tree(s)