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net/mlx5e: Change return type of tc add flow functions
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
358aa5ce 53#include "lib/vxlan.h"
3f6d08d1 54#include "fs_core.h"
2c81bfd5 55#include "en/port.h"
e8f887ac 56
3bc4b7bf
OG		 57struct mlx5_nic_flow_attr {
58 u32 action;
59 u32 flow_tag;
2f4fe4ca 60 u32 mod_hdr_id;
5c65c564 61 u32 hairpin_tirn;
38aa51c1 62 u8 match_level;
3f6d08d1 63 struct mlx5_flow_table *hairpin_ft;
b8aee822 64 struct mlx5_fc *counter;
3bc4b7bf
OG		 65};
66
60bd4af8
OG		 67#define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
68
65ba8fb7 69enum {
60bd4af8
OG		 70 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
71 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
72 MLX5E_TC_FLOW_ESWITCH = BIT(MLX5E_TC_FLOW_BASE),
73 MLX5E_TC_FLOW_NIC = BIT(MLX5E_TC_FLOW_BASE + 1),
74 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE + 2),
75 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 3),
76 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 4),
65ba8fb7
OG		 77};
78
e4ad91f2
CM		 79#define MLX5E_TC_MAX_SPLITS 1
80
e8f887ac
AV		 81struct mlx5e_tc_flow {
82 struct rhash_head node;
655dc3d2 83 struct mlx5e_priv *priv;
e8f887ac 84 u64 cookie;
65ba8fb7 85 u8 flags;
e4ad91f2 86 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
11c9c548
OG		 87 struct list_head encap; /* flows sharing the same encap ID */
88 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 89 struct list_head hairpin; /* flows sharing the same hairpin */
3bc4b7bf
OG		 90 union {
91 struct mlx5_esw_flow_attr esw_attr[0];
92 struct mlx5_nic_flow_attr nic_attr[0];
93 };
e8f887ac
AV		 94};
95
17091853 96struct mlx5e_tc_flow_parse_attr {
3c37745e 97 struct ip_tunnel_info tun_info;
17091853 98 struct mlx5_flow_spec spec;
d79b6df6
OG		 99 int num_mod_hdr_actions;
100 void *mod_hdr_actions;
3c37745e 101 int mirred_ifindex;
17091853
OG		 102};
103
acff797c 104#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 105#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 106
77ab67b7
OG		 107struct mlx5e_hairpin {
108 struct mlx5_hairpin *pair;
109
110 struct mlx5_core_dev *func_mdev;
3f6d08d1 111 struct mlx5e_priv *func_priv;
77ab67b7
OG		 112 u32 tdn;
113 u32 tirn;
3f6d08d1
OG		 114
115 int num_channels;
116 struct mlx5e_rqt indir_rqt;
117 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
118 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 119};
120
5c65c564
OG		 121struct mlx5e_hairpin_entry {
122 /* a node of a hash table which keeps all the hairpin entries */
123 struct hlist_node hairpin_hlist;
124
125 /* flows sharing the same hairpin */
126 struct list_head flows;
127
d8822868 128 u16 peer_vhca_id;
106be53b 129 u8 prio;
5c65c564
OG		 130 struct mlx5e_hairpin *hp;
131};
132
11c9c548
OG		 133struct mod_hdr_key {
134 int num_actions;
135 void *actions;
136};
137
138struct mlx5e_mod_hdr_entry {
139 /* a node of a hash table which keeps all the mod_hdr entries */
140 struct hlist_node mod_hdr_hlist;
141
142 /* flows sharing the same mod_hdr entry */
143 struct list_head flows;
144
145 struct mod_hdr_key key;
146
147 u32 mod_hdr_id;
148};
149
150#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
151
152static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
153{
154 return jhash(key->actions,
155 key->num_actions * MLX5_MH_ACT_SZ, 0);
156}
157
158static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
159 struct mod_hdr_key *b)
160{
161 if (a->num_actions != b->num_actions)
162 return 1;
163
164 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
165}
166
167static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
168 struct mlx5e_tc_flow *flow,
169 struct mlx5e_tc_flow_parse_attr *parse_attr)
170{
171 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
172 int num_actions, actions_size, namespace, err;
173 struct mlx5e_mod_hdr_entry *mh;
174 struct mod_hdr_key key;
175 bool found = false;
176 u32 hash_key;
177
178 num_actions = parse_attr->num_mod_hdr_actions;
179 actions_size = MLX5_MH_ACT_SZ * num_actions;
180
181 key.actions = parse_attr->mod_hdr_actions;
182 key.num_actions = num_actions;
183
184 hash_key = hash_mod_hdr_info(&key);
185
186 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
187 namespace = MLX5_FLOW_NAMESPACE_FDB;
188 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
189 mod_hdr_hlist, hash_key) {
190 if (!cmp_mod_hdr_info(&mh->key, &key)) {
191 found = true;
192 break;
193 }
194 }
195 } else {
196 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
197 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
198 mod_hdr_hlist, hash_key) {
199 if (!cmp_mod_hdr_info(&mh->key, &key)) {
200 found = true;
201 break;
202 }
203 }
204 }
205
206 if (found)
207 goto attach_flow;
208
209 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
210 if (!mh)
211 return -ENOMEM;
212
213 mh->key.actions = (void *)mh + sizeof(*mh);
214 memcpy(mh->key.actions, key.actions, actions_size);
215 mh->key.num_actions = num_actions;
216 INIT_LIST_HEAD(&mh->flows);
217
218 err = mlx5_modify_header_alloc(priv->mdev, namespace,
219 mh->key.num_actions,
220 mh->key.actions,
221 &mh->mod_hdr_id);
222 if (err)
223 goto out_err;
224
225 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
226 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
227 else
228 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
229
230attach_flow:
231 list_add(&flow->mod_hdr, &mh->flows);
232 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
233 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
234 else
235 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
236
237 return 0;
238
239out_err:
240 kfree(mh);
241 return err;
242}
243
244static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
245 struct mlx5e_tc_flow *flow)
246{
247 struct list_head *next = flow->mod_hdr.next;
248
249 list_del(&flow->mod_hdr);
250
251 if (list_empty(next)) {
252 struct mlx5e_mod_hdr_entry *mh;
253
254 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
255
256 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
257 hash_del(&mh->mod_hdr_hlist);
258 kfree(mh);
259 }
260}
261
77ab67b7
OG		 262static
263struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
264{
265 struct net_device *netdev;
266 struct mlx5e_priv *priv;
267
268 netdev = __dev_get_by_index(net, ifindex);
269 priv = netdev_priv(netdev);
270 return priv->mdev;
271}
272
273static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
274{
275 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
276 void *tirc;
277 int err;
278
279 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
280 if (err)
281 goto alloc_tdn_err;
282
283 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
284
285 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 286 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 287 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
288
289 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
290 if (err)
291 goto create_tir_err;
292
293 return 0;
294
295create_tir_err:
296 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
297alloc_tdn_err:
298 return err;
299}
300
301static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
302{
303 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
304 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
305}
306
3f6d08d1
OG		 307static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
308{
309 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
310 struct mlx5e_priv *priv = hp->func_priv;
311 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
312
313 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
314 hp->num_channels);
315
316 for (i = 0; i < sz; i++) {
317 ix = i;
318 if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR)
319 ix = mlx5e_bits_invert(i, ilog2(sz));
320 ix = indirection_rqt[ix];
321 rqn = hp->pair->rqn[ix];
322 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
323 }
324}
325
326static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
327{
328 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
329 struct mlx5e_priv *priv = hp->func_priv;
330 struct mlx5_core_dev *mdev = priv->mdev;
331 void *rqtc;
332 u32 *in;
333
334 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
335 in = kvzalloc(inlen, GFP_KERNEL);
336 if (!in)
337 return -ENOMEM;
338
339 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
340
341 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
342 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
343
344 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
345
346 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
347 if (!err)
348 hp->indir_rqt.enabled = true;
349
350 kvfree(in);
351 return err;
352}
353
354static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
355{
356 struct mlx5e_priv *priv = hp->func_priv;
357 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
358 int tt, i, err;
359 void *tirc;
360
361 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
362 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
363 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
364
365 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
366 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
367 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
368 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
369
370 err = mlx5_core_create_tir(hp->func_mdev, in,
371 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
372 if (err) {
373 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
374 goto err_destroy_tirs;
375 }
376 }
377 return 0;
378
379err_destroy_tirs:
380 for (i = 0; i < tt; i++)
381 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
382 return err;
383}
384
385static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
386{
387 int tt;
388
389 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
390 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
391}
392
393static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
394 struct ttc_params *ttc_params)
395{
396 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
397 int tt;
398
399 memset(ttc_params, 0, sizeof(*ttc_params));
400
401 ttc_params->any_tt_tirn = hp->tirn;
402
403 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
404 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
405
406 ft_attr->max_fte = MLX5E_NUM_TT;
407 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
408 ft_attr->prio = MLX5E_TC_PRIO;
409}
410
411static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
412{
413 struct mlx5e_priv *priv = hp->func_priv;
414 struct ttc_params ttc_params;
415 int err;
416
417 err = mlx5e_hairpin_create_indirect_rqt(hp);
418 if (err)
419 return err;
420
421 err = mlx5e_hairpin_create_indirect_tirs(hp);
422 if (err)
423 goto err_create_indirect_tirs;
424
425 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
426 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
427 if (err)
428 goto err_create_ttc_table;
429
430 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
431 hp->num_channels, hp->ttc.ft.t->id);
432
433 return 0;
434
435err_create_ttc_table:
436 mlx5e_hairpin_destroy_indirect_tirs(hp);
437err_create_indirect_tirs:
438 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
439
440 return err;
441}
442
443static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
444{
445 struct mlx5e_priv *priv = hp->func_priv;
446
447 mlx5e_destroy_ttc_table(priv, &hp->ttc);
448 mlx5e_hairpin_destroy_indirect_tirs(hp);
449 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
450}
451
77ab67b7
OG		 452static struct mlx5e_hairpin *
453mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
454 int peer_ifindex)
455{
456 struct mlx5_core_dev *func_mdev, *peer_mdev;
457 struct mlx5e_hairpin *hp;
458 struct mlx5_hairpin *pair;
459 int err;
460
461 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
462 if (!hp)
463 return ERR_PTR(-ENOMEM);
464
465 func_mdev = priv->mdev;
466 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
467
468 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
469 if (IS_ERR(pair)) {
470 err = PTR_ERR(pair);
471 goto create_pair_err;
472 }
473 hp->pair = pair;
474 hp->func_mdev = func_mdev;
3f6d08d1
OG		 475 hp->func_priv = priv;
476 hp->num_channels = params->num_channels;
77ab67b7
OG		 477
478 err = mlx5e_hairpin_create_transport(hp);
479 if (err)
480 goto create_transport_err;
481
3f6d08d1
OG		 482 if (hp->num_channels > 1) {
483 err = mlx5e_hairpin_rss_init(hp);
484 if (err)
485 goto rss_init_err;
486 }
487
77ab67b7
OG		 488 return hp;
489
3f6d08d1
OG		 490rss_init_err:
491 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 492create_transport_err:
493 mlx5_core_hairpin_destroy(hp->pair);
494create_pair_err:
495 kfree(hp);
496 return ERR_PTR(err);
497}
498
499static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
500{
3f6d08d1
OG		 501 if (hp->num_channels > 1)
502 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 503 mlx5e_hairpin_destroy_transport(hp);
504 mlx5_core_hairpin_destroy(hp->pair);
505 kvfree(hp);
506}
507
106be53b
OG		 508static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
509{
510 return (peer_vhca_id << 16 | prio);
511}
512
5c65c564 513static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 514 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 515{
516 struct mlx5e_hairpin_entry *hpe;
106be53b 517 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 518
519 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 520 hairpin_hlist, hash_key) {
521 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 522 return hpe;
523 }
524
525 return NULL;
526}
527
106be53b
OG		 528#define UNKNOWN_MATCH_PRIO 8
529
530static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 531 struct mlx5_flow_spec *spec, u8 *match_prio,
532 struct netlink_ext_ack *extack)
106be53b
OG		 533{
534 void *headers_c, *headers_v;
535 u8 prio_val, prio_mask = 0;
536 bool vlan_present;
537
538#ifdef CONFIG_MLX5_CORE_EN_DCB
539 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 540 NL_SET_ERR_MSG_MOD(extack,
541 "only PCP trust state supported for hairpin");
106be53b
OG		 542 return -EOPNOTSUPP;
543 }
544#endif
545 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
546 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
547
548 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
549 if (vlan_present) {
550 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
551 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
552 }
553
554 if (!vlan_present || !prio_mask) {
555 prio_val = UNKNOWN_MATCH_PRIO;
556 } else if (prio_mask != 0x7) {
e98bedf5
EB		 557 NL_SET_ERR_MSG_MOD(extack,
558 "masked priority match not supported for hairpin");
106be53b
OG		 559 return -EOPNOTSUPP;
560 }
561
562 *match_prio = prio_val;
563 return 0;
564}
565
5c65c564
OG		 566static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
567 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 568 struct mlx5e_tc_flow_parse_attr *parse_attr,
569 struct netlink_ext_ack *extack)
5c65c564
OG		 570{
571 int peer_ifindex = parse_attr->mirred_ifindex;
572 struct mlx5_hairpin_params params;
d8822868 573 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 574 struct mlx5e_hairpin_entry *hpe;
575 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 576 u64 link_speed64;
577 u32 link_speed;
106be53b 578 u8 match_prio;
d8822868 579 u16 peer_id;
5c65c564
OG		 580 int err;
581
d8822868
OG		 582 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
583 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 584 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 585 return -EOPNOTSUPP;
586 }
587
d8822868 588 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 589 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
590 extack);
106be53b
OG		 591 if (err)
592 return err;
593 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 594 if (hpe)
595 goto attach_flow;
596
597 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
598 if (!hpe)
599 return -ENOMEM;
600
601 INIT_LIST_HEAD(&hpe->flows);
d8822868 602 hpe->peer_vhca_id = peer_id;
106be53b 603 hpe->prio = match_prio;
5c65c564
OG		 604
605 params.log_data_size = 15;
606 params.log_data_size = min_t(u8, params.log_data_size,
607 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
608 params.log_data_size = max_t(u8, params.log_data_size,
609 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 610
eb9180f7
OG		 611 params.log_num_packets = params.log_data_size -
612 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
613 params.log_num_packets = min_t(u8, params.log_num_packets,
614 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
615
616 params.q_counter = priv->q_counter;
3f6d08d1 617 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 618 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 619 link_speed = max_t(u32, link_speed, 50000);
620 link_speed64 = link_speed;
621 do_div(link_speed64, 50000);
622 params.num_channels = link_speed64;
623
5c65c564
OG		 624 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
625 if (IS_ERR(hp)) {
626 err = PTR_ERR(hp);
627 goto create_hairpin_err;
628 }
629
eb9180f7 630 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 631 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 632 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 633
634 hpe->hp = hp;
106be53b
OG		 635 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
636 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 637
638attach_flow:
3f6d08d1
OG		 639 if (hpe->hp->num_channels > 1) {
640 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
641 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
642 } else {
643 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
644 }
5c65c564 645 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 646
5c65c564
OG		 647 return 0;
648
649create_hairpin_err:
650 kfree(hpe);
651 return err;
652}
653
654static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
655 struct mlx5e_tc_flow *flow)
656{
657 struct list_head *next = flow->hairpin.next;
658
659 list_del(&flow->hairpin);
660
661 /* no more hairpin flows for us, release the hairpin pair */
662 if (list_empty(next)) {
663 struct mlx5e_hairpin_entry *hpe;
664
665 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
666
667 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
668 hpe->hp->pair->peer_mdev->priv.name);
669
670 mlx5e_hairpin_destroy(hpe->hp);
671 hash_del(&hpe->hairpin_hlist);
672 kfree(hpe);
673 }
674}
675
c83954ab 676static int
74491de9 677mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 678 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 679 struct mlx5e_tc_flow *flow,
680 struct netlink_ext_ack *extack)
e8f887ac 681{
aa0cbbae 682 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 683 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 684 struct mlx5_flow_destination dest[2] = {};
66958ed9 685 struct mlx5_flow_act flow_act = {
3bc4b7bf 686 .action = attr->action,
a9db0ecf 687 .has_flow_tag = true,
3bc4b7bf 688 .flow_tag = attr->flow_tag,
60786f09 689 .reformat_id = 0,
66958ed9 690 };
aad7e08d 691 struct mlx5_fc *counter = NULL;
e8f887ac 692 bool table_created = false;
5c65c564 693 int err, dest_ix = 0;
e8f887ac 694
3f6d08d1 695 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
e98bedf5 696 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
3f6d08d1 697 if (err) {
3f6d08d1
OG		 698 goto err_add_hairpin_flow;
699 }
700 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
701 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
702 dest[dest_ix].ft = attr->hairpin_ft;
703 } else {
5c65c564
OG		 704 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
705 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 706 }
707 dest_ix++;
3f6d08d1
OG		 708 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
709 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
710 dest[dest_ix].ft = priv->fs.vlan.ft.t;
711 dest_ix++;
5c65c564 712 }
aad7e08d 713
5c65c564
OG		 714 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
715 counter = mlx5_fc_create(dev, true);
716 if (IS_ERR(counter)) {
c83954ab 717 err = PTR_ERR(counter);
5c65c564
OG		 718 goto err_fc_create;
719 }
720 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 721 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 722 dest_ix++;
b8aee822 723 attr->counter = counter;
aad7e08d
AV		 724 }
725
2f4fe4ca 726 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 727 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 728 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 729 kfree(parse_attr->mod_hdr_actions);
c83954ab 730 if (err)
2f4fe4ca 731 goto err_create_mod_hdr_id;
2f4fe4ca
OG		 732 }
733
acff797c 734 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 735 int tc_grp_size, tc_tbl_size;
736 u32 max_flow_counter;
737
738 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
739 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
740
741 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
742
743 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
744 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
745
acff797c
MG		 746 priv->fs.tc.t =
747 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
748 MLX5E_TC_PRIO,
21b9c144 749 tc_tbl_size,
acff797c 750 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 751 MLX5E_TC_FT_LEVEL, 0);
acff797c 752 if (IS_ERR(priv->fs.tc.t)) {
e98bedf5
EB		 753 NL_SET_ERR_MSG_MOD(extack,
754 "Failed to create tc offload table\n");
e8f887ac
AV		 755 netdev_err(priv->netdev,
756 "Failed to create tc offload table\n");
c83954ab 757 err = PTR_ERR(priv->fs.tc.t);
aad7e08d 758 goto err_create_ft;
e8f887ac
AV		 759 }
760
761 table_created = true;
762 }
763
38aa51c1
OG		 764 if (attr->match_level != MLX5_MATCH_NONE)
765 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
766
c83954ab
RL		 767 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
768 &flow_act, dest, dest_ix);
aad7e08d 769
c83954ab
RL		 770 if (IS_ERR(flow->rule[0])) {
771 err = PTR_ERR(flow->rule[0]);
aad7e08d 772 goto err_add_rule;
c83954ab 773 }
aad7e08d 774
c83954ab 775 return 0;
e8f887ac 776
aad7e08d
AV		 777err_add_rule:
778 if (table_created) {
acff797c
MG		 779 mlx5_destroy_flow_table(priv->fs.tc.t);
780 priv->fs.tc.t = NULL;
e8f887ac 781 }
aad7e08d 782err_create_ft:
2f4fe4ca 783 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 784 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 785err_create_mod_hdr_id:
aad7e08d 786 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 787err_fc_create:
788 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
789 mlx5e_hairpin_flow_del(priv, flow);
790err_add_hairpin_flow:
c83954ab 791 return err;
e8f887ac
AV		 792}
793
d85cdccb
OG		 794static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
795 struct mlx5e_tc_flow *flow)
796{
513f8f7f 797 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 798 struct mlx5_fc *counter = NULL;
799
b8aee822 800 counter = attr->counter;
e4ad91f2 801 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 802 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 803
b3a433de 804 if (!mlx5e_tc_num_filters(priv) && priv->fs.tc.t) {
d85cdccb
OG		 805 mlx5_destroy_flow_table(priv->fs.tc.t);
806 priv->fs.tc.t = NULL;
807 }
2f4fe4ca 808
513f8f7f 809 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 810 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 811
812 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
813 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 814}
815
aa0cbbae
OG		 816static void mlx5e_detach_encap(struct mlx5e_priv *priv,
817 struct mlx5e_tc_flow *flow);
818
3c37745e
OG		 819static int mlx5e_attach_encap(struct mlx5e_priv *priv,
820 struct ip_tunnel_info *tun_info,
821 struct net_device *mirred_dev,
822 struct net_device **encap_dev,
e98bedf5
EB		 823 struct mlx5e_tc_flow *flow,
824 struct netlink_ext_ack *extack);
3c37745e 825
c83954ab 826static int
74491de9 827mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 828 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 829 struct mlx5e_tc_flow *flow,
830 struct netlink_ext_ack *extack)
adb4c123
OG		 831{
832 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 833 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3c37745e 834 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 835 struct mlx5_fc *counter = NULL;
3c37745e
OG		 836 struct mlx5e_rep_priv *rpriv;
837 struct mlx5e_priv *out_priv;
c83954ab 838 int err = 0, encap_err = 0;
8b32580d 839
60786f09 840 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) {
3c37745e
OG		 841 out_dev = __dev_get_by_index(dev_net(priv->netdev),
842 attr->parse_attr->mirred_ifindex);
c83954ab
RL		 843 encap_err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
844 out_dev, &encap_dev, flow,
845 extack);
846 if (encap_err && encap_err != -EAGAIN) {
847 err = encap_err;
848 goto err_attach_encap;
3c37745e
OG		 849 }
850 out_priv = netdev_priv(encap_dev);
851 rpriv = out_priv->ppriv;
592d3651
CM		 852 attr->out_rep[attr->out_count] = rpriv->rep;
853 attr->out_mdev[attr->out_count++] = out_priv->mdev;
3c37745e
OG		 854 }
855
8b32580d 856 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 857 if (err)
aa0cbbae 858 goto err_add_vlan;
adb4c123 859
d7e75a32 860 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 861 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 862 kfree(parse_attr->mod_hdr_actions);
c83954ab 863 if (err)
d7e75a32 864 goto err_mod_hdr;
d7e75a32
OG		 865 }
866
b8aee822
MB		 867 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
868 counter = mlx5_fc_create(esw->dev, true);
869 if (IS_ERR(counter)) {
c83954ab 870 err = PTR_ERR(counter);
b8aee822
MB		 871 goto err_create_counter;
872 }
873
874 attr->counter = counter;
875 }
876
c83954ab 877 /* we get here if (1) there's no error or when
3c37745e
OG		 878 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
879 */
c83954ab
RL		 880 if (encap_err != -EAGAIN) {
881 flow->rule[0] = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
882 if (IS_ERR(flow->rule[0])) {
883 err = PTR_ERR(flow->rule[0]);
3c37745e 884 goto err_add_rule;
c83954ab 885 }
e4ad91f2
CM		 886
887 if (attr->mirror_count) {
888 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, &parse_attr->spec, attr);
c83954ab
RL		 889 if (IS_ERR(flow->rule[1])) {
890 err = PTR_ERR(flow->rule[1]);
e4ad91f2 891 goto err_fwd_rule;
c83954ab 892 }
e4ad91f2 893 }
3c37745e 894 }
c83954ab
RL		 895
896 return encap_err;
aa0cbbae 897
e4ad91f2 898err_fwd_rule:
c83954ab 899 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
aa0cbbae 900err_add_rule:
b8aee822
MB		 901 mlx5_fc_destroy(esw->dev, counter);
902err_create_counter:
513f8f7f 903 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 904 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 905err_mod_hdr:
aa0cbbae
OG		 906 mlx5_eswitch_del_vlan_action(esw, attr);
907err_add_vlan:
60786f09 908 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
aa0cbbae 909 mlx5e_detach_encap(priv, flow);
3c37745e 910err_attach_encap:
c83954ab 911 return err;
aa0cbbae 912}
d85cdccb
OG		 913
914static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
915 struct mlx5e_tc_flow *flow)
916{
917 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 918 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 919
232c0013
HHZ		 920 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
921 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
e4ad91f2
CM		 922 if (attr->mirror_count)
923 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[1], attr);
924 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
232c0013 925 }
d85cdccb 926
513f8f7f 927 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 928
60786f09 929 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) {
d85cdccb 930 mlx5e_detach_encap(priv, flow);
513f8f7f 931 kvfree(attr->parse_attr);
232c0013 932 }
d7e75a32 933
513f8f7f 934 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 935 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 936
937 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
938 mlx5_fc_destroy(esw->dev, attr->counter);
d85cdccb
OG		 939}
940
232c0013
HHZ		 941void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
942 struct mlx5e_encap_entry *e)
943{
3c37745e
OG		 944 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
945 struct mlx5_esw_flow_attr *esw_attr;
232c0013
HHZ		 946 struct mlx5e_tc_flow *flow;
947 int err;
948
60786f09
MB		 949 err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
950 e->encap_size, e->encap_header,
31ca3648 951 MLX5_FLOW_NAMESPACE_FDB,
60786f09 952 &e->encap_id);
232c0013
HHZ		 953 if (err) {
954 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
955 err);
956 return;
957 }
958 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 959 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 960
961 list_for_each_entry(flow, &e->flows, encap) {
3c37745e
OG		 962 esw_attr = flow->esw_attr;
963 esw_attr->encap_id = e->encap_id;
e4ad91f2
CM		 964 flow->rule[0] = mlx5_eswitch_add_offloaded_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
965 if (IS_ERR(flow->rule[0])) {
966 err = PTR_ERR(flow->rule[0]);
232c0013
HHZ		 967 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
968 err);
969 continue;
970 }
e4ad91f2
CM		 971
972 if (esw_attr->mirror_count) {
973 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
974 if (IS_ERR(flow->rule[1])) {
975 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], esw_attr);
976 err = PTR_ERR(flow->rule[1]);
977 mlx5_core_warn(priv->mdev, "Failed to update cached mirror flow, %d\n",
978 err);
979 continue;
980 }
981 }
982
232c0013
HHZ		 983 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
984 }
985}
986
987void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
988 struct mlx5e_encap_entry *e)
989{
3c37745e 990 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
232c0013 991 struct mlx5e_tc_flow *flow;
232c0013
HHZ		 992
993 list_for_each_entry(flow, &e->flows, encap) {
994 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
e4ad91f2
CM		 995 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
996
232c0013 997 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
e4ad91f2
CM		 998 if (attr->mirror_count)
999 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[1], attr);
1000 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
232c0013
HHZ		 1001 }
1002 }
1003
1004 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
1005 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
60786f09 1006 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1007 }
1008}
1009
b8aee822
MB		 1010static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1011{
1012 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1013 return flow->esw_attr->counter;
1014 else
1015 return flow->nic_attr->counter;
1016}
1017
f6dfb4c3
HHZ		 1018void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1019{
1020 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1021 u64 bytes, packets, lastuse = 0;
1022 struct mlx5e_tc_flow *flow;
1023 struct mlx5e_encap_entry *e;
1024 struct mlx5_fc *counter;
1025 struct neigh_table *tbl;
1026 bool neigh_used = false;
1027 struct neighbour *n;
1028
1029 if (m_neigh->family == AF_INET)
1030 tbl = &arp_tbl;
1031#if IS_ENABLED(CONFIG_IPV6)
1032 else if (m_neigh->family == AF_INET6)
423c9db2 1033 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1034#endif
1035 else
1036 return;
1037
1038 list_for_each_entry(e, &nhe->encap_list, encap_list) {
1039 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1040 continue;
1041 list_for_each_entry(flow, &e->flows, encap) {
1042 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
b8aee822 1043 counter = mlx5e_tc_get_counter(flow);
f6dfb4c3
HHZ		 1044 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1045 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1046 neigh_used = true;
1047 break;
1048 }
1049 }
1050 }
e36d4810
RD		 1051 if (neigh_used)
1052 break;
f6dfb4c3
HHZ		 1053 }
1054
1055 if (neigh_used) {
1056 nhe->reported_lastuse = jiffies;
1057
1058 /* find the relevant neigh according to the cached device and
1059 * dst ip pair
1060 */
1061 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1062 if (!n)
f6dfb4c3 1063 return;
f6dfb4c3
HHZ		 1064
1065 neigh_event_send(n, NULL);
1066 neigh_release(n);
1067 }
1068}
1069
d85cdccb
OG		 1070static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1071 struct mlx5e_tc_flow *flow)
1072{
5067b602
RD		 1073 struct list_head *next = flow->encap.next;
1074
1075 list_del(&flow->encap);
1076 if (list_empty(next)) {
c1ae1152 1077 struct mlx5e_encap_entry *e;
5067b602 1078
c1ae1152 1079 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1080 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1081
1082 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1083 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1084
cdc5a7f3 1085 hash_del_rcu(&e->encap_hlist);
232c0013 1086 kfree(e->encap_header);
5067b602
RD		 1087 kfree(e);
1088 }
1089}
1090
e8f887ac 1091static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1092 struct mlx5e_tc_flow *flow)
e8f887ac 1093{
d85cdccb
OG		 1094 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1095 mlx5e_tc_del_fdb_flow(priv, flow);
1096 else
1097 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 1098}
1099
bbd00f7e
HHZ		 1100static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
1101 struct tc_cls_flower_offload *f)
1102{
1103 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1104 outer_headers);
1105 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1106 outer_headers);
1107 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1108 misc_parameters);
1109 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1110 misc_parameters);
1111
1112 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
1113 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1114
1115 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
1116 struct flow_dissector_key_keyid *key =
1117 skb_flow_dissector_target(f->dissector,
1118 FLOW_DISSECTOR_KEY_ENC_KEYID,
1119 f->key);
1120 struct flow_dissector_key_keyid *mask =
1121 skb_flow_dissector_target(f->dissector,
1122 FLOW_DISSECTOR_KEY_ENC_KEYID,
1123 f->mask);
1124 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
1125 be32_to_cpu(mask->keyid));
1126 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
1127 be32_to_cpu(key->keyid));
1128 }
1129}
1130
1131static int parse_tunnel_attr(struct mlx5e_priv *priv,
1132 struct mlx5_flow_spec *spec,
1133 struct tc_cls_flower_offload *f)
1134{
e98bedf5 1135 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1136 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1137 outer_headers);
1138 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1139 outer_headers);
1140
2e72eb43
OG		 1141 struct flow_dissector_key_control *enc_control =
1142 skb_flow_dissector_target(f->dissector,
1143 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1144 f->key);
1145
bbd00f7e
HHZ		 1146 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
1147 struct flow_dissector_key_ports *key =
1148 skb_flow_dissector_target(f->dissector,
1149 FLOW_DISSECTOR_KEY_ENC_PORTS,
1150 f->key);
1151 struct flow_dissector_key_ports *mask =
1152 skb_flow_dissector_target(f->dissector,
1153 FLOW_DISSECTOR_KEY_ENC_PORTS,
1154 f->mask);
1155
1156 /* Full udp dst port must be given */
1157 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 1158 goto vxlan_match_offload_err;
bbd00f7e 1159
a3e67366 1160 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 1161 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
1162 parse_vxlan_attr(spec, f);
2fcd82e9 1163 else {
e98bedf5
EB		 1164 NL_SET_ERR_MSG_MOD(extack,
1165 "port isn't an offloaded vxlan udp dport");
2fcd82e9
OG		 1166 netdev_warn(priv->netdev,
1167 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 1168 return -EOPNOTSUPP;
2fcd82e9 1169 }
bbd00f7e
HHZ		 1170
1171 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1172 udp_dport, ntohs(mask->dst));
1173 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1174 udp_dport, ntohs(key->dst));
1175
cd377663
OG		 1176 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1177 udp_sport, ntohs(mask->src));
1178 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1179 udp_sport, ntohs(key->src));
bbd00f7e 1180 } else { /* udp dst port must be given */
2fcd82e9 1181vxlan_match_offload_err:
e98bedf5
EB		 1182 NL_SET_ERR_MSG_MOD(extack,
1183 "IP tunnel decap offload supported only for vxlan, must set UDP dport");
2fcd82e9
OG		 1184 netdev_warn(priv->netdev,
1185 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
1186 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1187 }
1188
2e72eb43 1189 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 1190 struct flow_dissector_key_ipv4_addrs *key =
1191 skb_flow_dissector_target(f->dissector,
1192 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1193 f->key);
1194 struct flow_dissector_key_ipv4_addrs *mask =
1195 skb_flow_dissector_target(f->dissector,
1196 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1197 f->mask);
1198 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1199 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1200 ntohl(mask->src));
1201 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1202 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1203 ntohl(key->src));
1204
1205 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1206 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1207 ntohl(mask->dst));
1208 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1209 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1210 ntohl(key->dst));
bbd00f7e 1211
2e72eb43
OG		 1212 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1213 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 1214 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1215 struct flow_dissector_key_ipv6_addrs *key =
1216 skb_flow_dissector_target(f->dissector,
1217 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1218 f->key);
1219 struct flow_dissector_key_ipv6_addrs *mask =
1220 skb_flow_dissector_target(f->dissector,
1221 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1222 f->mask);
1223
1224 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1225 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1226 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1227 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1228 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1229 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1230
1231 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1232 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1233 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1234 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1235 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1236 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1237
1238 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1239 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1240 }
bbd00f7e 1241
bcef735c
OG		 1242 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_IP)) {
1243 struct flow_dissector_key_ip *key =
1244 skb_flow_dissector_target(f->dissector,
1245 FLOW_DISSECTOR_KEY_ENC_IP,
1246 f->key);
1247 struct flow_dissector_key_ip *mask =
1248 skb_flow_dissector_target(f->dissector,
1249 FLOW_DISSECTOR_KEY_ENC_IP,
1250 f->mask);
1251
1252 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1253 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1254
1255 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1256 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1257
1258 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1259 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
e98bedf5
EB		 1260
1261 if (mask->ttl &&
1262 !MLX5_CAP_ESW_FLOWTABLE_FDB
1263 (priv->mdev,
1264 ft_field_support.outer_ipv4_ttl)) {
1265 NL_SET_ERR_MSG_MOD(extack,
1266 "Matching on TTL is not supported");
1267 return -EOPNOTSUPP;
1268 }
1269
bcef735c
OG		 1270 }
1271
bbd00f7e
HHZ		 1272 /* Enforce DMAC when offloading incoming tunneled flows.
1273 * Flow counters require a match on the DMAC.
1274 */
1275 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1276 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1277 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1278 dmac_47_16), priv->netdev->dev_addr);
1279
1280 /* let software handle IP fragments */
1281 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1282 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1283
1284 return 0;
1285}
1286
de0af0bf
RD		 1287static int __parse_cls_flower(struct mlx5e_priv *priv,
1288 struct mlx5_flow_spec *spec,
1289 struct tc_cls_flower_offload *f,
d708f902 1290 u8 *match_level)
e3a2b7ed 1291{
e98bedf5 1292 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1293 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1294 outer_headers);
1295 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1296 outer_headers);
699e96dd
JL		 1297 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1298 misc_parameters);
1299 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1300 misc_parameters);
e3a2b7ed
AV		 1301 u16 addr_type = 0;
1302 u8 ip_proto = 0;
1303
d708f902 1304 *match_level = MLX5_MATCH_NONE;
de0af0bf 1305
e3a2b7ed
AV		 1306 if (f->dissector->used_keys &
1307 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1308 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1309 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1310 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1311 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1312 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1313 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1314 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1315 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1316 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1317 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1318 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1319 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1320 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c
OG		 1321 BIT(FLOW_DISSECTOR_KEY_IP) |
1322 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
e98bedf5 1323 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed
AV		 1324 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1325 f->dissector->used_keys);
1326 return -EOPNOTSUPP;
1327 }
1328
bbd00f7e
HHZ		 1329 if ((dissector_uses_key(f->dissector,
1330 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1331 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1332 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1333 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1334 struct flow_dissector_key_control *key =
1335 skb_flow_dissector_target(f->dissector,
1336 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1337 f->key);
1338 switch (key->addr_type) {
1339 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1340 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 1341 if (parse_tunnel_attr(priv, spec, f))
1342 return -EOPNOTSUPP;
1343 break;
1344 default:
1345 return -EOPNOTSUPP;
1346 }
1347
1348 /* In decap flow, header pointers should point to the inner
1349 * headers, outer header were already set by parse_tunnel_attr
1350 */
1351 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1352 inner_headers);
1353 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1354 inner_headers);
1355 }
1356
e3a2b7ed
AV		 1357 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1358 struct flow_dissector_key_eth_addrs *key =
1359 skb_flow_dissector_target(f->dissector,
1360 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1361 f->key);
1362 struct flow_dissector_key_eth_addrs *mask =
1363 skb_flow_dissector_target(f->dissector,
1364 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1365 f->mask);
1366
1367 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1368 dmac_47_16),
1369 mask->dst);
1370 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1371 dmac_47_16),
1372 key->dst);
1373
1374 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1375 smac_47_16),
1376 mask->src);
1377 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1378 smac_47_16),
1379 key->src);
54782900
OG		 1380
1381 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
d708f902 1382 *match_level = MLX5_MATCH_L2;
e3a2b7ed
AV		 1383 }
1384
095b6cfd
OG		 1385 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1386 struct flow_dissector_key_vlan *key =
1387 skb_flow_dissector_target(f->dissector,
1388 FLOW_DISSECTOR_KEY_VLAN,
1389 f->key);
1390 struct flow_dissector_key_vlan *mask =
1391 skb_flow_dissector_target(f->dissector,
1392 FLOW_DISSECTOR_KEY_VLAN,
1393 f->mask);
699e96dd
JL		 1394 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1395 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1396 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1397 svlan_tag, 1);
1398 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1399 svlan_tag, 1);
1400 } else {
1401 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1402 cvlan_tag, 1);
1403 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1404 cvlan_tag, 1);
1405 }
095b6cfd
OG		 1406
1407 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1408 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 1409
1410 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1411 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
54782900 1412
d708f902 1413 *match_level = MLX5_MATCH_L2;
54782900 1414 }
cee26487
JL		 1415 } else {
1416 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1417 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
54782900
OG		 1418 }
1419
699e96dd
JL		 1420 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CVLAN)) {
1421 struct flow_dissector_key_vlan *key =
1422 skb_flow_dissector_target(f->dissector,
1423 FLOW_DISSECTOR_KEY_CVLAN,
1424 f->key);
1425 struct flow_dissector_key_vlan *mask =
1426 skb_flow_dissector_target(f->dissector,
1427 FLOW_DISSECTOR_KEY_CVLAN,
1428 f->mask);
1429 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1430 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1431 MLX5_SET(fte_match_set_misc, misc_c,
1432 outer_second_svlan_tag, 1);
1433 MLX5_SET(fte_match_set_misc, misc_v,
1434 outer_second_svlan_tag, 1);
1435 } else {
1436 MLX5_SET(fte_match_set_misc, misc_c,
1437 outer_second_cvlan_tag, 1);
1438 MLX5_SET(fte_match_set_misc, misc_v,
1439 outer_second_cvlan_tag, 1);
1440 }
1441
1442 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1443 mask->vlan_id);
1444 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1445 key->vlan_id);
1446 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1447 mask->vlan_priority);
1448 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1449 key->vlan_priority);
1450
1451 *match_level = MLX5_MATCH_L2;
1452 }
1453 }
1454
54782900
OG		 1455 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1456 struct flow_dissector_key_basic *key =
1457 skb_flow_dissector_target(f->dissector,
1458 FLOW_DISSECTOR_KEY_BASIC,
1459 f->key);
1460 struct flow_dissector_key_basic *mask =
1461 skb_flow_dissector_target(f->dissector,
1462 FLOW_DISSECTOR_KEY_BASIC,
1463 f->mask);
1464 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1465 ntohs(mask->n_proto));
1466 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1467 ntohs(key->n_proto));
1468
1469 if (mask->n_proto)
d708f902 1470 *match_level = MLX5_MATCH_L2;
54782900
OG		 1471 }
1472
1473 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1474 struct flow_dissector_key_control *key =
1475 skb_flow_dissector_target(f->dissector,
1476 FLOW_DISSECTOR_KEY_CONTROL,
1477 f->key);
1478
1479 struct flow_dissector_key_control *mask =
1480 skb_flow_dissector_target(f->dissector,
1481 FLOW_DISSECTOR_KEY_CONTROL,
1482 f->mask);
1483 addr_type = key->addr_type;
1484
1485 /* the HW doesn't support frag first/later */
1486 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1487 return -EOPNOTSUPP;
1488
1489 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1490 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1491 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1492 key->flags & FLOW_DIS_IS_FRAGMENT);
1493
1494 /* the HW doesn't need L3 inline to match on frag=no */
1495 if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
d708f902 1496 *match_level = MLX5_INLINE_MODE_L2;
54782900
OG		 1497 /* *** L2 attributes parsing up to here *** */
1498 else
d708f902 1499 *match_level = MLX5_INLINE_MODE_IP;
095b6cfd
OG		 1500 }
1501 }
1502
54782900
OG		 1503 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1504 struct flow_dissector_key_basic *key =
1505 skb_flow_dissector_target(f->dissector,
1506 FLOW_DISSECTOR_KEY_BASIC,
1507 f->key);
1508 struct flow_dissector_key_basic *mask =
1509 skb_flow_dissector_target(f->dissector,
1510 FLOW_DISSECTOR_KEY_BASIC,
1511 f->mask);
1512 ip_proto = key->ip_proto;
1513
1514 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1515 mask->ip_proto);
1516 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1517 key->ip_proto);
1518
1519 if (mask->ip_proto)
d708f902 1520 *match_level = MLX5_MATCH_L3;
54782900
OG		 1521 }
1522
e3a2b7ed
AV		 1523 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1524 struct flow_dissector_key_ipv4_addrs *key =
1525 skb_flow_dissector_target(f->dissector,
1526 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1527 f->key);
1528 struct flow_dissector_key_ipv4_addrs *mask =
1529 skb_flow_dissector_target(f->dissector,
1530 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1531 f->mask);
1532
1533 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1534 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1535 &mask->src, sizeof(mask->src));
1536 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1537 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1538 &key->src, sizeof(key->src));
1539 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1540 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1541 &mask->dst, sizeof(mask->dst));
1542 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1543 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1544 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1545
1546 if (mask->src || mask->dst)
d708f902 1547 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1548 }
1549
1550 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1551 struct flow_dissector_key_ipv6_addrs *key =
1552 skb_flow_dissector_target(f->dissector,
1553 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1554 f->key);
1555 struct flow_dissector_key_ipv6_addrs *mask =
1556 skb_flow_dissector_target(f->dissector,
1557 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1558 f->mask);
1559
1560 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1561 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1562 &mask->src, sizeof(mask->src));
1563 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1564 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1565 &key->src, sizeof(key->src));
1566
1567 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1568 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1569 &mask->dst, sizeof(mask->dst));
1570 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1571 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1572 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1573
1574 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1575 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
d708f902 1576 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1577 }
1578
1f97a526
OG		 1579 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1580 struct flow_dissector_key_ip *key =
1581 skb_flow_dissector_target(f->dissector,
1582 FLOW_DISSECTOR_KEY_IP,
1583 f->key);
1584 struct flow_dissector_key_ip *mask =
1585 skb_flow_dissector_target(f->dissector,
1586 FLOW_DISSECTOR_KEY_IP,
1587 f->mask);
1588
1589 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1590 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1591
1592 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1593 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1594
a8ade55f
OG		 1595 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1596 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 1597
a8ade55f
OG		 1598 if (mask->ttl &&
1599 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1600 ft_field_support.outer_ipv4_ttl)) {
1601 NL_SET_ERR_MSG_MOD(extack,
1602 "Matching on TTL is not supported");
1f97a526 1603 return -EOPNOTSUPP;
e98bedf5 1604 }
a8ade55f
OG		 1605
1606 if (mask->tos || mask->ttl)
d708f902 1607 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1608 }
1609
54782900
OG		 1610 /* *** L3 attributes parsing up to here *** */
1611
e3a2b7ed
AV		 1612 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1613 struct flow_dissector_key_ports *key =
1614 skb_flow_dissector_target(f->dissector,
1615 FLOW_DISSECTOR_KEY_PORTS,
1616 f->key);
1617 struct flow_dissector_key_ports *mask =
1618 skb_flow_dissector_target(f->dissector,
1619 FLOW_DISSECTOR_KEY_PORTS,
1620 f->mask);
1621 switch (ip_proto) {
1622 case IPPROTO_TCP:
1623 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1624 tcp_sport, ntohs(mask->src));
1625 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1626 tcp_sport, ntohs(key->src));
1627
1628 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1629 tcp_dport, ntohs(mask->dst));
1630 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1631 tcp_dport, ntohs(key->dst));
1632 break;
1633
1634 case IPPROTO_UDP:
1635 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1636 udp_sport, ntohs(mask->src));
1637 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1638 udp_sport, ntohs(key->src));
1639
1640 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1641 udp_dport, ntohs(mask->dst));
1642 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1643 udp_dport, ntohs(key->dst));
1644 break;
1645 default:
e98bedf5
EB		 1646 NL_SET_ERR_MSG_MOD(extack,
1647 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1648 netdev_err(priv->netdev,
1649 "Only UDP and TCP transport are supported\n");
1650 return -EINVAL;
1651 }
de0af0bf
RD		 1652
1653 if (mask->src || mask->dst)
d708f902 1654 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1655 }
1656
e77834ec
OG		 1657 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1658 struct flow_dissector_key_tcp *key =
1659 skb_flow_dissector_target(f->dissector,
1660 FLOW_DISSECTOR_KEY_TCP,
1661 f->key);
1662 struct flow_dissector_key_tcp *mask =
1663 skb_flow_dissector_target(f->dissector,
1664 FLOW_DISSECTOR_KEY_TCP,
1665 f->mask);
1666
1667 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1668 ntohs(mask->flags));
1669 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1670 ntohs(key->flags));
1671
1672 if (mask->flags)
d708f902 1673 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1674 }
1675
e3a2b7ed
AV		 1676 return 0;
1677}
1678
de0af0bf 1679static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1680 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 1681 struct mlx5_flow_spec *spec,
1682 struct tc_cls_flower_offload *f)
1683{
e98bedf5 1684 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1685 struct mlx5_core_dev *dev = priv->mdev;
1686 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1687 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1688 struct mlx5_eswitch_rep *rep;
d708f902 1689 u8 match_level;
de0af0bf
RD		 1690 int err;
1691
d708f902 1692 err = __parse_cls_flower(priv, spec, f, &match_level);
de0af0bf 1693
1d447a39
SM		 1694 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1695 rep = rpriv->rep;
1696 if (rep->vport != FDB_UPLINK_VPORT &&
1697 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1698 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1699 NL_SET_ERR_MSG_MOD(extack,
1700 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1701 netdev_warn(priv->netdev,
1702 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1703 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1704 return -EOPNOTSUPP;
1705 }
1706 }
1707
38aa51c1
OG		 1708 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1709 flow->esw_attr->match_level = match_level;
1710 else
1711 flow->nic_attr->match_level = match_level;
1712
de0af0bf
RD		 1713 return err;
1714}
1715
d79b6df6
OG		 1716struct pedit_headers {
1717 struct ethhdr eth;
1718 struct iphdr ip4;
1719 struct ipv6hdr ip6;
1720 struct tcphdr tcp;
1721 struct udphdr udp;
1722};
1723
1724static int pedit_header_offsets[] = {
1725 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1726 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1727 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1728 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1729 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1730};
1731
1732#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1733
1734static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1735 struct pedit_headers *masks,
1736 struct pedit_headers *vals)
1737{
1738 u32 *curr_pmask, *curr_pval;
1739
1740 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1741 goto out_err;
1742
1743 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1744 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1745
1746 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1747 goto out_err;
1748
1749 *curr_pmask |= mask;
1750 *curr_pval |= (val & mask);
1751
1752 return 0;
1753
1754out_err:
1755 return -EOPNOTSUPP;
1756}
1757
1758struct mlx5_fields {
1759 u8 field;
1760 u8 size;
1761 u32 offset;
1762};
1763
a8e4f0c4
OG		 1764#define OFFLOAD(fw_field, size, field, off) \
1765 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1766
d79b6df6 1767static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1768 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1769 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1770 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1771 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1772 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1773
1774 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1775 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1776 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1777
1778 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1779 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1780 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1781 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1782 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1783 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1784 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1785 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1786 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1787
1788 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1789 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1790 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1791
1792 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1793 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1794};
1795
1796/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1797 * max from the SW pedit action. On success, it says how many HW actions were
1798 * actually parsed.
1799 */
1800static int offload_pedit_fields(struct pedit_headers *masks,
1801 struct pedit_headers *vals,
e98bedf5
EB		 1802 struct mlx5e_tc_flow_parse_attr *parse_attr,
1803 struct netlink_ext_ack *extack)
d79b6df6
OG		 1804{
1805 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1806 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1807 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1808 struct mlx5_fields *f;
1809 u8 cmd, field_bsize;
e3ca4e05 1810 u32 s_mask, a_mask;
d79b6df6 1811 unsigned long mask;
2b64beba
OG		 1812 __be32 mask_be32;
1813 __be16 mask_be16;
d79b6df6
OG		 1814 void *action;
1815
1816 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1817 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1818 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1819 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1820
1821 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1822 action = parse_attr->mod_hdr_actions;
1823 max_actions = parse_attr->num_mod_hdr_actions;
1824 nactions = 0;
1825
1826 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1827 f = &fields[i];
1828 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1829 s_mask = 0;
1830 a_mask = 0;
d79b6df6
OG		 1831
1832 s_masks_p = (void *)set_masks + f->offset;
1833 a_masks_p = (void *)add_masks + f->offset;
1834
1835 memcpy(&s_mask, s_masks_p, f->size);
1836 memcpy(&a_mask, a_masks_p, f->size);
1837
1838 if (!s_mask && !a_mask) /* nothing to offload here */
1839 continue;
1840
1841 if (s_mask && a_mask) {
e98bedf5
EB		 1842 NL_SET_ERR_MSG_MOD(extack,
1843 "can't set and add to the same HW field");
d79b6df6
OG		 1844 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1845 return -EOPNOTSUPP;
1846 }
1847
1848 if (nactions == max_actions) {
e98bedf5
EB		 1849 NL_SET_ERR_MSG_MOD(extack,
1850 "too many pedit actions, can't offload");
d79b6df6
OG		 1851 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1852 return -EOPNOTSUPP;
1853 }
1854
1855 if (s_mask) {
1856 cmd = MLX5_ACTION_TYPE_SET;
1857 mask = s_mask;
1858 vals_p = (void *)set_vals + f->offset;
1859 /* clear to denote we consumed this field */
1860 memset(s_masks_p, 0, f->size);
1861 } else {
1862 cmd = MLX5_ACTION_TYPE_ADD;
1863 mask = a_mask;
1864 vals_p = (void *)add_vals + f->offset;
1865 /* clear to denote we consumed this field */
1866 memset(a_masks_p, 0, f->size);
1867 }
1868
d79b6df6 1869 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1870
2b64beba
OG		 1871 if (field_bsize == 32) {
1872 mask_be32 = *(__be32 *)&mask;
1873 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1874 } else if (field_bsize == 16) {
1875 mask_be16 = *(__be16 *)&mask;
1876 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1877 }
1878
d79b6df6 1879 first = find_first_bit(&mask, field_bsize);
2b64beba 1880 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1881 last = find_last_bit(&mask, field_bsize);
2b64beba 1882 if (first < next_z && next_z < last) {
e98bedf5
EB		 1883 NL_SET_ERR_MSG_MOD(extack,
1884 "rewrite of few sub-fields isn't supported");
2b64beba 1885 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1886 mask);
1887 return -EOPNOTSUPP;
1888 }
1889
1890 MLX5_SET(set_action_in, action, action_type, cmd);
1891 MLX5_SET(set_action_in, action, field, f->field);
1892
1893 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1894 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1895 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1896 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1897 }
1898
1899 if (field_bsize == 32)
2b64beba 1900 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1901 else if (field_bsize == 16)
2b64beba 1902 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1903 else if (field_bsize == 8)
2b64beba 1904 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1905
1906 action += action_size;
1907 nactions++;
1908 }
1909
1910 parse_attr->num_mod_hdr_actions = nactions;
1911 return 0;
1912}
1913
1914static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1915 const struct tc_action *a, int namespace,
1916 struct mlx5e_tc_flow_parse_attr *parse_attr)
1917{
1918 int nkeys, action_size, max_actions;
1919
1920 nkeys = tcf_pedit_nkeys(a);
1921 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1922
1923 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1924 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1925 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1926 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1927
1928 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1929 max_actions = min(max_actions, nkeys * 16);
1930
1931 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1932 if (!parse_attr->mod_hdr_actions)
1933 return -ENOMEM;
1934
1935 parse_attr->num_mod_hdr_actions = max_actions;
1936 return 0;
1937}
1938
1939static const struct pedit_headers zero_masks = {};
1940
1941static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1942 const struct tc_action *a, int namespace,
e98bedf5
EB		 1943 struct mlx5e_tc_flow_parse_attr *parse_attr,
1944 struct netlink_ext_ack *extack)
d79b6df6
OG		 1945{
1946 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1947 int nkeys, i, err = -EOPNOTSUPP;
1948 u32 mask, val, offset;
1949 u8 cmd, htype;
1950
1951 nkeys = tcf_pedit_nkeys(a);
1952
1953 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1954 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1955
1956 for (i = 0; i < nkeys; i++) {
1957 htype = tcf_pedit_htype(a, i);
1958 cmd = tcf_pedit_cmd(a, i);
1959 err = -EOPNOTSUPP; /* can't be all optimistic */
1960
1961 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
e98bedf5
EB		 1962 NL_SET_ERR_MSG_MOD(extack,
1963 "legacy pedit isn't offloaded");
d79b6df6
OG		 1964 goto out_err;
1965 }
1966
1967 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
e98bedf5 1968 NL_SET_ERR_MSG_MOD(extack, "pedit cmd isn't offloaded");
d79b6df6
OG		 1969 goto out_err;
1970 }
1971
1972 mask = tcf_pedit_mask(a, i);
1973 val = tcf_pedit_val(a, i);
1974 offset = tcf_pedit_offset(a, i);
1975
1976 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1977 if (err)
1978 goto out_err;
1979 }
1980
1981 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1982 if (err)
1983 goto out_err;
1984
e98bedf5 1985 err = offload_pedit_fields(masks, vals, parse_attr, extack);
d79b6df6
OG		 1986 if (err < 0)
1987 goto out_dealloc_parsed_actions;
1988
1989 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1990 cmd_masks = &masks[cmd];
1991 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 1992 NL_SET_ERR_MSG_MOD(extack,
1993 "attempt to offload an unsupported field");
b3a433de 1994 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 1995 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1996 16, 1, cmd_masks, sizeof(zero_masks), true);
1997 err = -EOPNOTSUPP;
1998 goto out_dealloc_parsed_actions;
1999 }
2000 }
2001
2002 return 0;
2003
2004out_dealloc_parsed_actions:
2005 kfree(parse_attr->mod_hdr_actions);
2006out_err:
2007 return err;
2008}
2009
e98bedf5
EB		 2010static bool csum_offload_supported(struct mlx5e_priv *priv,
2011 u32 action,
2012 u32 update_flags,
2013 struct netlink_ext_ack *extack)
26c02749
OG		 2014{
2015 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2016 TCA_CSUM_UPDATE_FLAG_UDP;
2017
2018 /* The HW recalcs checksums only if re-writing headers */
2019 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2020 NL_SET_ERR_MSG_MOD(extack,
2021 "TC csum action is only offloaded with pedit");
26c02749
OG		 2022 netdev_warn(priv->netdev,
2023 "TC csum action is only offloaded with pedit\n");
2024 return false;
2025 }
2026
2027 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2028 NL_SET_ERR_MSG_MOD(extack,
2029 "can't offload TC csum action for some header/s");
26c02749
OG		 2030 netdev_warn(priv->netdev,
2031 "can't offload TC csum action for some header/s - flags %#x\n",
2032 update_flags);
2033 return false;
2034 }
2035
2036 return true;
2037}
2038
bdd66ac0 2039static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
e98bedf5
EB		 2040 struct tcf_exts *exts,
2041 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2042{
2043 const struct tc_action *a;
2044 bool modify_ip_header;
2045 LIST_HEAD(actions);
2046 u8 htype, ip_proto;
2047 void *headers_v;
2048 u16 ethertype;
2049 int nkeys, i;
2050
2051 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2052 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2053
2054 /* for non-IP we only re-write MACs, so we're okay */
2055 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2056 goto out_ok;
2057
2058 modify_ip_header = false;
244cd96a
CW		 2059 tcf_exts_for_each_action(i, a, exts) {
2060 int k;
2061
bdd66ac0
OG		 2062 if (!is_tcf_pedit(a))
2063 continue;
2064
2065 nkeys = tcf_pedit_nkeys(a);
244cd96a
CW		 2066 for (k = 0; k < nkeys; k++) {
2067 htype = tcf_pedit_htype(a, k);
bdd66ac0
OG		 2068 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
2069 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
2070 modify_ip_header = true;
2071 break;
2072 }
2073 }
2074 }
2075
2076 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2077 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2078 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2079 NL_SET_ERR_MSG_MOD(extack,
2080 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2081 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2082 return false;
2083 }
2084
2085out_ok:
2086 return true;
2087}
2088
2089static bool actions_match_supported(struct mlx5e_priv *priv,
2090 struct tcf_exts *exts,
2091 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2092 struct mlx5e_tc_flow *flow,
2093 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2094{
2095 u32 actions;
2096
2097 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2098 actions = flow->esw_attr->action;
2099 else
2100 actions = flow->nic_attr->action;
2101
7e29392e
RD		 2102 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2103 !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2104 return false;
2105
bdd66ac0 2106 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
e98bedf5
EB		 2107 return modify_header_match_supported(&parse_attr->spec, exts,
2108 extack);
bdd66ac0
OG		 2109
2110 return true;
2111}
2112
5c65c564
OG		 2113static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2114{
2115 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2116 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2117
2118 fmdev = priv->mdev;
2119 pmdev = peer_priv->mdev;
2120
59c9d35e
AH		 2121 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2122 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2123
816f6706 2124 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2125}
2126
5c40348c 2127static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae 2128 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2129 struct mlx5e_tc_flow *flow,
2130 struct netlink_ext_ack *extack)
e3a2b7ed 2131{
aa0cbbae 2132 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 2133 const struct tc_action *a;
22dc13c8 2134 LIST_HEAD(actions);
1cab1cd7 2135 u32 action = 0;
244cd96a 2136 int err, i;
e3a2b7ed 2137
3bcc0cec 2138 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 2139 return -EINVAL;
2140
3bc4b7bf 2141 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2142
244cd96a 2143 tcf_exts_for_each_action(i, a, exts) {
e3a2b7ed 2144 if (is_tcf_gact_shot(a)) {
1cab1cd7 2145 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2146 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2147 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2148 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 2149 continue;
2150 }
2151
2f4fe4ca
OG		 2152 if (is_tcf_pedit(a)) {
2153 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
e98bedf5 2154 parse_attr, extack);
2f4fe4ca
OG		 2155 if (err)
2156 return err;
2157
1cab1cd7
OG		 2158 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2159 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2f4fe4ca
OG		 2160 continue;
2161 }
2162
26c02749 2163 if (is_tcf_csum(a)) {
1cab1cd7 2164 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2165 tcf_csum_update_flags(a),
2166 extack))
26c02749
OG		 2167 continue;
2168
2169 return -EOPNOTSUPP;
2170 }
2171
5c65c564
OG		 2172 if (is_tcf_mirred_egress_redirect(a)) {
2173 struct net_device *peer_dev = tcf_mirred_dev(a);
2174
2175 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2176 same_hw_devs(priv, netdev_priv(peer_dev))) {
2177 parse_attr->mirred_ifindex = peer_dev->ifindex;
2178 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 2179 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2180 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2181 } else {
e98bedf5
EB		 2182 NL_SET_ERR_MSG_MOD(extack,
2183 "device is not on same HW, can't offload");
5c65c564
OG		 2184 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2185 peer_dev->name);
2186 return -EINVAL;
2187 }
2188 continue;
2189 }
2190
e3a2b7ed
AV		 2191 if (is_tcf_skbedit_mark(a)) {
2192 u32 mark = tcf_skbedit_mark(a);
2193
2194 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2195 NL_SET_ERR_MSG_MOD(extack,
2196 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2197 return -EINVAL;
2198 }
2199
3bc4b7bf 2200 attr->flow_tag = mark;
1cab1cd7 2201 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 2202 continue;
2203 }
2204
2205 return -EINVAL;
2206 }
2207
1cab1cd7 2208 attr->action = action;
e98bedf5 2209 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2210 return -EOPNOTSUPP;
2211
e3a2b7ed
AV		 2212 return 0;
2213}
2214
76f7444d
OG		 2215static inline int cmp_encap_info(struct ip_tunnel_key *a,
2216 struct ip_tunnel_key *b)
a54e20b4
HHZ		 2217{
2218 return memcmp(a, b, sizeof(*a));
2219}
2220
76f7444d 2221static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2222{
76f7444d 2223 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2224}
2225
2226static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
2227 struct net_device *mirred_dev,
2228 struct net_device **out_dev,
2229 struct flowi4 *fl4,
2230 struct neighbour **out_n,
6360cd62 2231 u8 *out_ttl)
a54e20b4 2232{
3e621b19 2233 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5ed99fb4 2234 struct mlx5e_rep_priv *uplink_rpriv;
a54e20b4
HHZ		 2235 struct rtable *rt;
2236 struct neighbour *n = NULL;
a54e20b4
HHZ		 2237
2238#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 2239 int ret;
2240
a54e20b4 2241 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 2242 ret = PTR_ERR_OR_ZERO(rt);
2243 if (ret)
2244 return ret;
a54e20b4
HHZ		 2245#else
2246 return -EOPNOTSUPP;
2247#endif
a4b97ab4 2248 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3e621b19
HHZ		 2249 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2250 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
5ed99fb4 2251 *out_dev = uplink_rpriv->netdev;
3e621b19
HHZ		 2252 else
2253 *out_dev = rt->dst.dev;
a54e20b4 2254
6360cd62
OG		 2255 if (!(*out_ttl))
2256 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 2257 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
2258 ip_rt_put(rt);
2259 if (!n)
2260 return -ENOMEM;
2261
2262 *out_n = n;
a54e20b4
HHZ		 2263 return 0;
2264}
2265
b1d90e6b
RL		 2266static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2267 struct net_device *peer_netdev)
2268{
2269 struct mlx5e_priv *peer_priv;
2270
2271 peer_priv = netdev_priv(peer_netdev);
2272
2273 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2274 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2275 same_hw_devs(priv, peer_priv) &&
2276 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2277 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2278}
2279
ce99f6b9
OG		 2280static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
2281 struct net_device *mirred_dev,
2282 struct net_device **out_dev,
2283 struct flowi6 *fl6,
2284 struct neighbour **out_n,
6360cd62 2285 u8 *out_ttl)
ce99f6b9
OG		 2286{
2287 struct neighbour *n = NULL;
2288 struct dst_entry *dst;
2289
2290#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
74bd5d56 2291 struct mlx5e_rep_priv *uplink_rpriv;
ce99f6b9
OG		 2292 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2293 int ret;
2294
08820528
PB		 2295 ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
2296 fl6);
2297 if (ret < 0)
ce99f6b9 2298 return ret;
ce99f6b9 2299
6360cd62
OG		 2300 if (!(*out_ttl))
2301 *out_ttl = ip6_dst_hoplimit(dst);
ce99f6b9 2302
a4b97ab4 2303 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ce99f6b9
OG		 2304 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2305 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
5ed99fb4 2306 *out_dev = uplink_rpriv->netdev;
ce99f6b9
OG		 2307 else
2308 *out_dev = dst->dev;
2309#else
2310 return -EOPNOTSUPP;
2311#endif
2312
2313 n = dst_neigh_lookup(dst, &fl6->daddr);
2314 dst_release(dst);
2315 if (!n)
2316 return -ENOMEM;
2317
2318 *out_n = n;
2319 return 0;
2320}
2321
32f3671f
OG		 2322static void gen_vxlan_header_ipv4(struct net_device *out_dev,
2323 char buf[], int encap_size,
2324 unsigned char h_dest[ETH_ALEN],
f35f800d 2325 u8 tos, u8 ttl,
32f3671f
OG		 2326 __be32 daddr,
2327 __be32 saddr,
2328 __be16 udp_dst_port,
2329 __be32 vx_vni)
a54e20b4 2330{
a54e20b4
HHZ		 2331 struct ethhdr *eth = (struct ethhdr *)buf;
2332 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
2333 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
2334 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2335
2336 memset(buf, 0, encap_size);
2337
2338 ether_addr_copy(eth->h_dest, h_dest);
2339 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2340 eth->h_proto = htons(ETH_P_IP);
2341
2342 ip->daddr = daddr;
2343 ip->saddr = saddr;
2344
f35f800d 2345 ip->tos = tos;
a54e20b4
HHZ		 2346 ip->ttl = ttl;
2347 ip->protocol = IPPROTO_UDP;
2348 ip->version = 0x4;
2349 ip->ihl = 0x5;
2350
2351 udp->dest = udp_dst_port;
2352 vxh->vx_flags = VXLAN_HF_VNI;
2353 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 2354}
2355
225aabaf
OG		 2356static void gen_vxlan_header_ipv6(struct net_device *out_dev,
2357 char buf[], int encap_size,
2358 unsigned char h_dest[ETH_ALEN],
f35f800d 2359 u8 tos, u8 ttl,
225aabaf
OG		 2360 struct in6_addr *daddr,
2361 struct in6_addr *saddr,
2362 __be16 udp_dst_port,
2363 __be32 vx_vni)
ce99f6b9 2364{
ce99f6b9
OG		 2365 struct ethhdr *eth = (struct ethhdr *)buf;
2366 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
2367 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
2368 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2369
2370 memset(buf, 0, encap_size);
2371
2372 ether_addr_copy(eth->h_dest, h_dest);
2373 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2374 eth->h_proto = htons(ETH_P_IPV6);
2375
f35f800d 2376 ip6_flow_hdr(ip6h, tos, 0);
ce99f6b9
OG		 2377 /* the HW fills up ipv6 payload len */
2378 ip6h->nexthdr = IPPROTO_UDP;
2379 ip6h->hop_limit = ttl;
2380 ip6h->daddr = *daddr;
2381 ip6h->saddr = *saddr;
2382
2383 udp->dest = udp_dst_port;
2384 vxh->vx_flags = VXLAN_HF_VNI;
2385 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 2386}
2387
a54e20b4
HHZ		 2388static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
2389 struct net_device *mirred_dev,
1a8552bd 2390 struct mlx5e_encap_entry *e)
a54e20b4
HHZ		 2391{
2392 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 2393 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 2394 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2395 struct net_device *out_dev;
a42485eb 2396 struct neighbour *n = NULL;
a54e20b4 2397 struct flowi4 fl4 = {};
f35f800d 2398 u8 nud_state, tos, ttl;
a54e20b4 2399 char *encap_header;
6360cd62 2400 int err;
32f3671f
OG		 2401
2402 if (max_encap_size < ipv4_encap_size) {
2403 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2404 ipv4_encap_size, max_encap_size);
2405 return -EOPNOTSUPP;
2406 }
a54e20b4 2407
32f3671f 2408 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 2409 if (!encap_header)
2410 return -ENOMEM;
2411
2412 switch (e->tunnel_type) {
60786f09 2413 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
a54e20b4 2414 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 2415 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 2416 break;
2417 default:
2418 err = -EOPNOTSUPP;
ace74321 2419 goto free_encap;
a54e20b4 2420 }
6360cd62 2421
f35f800d
OG		 2422 tos = tun_key->tos;
2423 ttl = tun_key->ttl;
6360cd62 2424
9a941117 2425 fl4.flowi4_tos = tun_key->tos;
76f7444d 2426 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 2427 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 2428
1a8552bd 2429 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 2430 &fl4, &n, &ttl);
a54e20b4 2431 if (err)
ace74321 2432 goto free_encap;
a54e20b4 2433
232c0013
HHZ		 2434 /* used by mlx5e_detach_encap to lookup a neigh hash table
2435 * entry in the neigh hash table when a user deletes a rule
2436 */
2437 e->m_neigh.dev = n->dev;
f6dfb4c3 2438 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2439 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2440 e->out_dev = out_dev;
2441
2442 /* It's importent to add the neigh to the hash table before checking
2443 * the neigh validity state. So if we'll get a notification, in case the
2444 * neigh changes it's validity state, we would find the relevant neigh
2445 * in the hash.
2446 */
2447 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2448 if (err)
ace74321 2449 goto free_encap;
232c0013 2450
033354d5
HHZ		 2451 read_lock_bh(&n->lock);
2452 nud_state = n->nud_state;
2453 ether_addr_copy(e->h_dest, n->ha);
2454 read_unlock_bh(&n->lock);
2455
a54e20b4 2456 switch (e->tunnel_type) {
60786f09 2457 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
1a8552bd 2458 gen_vxlan_header_ipv4(out_dev, encap_header,
f35f800d 2459 ipv4_encap_size, e->h_dest, tos, ttl,
32f3671f
OG		 2460 fl4.daddr,
2461 fl4.saddr, tun_key->tp_dst,
2462 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 2463 break;
2464 default:
2465 err = -EOPNOTSUPP;
232c0013
HHZ		 2466 goto destroy_neigh_entry;
2467 }
2468 e->encap_size = ipv4_encap_size;
2469 e->encap_header = encap_header;
2470
2471 if (!(nud_state & NUD_VALID)) {
2472 neigh_event_send(n, NULL);
27902f08
WY		 2473 err = -EAGAIN;
2474 goto out;
a54e20b4
HHZ		 2475 }
2476
60786f09
MB		 2477 err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
2478 ipv4_encap_size, encap_header,
31ca3648 2479 MLX5_FLOW_NAMESPACE_FDB,
60786f09 2480 &e->encap_id);
232c0013
HHZ		 2481 if (err)
2482 goto destroy_neigh_entry;
2483
2484 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2485 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2486 neigh_release(n);
2487 return err;
2488
2489destroy_neigh_entry:
2490 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2491free_encap:
a54e20b4 2492 kfree(encap_header);
ace74321 2493out:
232c0013
HHZ		 2494 if (n)
2495 neigh_release(n);
a54e20b4
HHZ		 2496 return err;
2497}
2498
ce99f6b9
OG		 2499static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2500 struct net_device *mirred_dev,
1a8552bd 2501 struct mlx5e_encap_entry *e)
ce99f6b9
OG		 2502{
2503 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 2504 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 2505 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2506 struct net_device *out_dev;
ce99f6b9
OG		 2507 struct neighbour *n = NULL;
2508 struct flowi6 fl6 = {};
f35f800d 2509 u8 nud_state, tos, ttl;
ce99f6b9 2510 char *encap_header;
6360cd62 2511 int err;
ce99f6b9 2512
225aabaf
OG		 2513 if (max_encap_size < ipv6_encap_size) {
2514 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2515 ipv6_encap_size, max_encap_size);
2516 return -EOPNOTSUPP;
2517 }
ce99f6b9 2518
225aabaf 2519 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 2520 if (!encap_header)
2521 return -ENOMEM;
2522
2523 switch (e->tunnel_type) {
60786f09 2524 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
ce99f6b9
OG		 2525 fl6.flowi6_proto = IPPROTO_UDP;
2526 fl6.fl6_dport = tun_key->tp_dst;
2527 break;
2528 default:
2529 err = -EOPNOTSUPP;
ace74321 2530 goto free_encap;
ce99f6b9
OG		 2531 }
2532
f35f800d
OG		 2533 tos = tun_key->tos;
2534 ttl = tun_key->ttl;
6360cd62 2535
ce99f6b9
OG		 2536 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2537 fl6.daddr = tun_key->u.ipv6.dst;
2538 fl6.saddr = tun_key->u.ipv6.src;
2539
1a8552bd 2540 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG		 2541 &fl6, &n, &ttl);
2542 if (err)
ace74321 2543 goto free_encap;
ce99f6b9 2544
232c0013
HHZ		 2545 /* used by mlx5e_detach_encap to lookup a neigh hash table
2546 * entry in the neigh hash table when a user deletes a rule
2547 */
2548 e->m_neigh.dev = n->dev;
f6dfb4c3 2549 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2550 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2551 e->out_dev = out_dev;
2552
2553 /* It's importent to add the neigh to the hash table before checking
2554 * the neigh validity state. So if we'll get a notification, in case the
2555 * neigh changes it's validity state, we would find the relevant neigh
2556 * in the hash.
2557 */
2558 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2559 if (err)
ace74321 2560 goto free_encap;
232c0013 2561
033354d5
HHZ		 2562 read_lock_bh(&n->lock);
2563 nud_state = n->nud_state;
2564 ether_addr_copy(e->h_dest, n->ha);
2565 read_unlock_bh(&n->lock);
2566
ce99f6b9 2567 switch (e->tunnel_type) {
60786f09 2568 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
1a8552bd 2569 gen_vxlan_header_ipv6(out_dev, encap_header,
f35f800d 2570 ipv6_encap_size, e->h_dest, tos, ttl,
225aabaf
OG		 2571 &fl6.daddr,
2572 &fl6.saddr, tun_key->tp_dst,
2573 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 2574 break;
2575 default:
2576 err = -EOPNOTSUPP;
232c0013
HHZ		 2577 goto destroy_neigh_entry;
2578 }
2579
2580 e->encap_size = ipv6_encap_size;
2581 e->encap_header = encap_header;
2582
2583 if (!(nud_state & NUD_VALID)) {
2584 neigh_event_send(n, NULL);
27902f08
WY		 2585 err = -EAGAIN;
2586 goto out;
ce99f6b9
OG		 2587 }
2588
60786f09
MB		 2589 err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
2590 ipv6_encap_size, encap_header,
31ca3648 2591 MLX5_FLOW_NAMESPACE_FDB,
60786f09 2592 &e->encap_id);
232c0013
HHZ		 2593 if (err)
2594 goto destroy_neigh_entry;
2595
2596 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2597 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2598 neigh_release(n);
2599 return err;
2600
2601destroy_neigh_entry:
2602 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2603free_encap:
ce99f6b9 2604 kfree(encap_header);
ace74321 2605out:
232c0013
HHZ		 2606 if (n)
2607 neigh_release(n);
ce99f6b9
OG		 2608 return err;
2609}
2610
a54e20b4
HHZ		 2611static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2612 struct ip_tunnel_info *tun_info,
2613 struct net_device *mirred_dev,
45247bf2 2614 struct net_device **encap_dev,
e98bedf5
EB		 2615 struct mlx5e_tc_flow *flow,
2616 struct netlink_ext_ack *extack)
a54e20b4
HHZ		 2617{
2618 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2619 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2 2620 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2621 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2622 struct mlx5e_encap_entry *e;
45247bf2 2623 int tunnel_type, err = 0;
a54e20b4
HHZ		 2624 uintptr_t hash_key;
2625 bool found = false;
a54e20b4 2626
2fcd82e9 2627 /* udp dst port must be set */
a54e20b4 2628 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 2629 goto vxlan_encap_offload_err;
a54e20b4 2630
cd377663 2631 /* setting udp src port isn't supported */
2fcd82e9
OG		 2632 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2633vxlan_encap_offload_err:
e98bedf5
EB		 2634 NL_SET_ERR_MSG_MOD(extack,
2635 "must set udp dst port and not set udp src port");
2fcd82e9
OG		 2636 netdev_warn(priv->netdev,
2637 "must set udp dst port and not set udp src port\n");
cd377663 2638 return -EOPNOTSUPP;
2fcd82e9 2639 }
cd377663 2640
a3e67366 2641 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->tp_dst)) &&
a54e20b4 2642 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
60786f09 2643 tunnel_type = MLX5_REFORMAT_TYPE_L2_TO_VXLAN;
a54e20b4 2644 } else {
e98bedf5
EB		 2645 NL_SET_ERR_MSG_MOD(extack,
2646 "port isn't an offloaded vxlan udp dport");
2fcd82e9
OG		 2647 netdev_warn(priv->netdev,
2648 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 2649 return -EOPNOTSUPP;
2650 }
2651
76f7444d 2652 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2653
2654 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2655 encap_hlist, hash_key) {
76f7444d 2656 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2657 found = true;
2658 break;
2659 }
2660 }
2661
b2812089 2662 /* must verify if encap is valid or not */
45247bf2
OG		 2663 if (found)
2664 goto attach_flow;
a54e20b4
HHZ		 2665
2666 e = kzalloc(sizeof(*e), GFP_KERNEL);
2667 if (!e)
2668 return -ENOMEM;
2669
76f7444d 2670 e->tun_info = *tun_info;
a54e20b4
HHZ		 2671 e->tunnel_type = tunnel_type;
2672 INIT_LIST_HEAD(&e->flows);
2673
ce99f6b9 2674 if (family == AF_INET)
1a8552bd 2675 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2676 else if (family == AF_INET6)
1a8552bd 2677 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2678
232c0013 2679 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2680 goto out_err;
2681
a54e20b4
HHZ		 2682 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2683
45247bf2
OG		 2684attach_flow:
2685 list_add(&flow->encap, &e->flows);
2686 *encap_dev = e->out_dev;
232c0013
HHZ		 2687 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2688 attr->encap_id = e->encap_id;
b2812089
VB		 2689 else
2690 err = -EAGAIN;
45247bf2 2691
232c0013 2692 return err;
a54e20b4
HHZ		 2693
2694out_err:
2695 kfree(e);
2696 return err;
2697}
2698
1482bd3d
JL		 2699static int parse_tc_vlan_action(struct mlx5e_priv *priv,
2700 const struct tc_action *a,
2701 struct mlx5_esw_flow_attr *attr,
2702 u32 *action)
2703{
cc495188
JL		 2704 u8 vlan_idx = attr->total_vlan;
2705
2706 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2707 return -EOPNOTSUPP;
2708
1482bd3d 2709 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
cc495188
JL		 2710 if (vlan_idx) {
2711 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2712 MLX5_FS_VLAN_DEPTH))
2713 return -EOPNOTSUPP;
2714
2715 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2716 } else {
2717 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2718 }
1482bd3d 2719 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
cc495188
JL		 2720 attr->vlan_vid[vlan_idx] = tcf_vlan_push_vid(a);
2721 attr->vlan_prio[vlan_idx] = tcf_vlan_push_prio(a);
2722 attr->vlan_proto[vlan_idx] = tcf_vlan_push_proto(a);
2723 if (!attr->vlan_proto[vlan_idx])
2724 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2725
2726 if (vlan_idx) {
2727 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2728 MLX5_FS_VLAN_DEPTH))
2729 return -EOPNOTSUPP;
2730
2731 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2732 } else {
2733 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
2734 (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2735 tcf_vlan_push_prio(a)))
2736 return -EOPNOTSUPP;
2737
2738 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d
JL		 2739 }
2740 } else { /* action is TCA_VLAN_ACT_MODIFY */
2741 return -EOPNOTSUPP;
2742 }
2743
cc495188
JL		 2744 attr->total_vlan = vlan_idx + 1;
2745
1482bd3d
JL		 2746 return 0;
2747}
2748
03a9d11e 2749static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 2750 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2751 struct mlx5e_tc_flow *flow,
2752 struct netlink_ext_ack *extack)
03a9d11e 2753{
ecf5bb79 2754 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2755 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 2756 struct ip_tunnel_info *info = NULL;
03a9d11e 2757 const struct tc_action *a;
22dc13c8 2758 LIST_HEAD(actions);
a54e20b4 2759 bool encap = false;
1cab1cd7 2760 u32 action = 0;
244cd96a 2761 int err, i;
03a9d11e 2762
3bcc0cec 2763 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 2764 return -EINVAL;
2765
1d447a39 2766 attr->in_rep = rpriv->rep;
10ff5359 2767 attr->in_mdev = priv->mdev;
03a9d11e 2768
244cd96a 2769 tcf_exts_for_each_action(i, a, exts) {
03a9d11e 2770 if (is_tcf_gact_shot(a)) {
1cab1cd7
OG		 2771 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2772 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 2773 continue;
2774 }
2775
d7e75a32
OG		 2776 if (is_tcf_pedit(a)) {
2777 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
e98bedf5 2778 parse_attr, extack);
d7e75a32
OG		 2779 if (err)
2780 return err;
2781
1cab1cd7 2782 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
592d3651 2783 attr->mirror_count = attr->out_count;
d7e75a32
OG		 2784 continue;
2785 }
2786
26c02749 2787 if (is_tcf_csum(a)) {
1cab1cd7 2788 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2789 tcf_csum_update_flags(a),
2790 extack))
26c02749
OG		 2791 continue;
2792
2793 return -EOPNOTSUPP;
2794 }
2795
592d3651 2796 if (is_tcf_mirred_egress_redirect(a) || is_tcf_mirred_egress_mirror(a)) {
03a9d11e 2797 struct mlx5e_priv *out_priv;
592d3651 2798 struct net_device *out_dev;
03a9d11e 2799
9f8a739e 2800 out_dev = tcf_mirred_dev(a);
03a9d11e 2801
592d3651 2802 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2803 NL_SET_ERR_MSG_MOD(extack,
2804 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2805 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2806 attr->out_count);
2807 return -EOPNOTSUPP;
2808 }
2809
a54e20b4 2810 if (switchdev_port_same_parent_id(priv->netdev,
b1d90e6b
RL		 2811 out_dev) ||
2812 is_merged_eswitch_dev(priv, out_dev)) {
1cab1cd7
OG		 2813 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2814 MLX5_FLOW_CONTEXT_ACTION_COUNT;
a54e20b4 2815 out_priv = netdev_priv(out_dev);
1d447a39 2816 rpriv = out_priv->ppriv;
592d3651
CM		 2817 attr->out_rep[attr->out_count] = rpriv->rep;
2818 attr->out_mdev[attr->out_count++] = out_priv->mdev;
a54e20b4 2819 } else if (encap) {
9f8a739e 2820 parse_attr->mirred_ifindex = out_dev->ifindex;
3c37745e
OG		 2821 parse_attr->tun_info = *info;
2822 attr->parse_attr = parse_attr;
60786f09 2823 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
1cab1cd7
OG		 2824 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2825 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3c37745e 2826 /* attr->out_rep is resolved when we handle encap */
a54e20b4 2827 } else {
e98bedf5
EB		 2828 NL_SET_ERR_MSG_MOD(extack,
2829 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 2830 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2831 priv->netdev->name, out_dev->name);
2832 return -EINVAL;
2833 }
a54e20b4
HHZ		 2834 continue;
2835 }
03a9d11e 2836
a54e20b4
HHZ		 2837 if (is_tcf_tunnel_set(a)) {
2838 info = tcf_tunnel_info(a);
2839 if (info)
2840 encap = true;
2841 else
2842 return -EOPNOTSUPP;
592d3651 2843 attr->mirror_count = attr->out_count;
03a9d11e
OG		 2844 continue;
2845 }
2846
8b32580d 2847 if (is_tcf_vlan(a)) {
1482bd3d
JL		 2848 err = parse_tc_vlan_action(priv, a, attr, &action);
2849
2850 if (err)
2851 return err;
2852
592d3651 2853 attr->mirror_count = attr->out_count;
8b32580d
OG		 2854 continue;
2855 }
2856
bbd00f7e 2857 if (is_tcf_tunnel_release(a)) {
1cab1cd7 2858 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bbd00f7e
HHZ		 2859 continue;
2860 }
2861
03a9d11e
OG		 2862 return -EINVAL;
2863 }
bdd66ac0 2864
1cab1cd7 2865 attr->action = action;
e98bedf5 2866 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2867 return -EOPNOTSUPP;
2868
592d3651 2869 if (attr->out_count > 1 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 2870 NL_SET_ERR_MSG_MOD(extack,
2871 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 2872 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2873 return -EOPNOTSUPP;
2874 }
2875
31c8eba5 2876 return 0;
03a9d11e
OG		 2877}
2878
60bd4af8
OG		 2879static void get_flags(int flags, u8 *flow_flags)
2880{
2881 u8 __flow_flags = 0;
2882
2883 if (flags & MLX5E_TC_INGRESS)
2884 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2885 if (flags & MLX5E_TC_EGRESS)
2886 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
2887
2888 *flow_flags = __flow_flags;
2889}
2890
05866c82
OG		 2891static const struct rhashtable_params tc_ht_params = {
2892 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2893 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2894 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2895 .automatic_shrinking = true,
2896};
2897
2898static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv)
2899{
655dc3d2
OG		 2900 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2901 struct mlx5e_rep_priv *uplink_rpriv;
2902
2903 if (MLX5_VPORT_MANAGER(priv->mdev) && esw->mode == SRIOV_OFFLOADS) {
2904 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2905 return &uplink_rpriv->tc_ht;
2906 } else
2907 return &priv->fs.tc.ht;
05866c82
OG		 2908}
2909
5fd9fc4e 2910int mlx5e_configure_flower(struct mlx5e_priv *priv,
60bd4af8 2911 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 2912{
e98bedf5 2913 struct netlink_ext_ack *extack = f->common.extack;
3bc4b7bf 2914 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 2915 struct mlx5e_tc_flow_parse_attr *parse_attr;
05866c82 2916 struct rhashtable *tc_ht = get_tc_ht(priv);
3bc4b7bf
OG		 2917 struct mlx5e_tc_flow *flow;
2918 int attr_size, err = 0;
65ba8fb7 2919 u8 flow_flags = 0;
e3a2b7ed 2920
60bd4af8
OG		 2921 get_flags(flags, &flow_flags);
2922
8f8ae895
OG		 2923 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2924 if (flow) {
e98bedf5
EB		 2925 NL_SET_ERR_MSG_MOD(extack,
2926 "flow cookie already exists, ignoring");
8f8ae895
OG		 2927 netdev_warn_once(priv->netdev, "flow cookie %lx already exists, ignoring\n", f->cookie);
2928 return 0;
2929 }
2930
65ba8fb7 2931 if (esw && esw->mode == SRIOV_OFFLOADS) {
60bd4af8 2932 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
65ba8fb7 2933 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf 2934 } else {
60bd4af8 2935 flow_flags |= MLX5E_TC_FLOW_NIC;
3bc4b7bf 2936 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 2937 }
e3a2b7ed 2938
65ba8fb7 2939 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2940 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2941 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2942 err = -ENOMEM;
2943 goto err_free;
2944 }
2945
2946 flow->cookie = f->cookie;
65ba8fb7 2947 flow->flags = flow_flags;
655dc3d2 2948 flow->priv = priv;
e3a2b7ed 2949
17091853 2950 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV		 2951 if (err < 0)
2952 goto err_free;
2953
65ba8fb7 2954 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
e98bedf5
EB		 2955 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow,
2956 extack);
adb4c123 2957 if (err < 0)
3c37745e 2958 goto err_free;
c83954ab 2959 err = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow, extack);
adb4c123 2960 } else {
e98bedf5
EB		 2961 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow,
2962 extack);
adb4c123
OG		 2963 if (err < 0)
2964 goto err_free;
c83954ab 2965 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
adb4c123 2966 }
e3a2b7ed 2967
c83954ab
RL		 2968 if (err && err != -EAGAIN)
2969 goto err_free;
e3a2b7ed 2970
3c37745e
OG		 2971 if (err != -EAGAIN)
2972 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2973
af1607c3 2974 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
60786f09
MB		 2975 !(flow->esw_attr->action &
2976 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT))
af1607c3
JL		 2977 kvfree(parse_attr);
2978
05866c82 2979 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
af1607c3
JL		 2980 if (err) {
2981 mlx5e_tc_del_flow(priv, flow);
2982 kfree(flow);
2983 }
5c40348c 2984
232c0013 2985 return err;
e3a2b7ed 2986
e3a2b7ed 2987err_free:
17091853 2988 kvfree(parse_attr);
232c0013 2989 kfree(flow);
e3a2b7ed
AV		 2990 return err;
2991}
2992
8f8ae895
OG		 2993#define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
2994#define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
2995
2996static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
2997{
2998 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
2999 return true;
3000
3001 return false;
3002}
3003
e3a2b7ed 3004int mlx5e_delete_flower(struct mlx5e_priv *priv,
60bd4af8 3005 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 3006{
05866c82 3007 struct rhashtable *tc_ht = get_tc_ht(priv);
e3a2b7ed 3008 struct mlx5e_tc_flow *flow;
e3a2b7ed 3009
05866c82 3010 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3011 if (!flow || !same_flow_direction(flow, flags))
e3a2b7ed
AV		 3012 return -EINVAL;
3013
05866c82 3014 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
e3a2b7ed 3015
961e8979 3016 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 3017
3018 kfree(flow);
3019
3020 return 0;
3021}
3022
aad7e08d 3023int mlx5e_stats_flower(struct mlx5e_priv *priv,
60bd4af8 3024 struct tc_cls_flower_offload *f, int flags)
aad7e08d 3025{
05866c82 3026 struct rhashtable *tc_ht = get_tc_ht(priv);
aad7e08d 3027 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 3028 struct mlx5_fc *counter;
3029 u64 bytes;
3030 u64 packets;
3031 u64 lastuse;
3032
05866c82 3033 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3034 if (!flow || !same_flow_direction(flow, flags))
aad7e08d
AV		 3035 return -EINVAL;
3036
0b67a38f
HHZ		 3037 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
3038 return 0;
3039
b8aee822 3040 counter = mlx5e_tc_get_counter(flow);
aad7e08d
AV		 3041 if (!counter)
3042 return 0;
3043
3044 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3045
d897a638 3046 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 3047
aad7e08d
AV		 3048 return 0;
3049}
3050
4d8fcf21
AH		 3051static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3052 struct mlx5e_priv *peer_priv)
3053{
3054 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3055 struct mlx5e_hairpin_entry *hpe;
3056 u16 peer_vhca_id;
3057 int bkt;
3058
3059 if (!same_hw_devs(priv, peer_priv))
3060 return;
3061
3062 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3063
3064 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3065 if (hpe->peer_vhca_id == peer_vhca_id)
3066 hpe->hp->pair->peer_gone = true;
3067 }
3068}
3069
3070static int mlx5e_tc_netdev_event(struct notifier_block *this,
3071 unsigned long event, void *ptr)
3072{
3073 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3074 struct mlx5e_flow_steering *fs;
3075 struct mlx5e_priv *peer_priv;
3076 struct mlx5e_tc_table *tc;
3077 struct mlx5e_priv *priv;
3078
3079 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3080 event != NETDEV_UNREGISTER ||
3081 ndev->reg_state == NETREG_REGISTERED)
3082 return NOTIFY_DONE;
3083
3084 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3085 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3086 priv = container_of(fs, struct mlx5e_priv, fs);
3087 peer_priv = netdev_priv(ndev);
3088 if (priv == peer_priv ||
3089 !(priv->netdev->features & NETIF_F_HW_TC))
3090 return NOTIFY_DONE;
3091
3092 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3093
3094 return NOTIFY_DONE;
3095}
3096
655dc3d2 3097int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3098{
acff797c 3099 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3100 int err;
e8f887ac 3101
11c9c548 3102 hash_init(tc->mod_hdr_tbl);
5c65c564 3103 hash_init(tc->hairpin_tbl);
11c9c548 3104
4d8fcf21
AH		 3105 err = rhashtable_init(&tc->ht, &tc_ht_params);
3106 if (err)
3107 return err;
3108
3109 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3110 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3111 tc->netdevice_nb.notifier_call = NULL;
3112 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3113 }
3114
3115 return err;
e8f887ac
AV		 3116}
3117
3118static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3119{
3120 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3121 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3122
961e8979 3123 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3124 kfree(flow);
3125}
3126
655dc3d2 3127void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3128{
acff797c 3129 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3130
4d8fcf21
AH		 3131 if (tc->netdevice_nb.notifier_call)
3132 unregister_netdevice_notifier(&tc->netdevice_nb);
3133
655dc3d2 3134 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 3135
acff797c
MG		 3136 if (!IS_ERR_OR_NULL(tc->t)) {
3137 mlx5_destroy_flow_table(tc->t);
3138 tc->t = NULL;
e8f887ac
AV		 3139 }
3140}
655dc3d2
OG		 3141
3142int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3143{
3144 return rhashtable_init(tc_ht, &tc_ht_params);
3145}
3146
3147void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3148{
3149 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3150}
01252a27
OG		 3151
3152int mlx5e_tc_num_filters(struct mlx5e_priv *priv)
3153{
3154 struct rhashtable *tc_ht = get_tc_ht(priv);
3155
3156 return atomic_read(&tc_ht->nelems);
3157}
Linux 6.x block layer and io_uring tree(s)