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Merge tag 'mlx5-updates-2018-05-17' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
bbd00f7e 53#include "vxlan.h"
3f6d08d1 54#include "fs_core.h"
e8f887ac 55
3bc4b7bf
OG		 56struct mlx5_nic_flow_attr {
57 u32 action;
58 u32 flow_tag;
2f4fe4ca 59 u32 mod_hdr_id;
5c65c564 60 u32 hairpin_tirn;
38aa51c1 61 u8 match_level;
3f6d08d1 62 struct mlx5_flow_table *hairpin_ft;
3bc4b7bf
OG		 63};
64
65ba8fb7
OG		 65enum {
66 MLX5E_TC_FLOW_ESWITCH = BIT(0),
3bc4b7bf 67 MLX5E_TC_FLOW_NIC = BIT(1),
0b67a38f 68 MLX5E_TC_FLOW_OFFLOADED = BIT(2),
5c65c564 69 MLX5E_TC_FLOW_HAIRPIN = BIT(3),
3f6d08d1 70 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(4),
65ba8fb7
OG		 71};
72
e8f887ac
AV		 73struct mlx5e_tc_flow {
74 struct rhash_head node;
75 u64 cookie;
65ba8fb7 76 u8 flags;
74491de9 77 struct mlx5_flow_handle *rule;
11c9c548
OG		 78 struct list_head encap; /* flows sharing the same encap ID */
79 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 80 struct list_head hairpin; /* flows sharing the same hairpin */
3bc4b7bf
OG		 81 union {
82 struct mlx5_esw_flow_attr esw_attr[0];
83 struct mlx5_nic_flow_attr nic_attr[0];
84 };
e8f887ac
AV		 85};
86
17091853 87struct mlx5e_tc_flow_parse_attr {
3c37745e 88 struct ip_tunnel_info tun_info;
17091853 89 struct mlx5_flow_spec spec;
d79b6df6
OG		 90 int num_mod_hdr_actions;
91 void *mod_hdr_actions;
3c37745e 92 int mirred_ifindex;
17091853
OG		 93};
94
a54e20b4
HHZ		 95enum {
96 MLX5_HEADER_TYPE_VXLAN = 0x0,
97 MLX5_HEADER_TYPE_NVGRE = 0x1,
98};
99
acff797c 100#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 101#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 102
77ab67b7
OG		 103struct mlx5e_hairpin {
104 struct mlx5_hairpin *pair;
105
106 struct mlx5_core_dev *func_mdev;
3f6d08d1 107 struct mlx5e_priv *func_priv;
77ab67b7
OG		 108 u32 tdn;
109 u32 tirn;
3f6d08d1
OG		 110
111 int num_channels;
112 struct mlx5e_rqt indir_rqt;
113 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
114 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 115};
116
5c65c564
OG		 117struct mlx5e_hairpin_entry {
118 /* a node of a hash table which keeps all the hairpin entries */
119 struct hlist_node hairpin_hlist;
120
121 /* flows sharing the same hairpin */
122 struct list_head flows;
123
d8822868 124 u16 peer_vhca_id;
106be53b 125 u8 prio;
5c65c564
OG		 126 struct mlx5e_hairpin *hp;
127};
128
11c9c548
OG		 129struct mod_hdr_key {
130 int num_actions;
131 void *actions;
132};
133
134struct mlx5e_mod_hdr_entry {
135 /* a node of a hash table which keeps all the mod_hdr entries */
136 struct hlist_node mod_hdr_hlist;
137
138 /* flows sharing the same mod_hdr entry */
139 struct list_head flows;
140
141 struct mod_hdr_key key;
142
143 u32 mod_hdr_id;
144};
145
146#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
147
148static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
149{
150 return jhash(key->actions,
151 key->num_actions * MLX5_MH_ACT_SZ, 0);
152}
153
154static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
155 struct mod_hdr_key *b)
156{
157 if (a->num_actions != b->num_actions)
158 return 1;
159
160 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
161}
162
163static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
164 struct mlx5e_tc_flow *flow,
165 struct mlx5e_tc_flow_parse_attr *parse_attr)
166{
167 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
168 int num_actions, actions_size, namespace, err;
169 struct mlx5e_mod_hdr_entry *mh;
170 struct mod_hdr_key key;
171 bool found = false;
172 u32 hash_key;
173
174 num_actions = parse_attr->num_mod_hdr_actions;
175 actions_size = MLX5_MH_ACT_SZ * num_actions;
176
177 key.actions = parse_attr->mod_hdr_actions;
178 key.num_actions = num_actions;
179
180 hash_key = hash_mod_hdr_info(&key);
181
182 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
183 namespace = MLX5_FLOW_NAMESPACE_FDB;
184 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
185 mod_hdr_hlist, hash_key) {
186 if (!cmp_mod_hdr_info(&mh->key, &key)) {
187 found = true;
188 break;
189 }
190 }
191 } else {
192 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
193 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
194 mod_hdr_hlist, hash_key) {
195 if (!cmp_mod_hdr_info(&mh->key, &key)) {
196 found = true;
197 break;
198 }
199 }
200 }
201
202 if (found)
203 goto attach_flow;
204
205 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
206 if (!mh)
207 return -ENOMEM;
208
209 mh->key.actions = (void *)mh + sizeof(*mh);
210 memcpy(mh->key.actions, key.actions, actions_size);
211 mh->key.num_actions = num_actions;
212 INIT_LIST_HEAD(&mh->flows);
213
214 err = mlx5_modify_header_alloc(priv->mdev, namespace,
215 mh->key.num_actions,
216 mh->key.actions,
217 &mh->mod_hdr_id);
218 if (err)
219 goto out_err;
220
221 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
222 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
223 else
224 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
225
226attach_flow:
227 list_add(&flow->mod_hdr, &mh->flows);
228 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
229 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
230 else
231 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
232
233 return 0;
234
235out_err:
236 kfree(mh);
237 return err;
238}
239
240static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
241 struct mlx5e_tc_flow *flow)
242{
243 struct list_head *next = flow->mod_hdr.next;
244
245 list_del(&flow->mod_hdr);
246
247 if (list_empty(next)) {
248 struct mlx5e_mod_hdr_entry *mh;
249
250 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
251
252 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
253 hash_del(&mh->mod_hdr_hlist);
254 kfree(mh);
255 }
256}
257
77ab67b7
OG		 258static
259struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
260{
261 struct net_device *netdev;
262 struct mlx5e_priv *priv;
263
264 netdev = __dev_get_by_index(net, ifindex);
265 priv = netdev_priv(netdev);
266 return priv->mdev;
267}
268
269static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
270{
271 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
272 void *tirc;
273 int err;
274
275 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
276 if (err)
277 goto alloc_tdn_err;
278
279 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
280
281 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 282 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 283 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
284
285 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
286 if (err)
287 goto create_tir_err;
288
289 return 0;
290
291create_tir_err:
292 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
293alloc_tdn_err:
294 return err;
295}
296
297static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
298{
299 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
300 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
301}
302
3f6d08d1
OG		 303static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
304{
305 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
306 struct mlx5e_priv *priv = hp->func_priv;
307 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
308
309 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
310 hp->num_channels);
311
312 for (i = 0; i < sz; i++) {
313 ix = i;
314 if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR)
315 ix = mlx5e_bits_invert(i, ilog2(sz));
316 ix = indirection_rqt[ix];
317 rqn = hp->pair->rqn[ix];
318 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
319 }
320}
321
322static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
323{
324 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
325 struct mlx5e_priv *priv = hp->func_priv;
326 struct mlx5_core_dev *mdev = priv->mdev;
327 void *rqtc;
328 u32 *in;
329
330 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
331 in = kvzalloc(inlen, GFP_KERNEL);
332 if (!in)
333 return -ENOMEM;
334
335 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
336
337 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
338 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
339
340 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
341
342 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
343 if (!err)
344 hp->indir_rqt.enabled = true;
345
346 kvfree(in);
347 return err;
348}
349
350static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
351{
352 struct mlx5e_priv *priv = hp->func_priv;
353 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
354 int tt, i, err;
355 void *tirc;
356
357 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
358 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
359 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
360
361 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
362 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
363 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
364 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
365
366 err = mlx5_core_create_tir(hp->func_mdev, in,
367 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
368 if (err) {
369 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
370 goto err_destroy_tirs;
371 }
372 }
373 return 0;
374
375err_destroy_tirs:
376 for (i = 0; i < tt; i++)
377 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
378 return err;
379}
380
381static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
382{
383 int tt;
384
385 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
386 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
387}
388
389static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
390 struct ttc_params *ttc_params)
391{
392 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
393 int tt;
394
395 memset(ttc_params, 0, sizeof(*ttc_params));
396
397 ttc_params->any_tt_tirn = hp->tirn;
398
399 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
400 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
401
402 ft_attr->max_fte = MLX5E_NUM_TT;
403 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
404 ft_attr->prio = MLX5E_TC_PRIO;
405}
406
407static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
408{
409 struct mlx5e_priv *priv = hp->func_priv;
410 struct ttc_params ttc_params;
411 int err;
412
413 err = mlx5e_hairpin_create_indirect_rqt(hp);
414 if (err)
415 return err;
416
417 err = mlx5e_hairpin_create_indirect_tirs(hp);
418 if (err)
419 goto err_create_indirect_tirs;
420
421 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
422 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
423 if (err)
424 goto err_create_ttc_table;
425
426 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
427 hp->num_channels, hp->ttc.ft.t->id);
428
429 return 0;
430
431err_create_ttc_table:
432 mlx5e_hairpin_destroy_indirect_tirs(hp);
433err_create_indirect_tirs:
434 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
435
436 return err;
437}
438
439static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
440{
441 struct mlx5e_priv *priv = hp->func_priv;
442
443 mlx5e_destroy_ttc_table(priv, &hp->ttc);
444 mlx5e_hairpin_destroy_indirect_tirs(hp);
445 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
446}
447
77ab67b7
OG		 448static struct mlx5e_hairpin *
449mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
450 int peer_ifindex)
451{
452 struct mlx5_core_dev *func_mdev, *peer_mdev;
453 struct mlx5e_hairpin *hp;
454 struct mlx5_hairpin *pair;
455 int err;
456
457 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
458 if (!hp)
459 return ERR_PTR(-ENOMEM);
460
461 func_mdev = priv->mdev;
462 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
463
464 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
465 if (IS_ERR(pair)) {
466 err = PTR_ERR(pair);
467 goto create_pair_err;
468 }
469 hp->pair = pair;
470 hp->func_mdev = func_mdev;
3f6d08d1
OG		 471 hp->func_priv = priv;
472 hp->num_channels = params->num_channels;
77ab67b7
OG		 473
474 err = mlx5e_hairpin_create_transport(hp);
475 if (err)
476 goto create_transport_err;
477
3f6d08d1
OG		 478 if (hp->num_channels > 1) {
479 err = mlx5e_hairpin_rss_init(hp);
480 if (err)
481 goto rss_init_err;
482 }
483
77ab67b7
OG		 484 return hp;
485
3f6d08d1
OG		 486rss_init_err:
487 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 488create_transport_err:
489 mlx5_core_hairpin_destroy(hp->pair);
490create_pair_err:
491 kfree(hp);
492 return ERR_PTR(err);
493}
494
495static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
496{
3f6d08d1
OG		 497 if (hp->num_channels > 1)
498 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 499 mlx5e_hairpin_destroy_transport(hp);
500 mlx5_core_hairpin_destroy(hp->pair);
501 kvfree(hp);
502}
503
106be53b
OG		 504static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
505{
506 return (peer_vhca_id << 16 | prio);
507}
508
5c65c564 509static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 510 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 511{
512 struct mlx5e_hairpin_entry *hpe;
106be53b 513 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 514
515 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 516 hairpin_hlist, hash_key) {
517 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 518 return hpe;
519 }
520
521 return NULL;
522}
523
106be53b
OG		 524#define UNKNOWN_MATCH_PRIO 8
525
526static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
527 struct mlx5_flow_spec *spec, u8 *match_prio)
528{
529 void *headers_c, *headers_v;
530 u8 prio_val, prio_mask = 0;
531 bool vlan_present;
532
533#ifdef CONFIG_MLX5_CORE_EN_DCB
534 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
535 netdev_warn(priv->netdev,
536 "only PCP trust state supported for hairpin\n");
537 return -EOPNOTSUPP;
538 }
539#endif
540 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
541 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
542
543 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
544 if (vlan_present) {
545 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
546 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
547 }
548
549 if (!vlan_present || !prio_mask) {
550 prio_val = UNKNOWN_MATCH_PRIO;
551 } else if (prio_mask != 0x7) {
552 netdev_warn(priv->netdev,
553 "masked priority match not supported for hairpin\n");
554 return -EOPNOTSUPP;
555 }
556
557 *match_prio = prio_val;
558 return 0;
559}
560
5c65c564
OG		 561static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
562 struct mlx5e_tc_flow *flow,
563 struct mlx5e_tc_flow_parse_attr *parse_attr)
564{
565 int peer_ifindex = parse_attr->mirred_ifindex;
566 struct mlx5_hairpin_params params;
d8822868 567 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 568 struct mlx5e_hairpin_entry *hpe;
569 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 570 u64 link_speed64;
571 u32 link_speed;
106be53b 572 u8 match_prio;
d8822868 573 u16 peer_id;
5c65c564
OG		 574 int err;
575
d8822868
OG		 576 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
577 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
5c65c564
OG		 578 netdev_warn(priv->netdev, "hairpin is not supported\n");
579 return -EOPNOTSUPP;
580 }
581
d8822868 582 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
106be53b
OG		 583 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio);
584 if (err)
585 return err;
586 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 587 if (hpe)
588 goto attach_flow;
589
590 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
591 if (!hpe)
592 return -ENOMEM;
593
594 INIT_LIST_HEAD(&hpe->flows);
d8822868 595 hpe->peer_vhca_id = peer_id;
106be53b 596 hpe->prio = match_prio;
5c65c564
OG		 597
598 params.log_data_size = 15;
599 params.log_data_size = min_t(u8, params.log_data_size,
600 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
601 params.log_data_size = max_t(u8, params.log_data_size,
602 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 603
eb9180f7
OG		 604 params.log_num_packets = params.log_data_size -
605 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
606 params.log_num_packets = min_t(u8, params.log_num_packets,
607 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
608
609 params.q_counter = priv->q_counter;
3f6d08d1
OG		 610 /* set hairpin pair per each 50Gbs share of the link */
611 mlx5e_get_max_linkspeed(priv->mdev, &link_speed);
612 link_speed = max_t(u32, link_speed, 50000);
613 link_speed64 = link_speed;
614 do_div(link_speed64, 50000);
615 params.num_channels = link_speed64;
616
5c65c564
OG		 617 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
618 if (IS_ERR(hp)) {
619 err = PTR_ERR(hp);
620 goto create_hairpin_err;
621 }
622
eb9180f7 623 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 624 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 625 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 626
627 hpe->hp = hp;
106be53b
OG		 628 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
629 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 630
631attach_flow:
3f6d08d1
OG		 632 if (hpe->hp->num_channels > 1) {
633 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
634 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
635 } else {
636 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
637 }
5c65c564 638 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 639
5c65c564
OG		 640 return 0;
641
642create_hairpin_err:
643 kfree(hpe);
644 return err;
645}
646
647static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
648 struct mlx5e_tc_flow *flow)
649{
650 struct list_head *next = flow->hairpin.next;
651
652 list_del(&flow->hairpin);
653
654 /* no more hairpin flows for us, release the hairpin pair */
655 if (list_empty(next)) {
656 struct mlx5e_hairpin_entry *hpe;
657
658 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
659
660 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
661 hpe->hp->pair->peer_mdev->priv.name);
662
663 mlx5e_hairpin_destroy(hpe->hp);
664 hash_del(&hpe->hairpin_hlist);
665 kfree(hpe);
666 }
667}
668
74491de9
MB		 669static struct mlx5_flow_handle *
670mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 671 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 672 struct mlx5e_tc_flow *flow)
e8f887ac 673{
aa0cbbae 674 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 675 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 676 struct mlx5_flow_destination dest[2] = {};
66958ed9 677 struct mlx5_flow_act flow_act = {
3bc4b7bf 678 .action = attr->action,
a9db0ecf 679 .has_flow_tag = true,
3bc4b7bf 680 .flow_tag = attr->flow_tag,
66958ed9
HHZ		 681 .encap_id = 0,
682 };
aad7e08d 683 struct mlx5_fc *counter = NULL;
74491de9 684 struct mlx5_flow_handle *rule;
e8f887ac 685 bool table_created = false;
5c65c564 686 int err, dest_ix = 0;
e8f887ac 687
3f6d08d1
OG		 688 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
689 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr);
690 if (err) {
691 rule = ERR_PTR(err);
692 goto err_add_hairpin_flow;
693 }
694 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
695 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
696 dest[dest_ix].ft = attr->hairpin_ft;
697 } else {
5c65c564
OG		 698 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
699 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 700 }
701 dest_ix++;
3f6d08d1
OG		 702 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
703 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
704 dest[dest_ix].ft = priv->fs.vlan.ft.t;
705 dest_ix++;
5c65c564 706 }
aad7e08d 707
5c65c564
OG		 708 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
709 counter = mlx5_fc_create(dev, true);
710 if (IS_ERR(counter)) {
711 rule = ERR_CAST(counter);
712 goto err_fc_create;
713 }
714 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
715 dest[dest_ix].counter = counter;
716 dest_ix++;
aad7e08d
AV		 717 }
718
2f4fe4ca 719 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 720 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 721 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG		 722 kfree(parse_attr->mod_hdr_actions);
723 if (err) {
724 rule = ERR_PTR(err);
725 goto err_create_mod_hdr_id;
726 }
727 }
728
acff797c 729 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 730 int tc_grp_size, tc_tbl_size;
731 u32 max_flow_counter;
732
733 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
734 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
735
736 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
737
738 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
739 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
740
acff797c
MG		 741 priv->fs.tc.t =
742 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
743 MLX5E_TC_PRIO,
21b9c144 744 tc_tbl_size,
acff797c 745 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 746 MLX5E_TC_FT_LEVEL, 0);
acff797c 747 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV		 748 netdev_err(priv->netdev,
749 "Failed to create tc offload table\n");
aad7e08d
AV		 750 rule = ERR_CAST(priv->fs.tc.t);
751 goto err_create_ft;
e8f887ac
AV		 752 }
753
754 table_created = true;
755 }
756
38aa51c1
OG		 757 if (attr->match_level != MLX5_MATCH_NONE)
758 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
759
17091853 760 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
5c65c564 761 &flow_act, dest, dest_ix);
aad7e08d
AV		 762
763 if (IS_ERR(rule))
764 goto err_add_rule;
765
766 return rule;
e8f887ac 767
aad7e08d
AV		 768err_add_rule:
769 if (table_created) {
acff797c
MG		 770 mlx5_destroy_flow_table(priv->fs.tc.t);
771 priv->fs.tc.t = NULL;
e8f887ac 772 }
aad7e08d 773err_create_ft:
2f4fe4ca 774 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 775 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 776err_create_mod_hdr_id:
aad7e08d 777 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 778err_fc_create:
779 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
780 mlx5e_hairpin_flow_del(priv, flow);
781err_add_hairpin_flow:
e8f887ac
AV		 782 return rule;
783}
784
d85cdccb
OG		 785static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
786 struct mlx5e_tc_flow *flow)
787{
513f8f7f 788 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 789 struct mlx5_fc *counter = NULL;
790
aa0cbbae
OG		 791 counter = mlx5_flow_rule_counter(flow->rule);
792 mlx5_del_flow_rules(flow->rule);
793 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 794
b3a433de 795 if (!mlx5e_tc_num_filters(priv) && priv->fs.tc.t) {
d85cdccb
OG		 796 mlx5_destroy_flow_table(priv->fs.tc.t);
797 priv->fs.tc.t = NULL;
798 }
2f4fe4ca 799
513f8f7f 800 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 801 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 802
803 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
804 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 805}
806
aa0cbbae
OG		 807static void mlx5e_detach_encap(struct mlx5e_priv *priv,
808 struct mlx5e_tc_flow *flow);
809
3c37745e
OG		 810static int mlx5e_attach_encap(struct mlx5e_priv *priv,
811 struct ip_tunnel_info *tun_info,
812 struct net_device *mirred_dev,
813 struct net_device **encap_dev,
814 struct mlx5e_tc_flow *flow);
815
74491de9
MB		 816static struct mlx5_flow_handle *
817mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 818 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 819 struct mlx5e_tc_flow *flow)
adb4c123
OG		 820{
821 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 822 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3c37745e
OG		 823 struct net_device *out_dev, *encap_dev = NULL;
824 struct mlx5_flow_handle *rule = NULL;
825 struct mlx5e_rep_priv *rpriv;
826 struct mlx5e_priv *out_priv;
8b32580d
OG		 827 int err;
828
3c37745e
OG		 829 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
830 out_dev = __dev_get_by_index(dev_net(priv->netdev),
831 attr->parse_attr->mirred_ifindex);
832 err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
833 out_dev, &encap_dev, flow);
834 if (err) {
835 rule = ERR_PTR(err);
836 if (err != -EAGAIN)
837 goto err_attach_encap;
838 }
839 out_priv = netdev_priv(encap_dev);
840 rpriv = out_priv->ppriv;
841 attr->out_rep = rpriv->rep;
56e858df 842 attr->out_mdev = out_priv->mdev;
3c37745e
OG		 843 }
844
8b32580d 845 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG		 846 if (err) {
847 rule = ERR_PTR(err);
848 goto err_add_vlan;
849 }
adb4c123 850
d7e75a32 851 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 852 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32
OG		 853 kfree(parse_attr->mod_hdr_actions);
854 if (err) {
855 rule = ERR_PTR(err);
856 goto err_mod_hdr;
857 }
858 }
859
3c37745e
OG		 860 /* we get here if (1) there's no error (rule being null) or when
861 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
862 */
863 if (rule != ERR_PTR(-EAGAIN)) {
864 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
865 if (IS_ERR(rule))
866 goto err_add_rule;
867 }
aa0cbbae
OG		 868 return rule;
869
870err_add_rule:
513f8f7f 871 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 872 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 873err_mod_hdr:
aa0cbbae
OG		 874 mlx5_eswitch_del_vlan_action(esw, attr);
875err_add_vlan:
876 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
877 mlx5e_detach_encap(priv, flow);
3c37745e 878err_attach_encap:
aa0cbbae
OG		 879 return rule;
880}
d85cdccb
OG		 881
882static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
883 struct mlx5e_tc_flow *flow)
884{
885 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 886 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 887
232c0013
HHZ		 888 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
889 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
513f8f7f 890 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, attr);
232c0013 891 }
d85cdccb 892
513f8f7f 893 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 894
513f8f7f 895 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
d85cdccb 896 mlx5e_detach_encap(priv, flow);
513f8f7f 897 kvfree(attr->parse_attr);
232c0013 898 }
d7e75a32 899
513f8f7f 900 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 901 mlx5e_detach_mod_hdr(priv, flow);
d85cdccb
OG		 902}
903
232c0013
HHZ		 904void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
905 struct mlx5e_encap_entry *e)
906{
3c37745e
OG		 907 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
908 struct mlx5_esw_flow_attr *esw_attr;
232c0013
HHZ		 909 struct mlx5e_tc_flow *flow;
910 int err;
911
912 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
913 e->encap_size, e->encap_header,
914 &e->encap_id);
915 if (err) {
916 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
917 err);
918 return;
919 }
920 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 921 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 922
923 list_for_each_entry(flow, &e->flows, encap) {
3c37745e
OG		 924 esw_attr = flow->esw_attr;
925 esw_attr->encap_id = e->encap_id;
926 flow->rule = mlx5_eswitch_add_offloaded_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
232c0013
HHZ		 927 if (IS_ERR(flow->rule)) {
928 err = PTR_ERR(flow->rule);
929 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
930 err);
931 continue;
932 }
933 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
934 }
935}
936
937void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
938 struct mlx5e_encap_entry *e)
939{
3c37745e 940 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
232c0013 941 struct mlx5e_tc_flow *flow;
232c0013
HHZ		 942
943 list_for_each_entry(flow, &e->flows, encap) {
944 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
945 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
3c37745e 946 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, flow->esw_attr);
232c0013
HHZ		 947 }
948 }
949
950 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
951 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
952 mlx5_encap_dealloc(priv->mdev, e->encap_id);
953 }
954}
955
f6dfb4c3
HHZ		 956void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
957{
958 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
959 u64 bytes, packets, lastuse = 0;
960 struct mlx5e_tc_flow *flow;
961 struct mlx5e_encap_entry *e;
962 struct mlx5_fc *counter;
963 struct neigh_table *tbl;
964 bool neigh_used = false;
965 struct neighbour *n;
966
967 if (m_neigh->family == AF_INET)
968 tbl = &arp_tbl;
969#if IS_ENABLED(CONFIG_IPV6)
970 else if (m_neigh->family == AF_INET6)
423c9db2 971 tbl = &nd_tbl;
f6dfb4c3
HHZ		 972#endif
973 else
974 return;
975
976 list_for_each_entry(e, &nhe->encap_list, encap_list) {
977 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
978 continue;
979 list_for_each_entry(flow, &e->flows, encap) {
980 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
981 counter = mlx5_flow_rule_counter(flow->rule);
982 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
983 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
984 neigh_used = true;
985 break;
986 }
987 }
988 }
e36d4810
RD		 989 if (neigh_used)
990 break;
f6dfb4c3
HHZ		 991 }
992
993 if (neigh_used) {
994 nhe->reported_lastuse = jiffies;
995
996 /* find the relevant neigh according to the cached device and
997 * dst ip pair
998 */
999 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1000 if (!n) {
1001 WARN(1, "The neighbour already freed\n");
1002 return;
1003 }
1004
1005 neigh_event_send(n, NULL);
1006 neigh_release(n);
1007 }
1008}
1009
d85cdccb
OG		 1010static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1011 struct mlx5e_tc_flow *flow)
1012{
5067b602
RD		 1013 struct list_head *next = flow->encap.next;
1014
1015 list_del(&flow->encap);
1016 if (list_empty(next)) {
c1ae1152 1017 struct mlx5e_encap_entry *e;
5067b602 1018
c1ae1152 1019 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1020 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1021
1022 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
5067b602 1023 mlx5_encap_dealloc(priv->mdev, e->encap_id);
232c0013 1024
cdc5a7f3 1025 hash_del_rcu(&e->encap_hlist);
232c0013 1026 kfree(e->encap_header);
5067b602
RD		 1027 kfree(e);
1028 }
1029}
1030
e8f887ac 1031static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1032 struct mlx5e_tc_flow *flow)
e8f887ac 1033{
d85cdccb
OG		 1034 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1035 mlx5e_tc_del_fdb_flow(priv, flow);
1036 else
1037 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 1038}
1039
bbd00f7e
HHZ		 1040static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
1041 struct tc_cls_flower_offload *f)
1042{
1043 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1044 outer_headers);
1045 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1046 outer_headers);
1047 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1048 misc_parameters);
1049 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1050 misc_parameters);
1051
1052 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
1053 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1054
1055 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
1056 struct flow_dissector_key_keyid *key =
1057 skb_flow_dissector_target(f->dissector,
1058 FLOW_DISSECTOR_KEY_ENC_KEYID,
1059 f->key);
1060 struct flow_dissector_key_keyid *mask =
1061 skb_flow_dissector_target(f->dissector,
1062 FLOW_DISSECTOR_KEY_ENC_KEYID,
1063 f->mask);
1064 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
1065 be32_to_cpu(mask->keyid));
1066 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
1067 be32_to_cpu(key->keyid));
1068 }
1069}
1070
1071static int parse_tunnel_attr(struct mlx5e_priv *priv,
1072 struct mlx5_flow_spec *spec,
1073 struct tc_cls_flower_offload *f)
1074{
1075 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1076 outer_headers);
1077 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1078 outer_headers);
1079
2e72eb43
OG		 1080 struct flow_dissector_key_control *enc_control =
1081 skb_flow_dissector_target(f->dissector,
1082 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1083 f->key);
1084
bbd00f7e
HHZ		 1085 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
1086 struct flow_dissector_key_ports *key =
1087 skb_flow_dissector_target(f->dissector,
1088 FLOW_DISSECTOR_KEY_ENC_PORTS,
1089 f->key);
1090 struct flow_dissector_key_ports *mask =
1091 skb_flow_dissector_target(f->dissector,
1092 FLOW_DISSECTOR_KEY_ENC_PORTS,
1093 f->mask);
1ad9a00a 1094 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4 1095 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5ed99fb4 1096 struct net_device *up_dev = uplink_rpriv->netdev;
1ad9a00a 1097 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ		 1098
1099 /* Full udp dst port must be given */
1100 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 1101 goto vxlan_match_offload_err;
bbd00f7e 1102
1ad9a00a 1103 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 1104 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
1105 parse_vxlan_attr(spec, f);
2fcd82e9
OG		 1106 else {
1107 netdev_warn(priv->netdev,
1108 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 1109 return -EOPNOTSUPP;
2fcd82e9 1110 }
bbd00f7e
HHZ		 1111
1112 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1113 udp_dport, ntohs(mask->dst));
1114 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1115 udp_dport, ntohs(key->dst));
1116
cd377663
OG		 1117 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1118 udp_sport, ntohs(mask->src));
1119 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1120 udp_sport, ntohs(key->src));
bbd00f7e 1121 } else { /* udp dst port must be given */
2fcd82e9
OG		 1122vxlan_match_offload_err:
1123 netdev_warn(priv->netdev,
1124 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
1125 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1126 }
1127
2e72eb43 1128 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 1129 struct flow_dissector_key_ipv4_addrs *key =
1130 skb_flow_dissector_target(f->dissector,
1131 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1132 f->key);
1133 struct flow_dissector_key_ipv4_addrs *mask =
1134 skb_flow_dissector_target(f->dissector,
1135 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1136 f->mask);
1137 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1138 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1139 ntohl(mask->src));
1140 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1141 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1142 ntohl(key->src));
1143
1144 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1145 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1146 ntohl(mask->dst));
1147 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1148 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1149 ntohl(key->dst));
bbd00f7e 1150
2e72eb43
OG		 1151 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1152 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 1153 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1154 struct flow_dissector_key_ipv6_addrs *key =
1155 skb_flow_dissector_target(f->dissector,
1156 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1157 f->key);
1158 struct flow_dissector_key_ipv6_addrs *mask =
1159 skb_flow_dissector_target(f->dissector,
1160 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1161 f->mask);
1162
1163 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1164 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1165 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1166 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1167 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1168 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1169
1170 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1171 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1172 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1173 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1174 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1175 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1176
1177 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1178 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1179 }
bbd00f7e
HHZ		 1180
1181 /* Enforce DMAC when offloading incoming tunneled flows.
1182 * Flow counters require a match on the DMAC.
1183 */
1184 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1185 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1186 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1187 dmac_47_16), priv->netdev->dev_addr);
1188
1189 /* let software handle IP fragments */
1190 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1191 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1192
1193 return 0;
1194}
1195
de0af0bf
RD		 1196static int __parse_cls_flower(struct mlx5e_priv *priv,
1197 struct mlx5_flow_spec *spec,
1198 struct tc_cls_flower_offload *f,
d708f902 1199 u8 *match_level)
e3a2b7ed 1200{
c5bb1730
MG		 1201 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1202 outer_headers);
1203 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1204 outer_headers);
e3a2b7ed
AV		 1205 u16 addr_type = 0;
1206 u8 ip_proto = 0;
1207
d708f902 1208 *match_level = MLX5_MATCH_NONE;
de0af0bf 1209
e3a2b7ed
AV		 1210 if (f->dissector->used_keys &
1211 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1212 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1213 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1214 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV		 1215 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1216 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1217 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1218 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1219 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1220 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1221 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1222 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b
OG		 1223 BIT(FLOW_DISSECTOR_KEY_TCP) |
1224 BIT(FLOW_DISSECTOR_KEY_IP))) {
e3a2b7ed
AV		 1225 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1226 f->dissector->used_keys);
1227 return -EOPNOTSUPP;
1228 }
1229
bbd00f7e
HHZ		 1230 if ((dissector_uses_key(f->dissector,
1231 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1232 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1233 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1234 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1235 struct flow_dissector_key_control *key =
1236 skb_flow_dissector_target(f->dissector,
1237 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1238 f->key);
1239 switch (key->addr_type) {
1240 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1241 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 1242 if (parse_tunnel_attr(priv, spec, f))
1243 return -EOPNOTSUPP;
1244 break;
1245 default:
1246 return -EOPNOTSUPP;
1247 }
1248
1249 /* In decap flow, header pointers should point to the inner
1250 * headers, outer header were already set by parse_tunnel_attr
1251 */
1252 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1253 inner_headers);
1254 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1255 inner_headers);
1256 }
1257
e3a2b7ed
AV		 1258 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1259 struct flow_dissector_key_eth_addrs *key =
1260 skb_flow_dissector_target(f->dissector,
1261 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1262 f->key);
1263 struct flow_dissector_key_eth_addrs *mask =
1264 skb_flow_dissector_target(f->dissector,
1265 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1266 f->mask);
1267
1268 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1269 dmac_47_16),
1270 mask->dst);
1271 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1272 dmac_47_16),
1273 key->dst);
1274
1275 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1276 smac_47_16),
1277 mask->src);
1278 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1279 smac_47_16),
1280 key->src);
54782900
OG		 1281
1282 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
d708f902 1283 *match_level = MLX5_MATCH_L2;
e3a2b7ed
AV		 1284 }
1285
095b6cfd
OG		 1286 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1287 struct flow_dissector_key_vlan *key =
1288 skb_flow_dissector_target(f->dissector,
1289 FLOW_DISSECTOR_KEY_VLAN,
1290 f->key);
1291 struct flow_dissector_key_vlan *mask =
1292 skb_flow_dissector_target(f->dissector,
1293 FLOW_DISSECTOR_KEY_VLAN,
1294 f->mask);
358d79a4 1295 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY		 1296 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1297 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG		 1298
1299 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1300 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 1301
1302 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1303 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
54782900 1304
d708f902 1305 *match_level = MLX5_MATCH_L2;
54782900
OG		 1306 }
1307 }
1308
1309 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1310 struct flow_dissector_key_basic *key =
1311 skb_flow_dissector_target(f->dissector,
1312 FLOW_DISSECTOR_KEY_BASIC,
1313 f->key);
1314 struct flow_dissector_key_basic *mask =
1315 skb_flow_dissector_target(f->dissector,
1316 FLOW_DISSECTOR_KEY_BASIC,
1317 f->mask);
1318 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1319 ntohs(mask->n_proto));
1320 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1321 ntohs(key->n_proto));
1322
1323 if (mask->n_proto)
d708f902 1324 *match_level = MLX5_MATCH_L2;
54782900
OG		 1325 }
1326
1327 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1328 struct flow_dissector_key_control *key =
1329 skb_flow_dissector_target(f->dissector,
1330 FLOW_DISSECTOR_KEY_CONTROL,
1331 f->key);
1332
1333 struct flow_dissector_key_control *mask =
1334 skb_flow_dissector_target(f->dissector,
1335 FLOW_DISSECTOR_KEY_CONTROL,
1336 f->mask);
1337 addr_type = key->addr_type;
1338
1339 /* the HW doesn't support frag first/later */
1340 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1341 return -EOPNOTSUPP;
1342
1343 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1344 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1345 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1346 key->flags & FLOW_DIS_IS_FRAGMENT);
1347
1348 /* the HW doesn't need L3 inline to match on frag=no */
1349 if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
d708f902 1350 *match_level = MLX5_INLINE_MODE_L2;
54782900
OG		 1351 /* *** L2 attributes parsing up to here *** */
1352 else
d708f902 1353 *match_level = MLX5_INLINE_MODE_IP;
095b6cfd
OG		 1354 }
1355 }
1356
54782900
OG		 1357 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1358 struct flow_dissector_key_basic *key =
1359 skb_flow_dissector_target(f->dissector,
1360 FLOW_DISSECTOR_KEY_BASIC,
1361 f->key);
1362 struct flow_dissector_key_basic *mask =
1363 skb_flow_dissector_target(f->dissector,
1364 FLOW_DISSECTOR_KEY_BASIC,
1365 f->mask);
1366 ip_proto = key->ip_proto;
1367
1368 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1369 mask->ip_proto);
1370 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1371 key->ip_proto);
1372
1373 if (mask->ip_proto)
d708f902 1374 *match_level = MLX5_MATCH_L3;
54782900
OG		 1375 }
1376
e3a2b7ed
AV		 1377 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1378 struct flow_dissector_key_ipv4_addrs *key =
1379 skb_flow_dissector_target(f->dissector,
1380 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1381 f->key);
1382 struct flow_dissector_key_ipv4_addrs *mask =
1383 skb_flow_dissector_target(f->dissector,
1384 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1385 f->mask);
1386
1387 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1388 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1389 &mask->src, sizeof(mask->src));
1390 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1391 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1392 &key->src, sizeof(key->src));
1393 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1394 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1395 &mask->dst, sizeof(mask->dst));
1396 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1397 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1398 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1399
1400 if (mask->src || mask->dst)
d708f902 1401 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1402 }
1403
1404 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1405 struct flow_dissector_key_ipv6_addrs *key =
1406 skb_flow_dissector_target(f->dissector,
1407 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1408 f->key);
1409 struct flow_dissector_key_ipv6_addrs *mask =
1410 skb_flow_dissector_target(f->dissector,
1411 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1412 f->mask);
1413
1414 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1415 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1416 &mask->src, sizeof(mask->src));
1417 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1418 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1419 &key->src, sizeof(key->src));
1420
1421 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1422 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1423 &mask->dst, sizeof(mask->dst));
1424 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1425 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1426 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1427
1428 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1429 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
d708f902 1430 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1431 }
1432
1f97a526
OG		 1433 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1434 struct flow_dissector_key_ip *key =
1435 skb_flow_dissector_target(f->dissector,
1436 FLOW_DISSECTOR_KEY_IP,
1437 f->key);
1438 struct flow_dissector_key_ip *mask =
1439 skb_flow_dissector_target(f->dissector,
1440 FLOW_DISSECTOR_KEY_IP,
1441 f->mask);
1442
1443 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1444 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1445
1446 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1447 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1448
a8ade55f
OG		 1449 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1450 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 1451
a8ade55f
OG		 1452 if (mask->ttl &&
1453 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
1454 ft_field_support.outer_ipv4_ttl))
1f97a526 1455 return -EOPNOTSUPP;
a8ade55f
OG		 1456
1457 if (mask->tos || mask->ttl)
d708f902 1458 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1459 }
1460
54782900
OG		 1461 /* *** L3 attributes parsing up to here *** */
1462
e3a2b7ed
AV		 1463 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1464 struct flow_dissector_key_ports *key =
1465 skb_flow_dissector_target(f->dissector,
1466 FLOW_DISSECTOR_KEY_PORTS,
1467 f->key);
1468 struct flow_dissector_key_ports *mask =
1469 skb_flow_dissector_target(f->dissector,
1470 FLOW_DISSECTOR_KEY_PORTS,
1471 f->mask);
1472 switch (ip_proto) {
1473 case IPPROTO_TCP:
1474 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1475 tcp_sport, ntohs(mask->src));
1476 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1477 tcp_sport, ntohs(key->src));
1478
1479 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1480 tcp_dport, ntohs(mask->dst));
1481 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1482 tcp_dport, ntohs(key->dst));
1483 break;
1484
1485 case IPPROTO_UDP:
1486 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1487 udp_sport, ntohs(mask->src));
1488 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1489 udp_sport, ntohs(key->src));
1490
1491 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1492 udp_dport, ntohs(mask->dst));
1493 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1494 udp_dport, ntohs(key->dst));
1495 break;
1496 default:
1497 netdev_err(priv->netdev,
1498 "Only UDP and TCP transport are supported\n");
1499 return -EINVAL;
1500 }
de0af0bf
RD		 1501
1502 if (mask->src || mask->dst)
d708f902 1503 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1504 }
1505
e77834ec
OG		 1506 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1507 struct flow_dissector_key_tcp *key =
1508 skb_flow_dissector_target(f->dissector,
1509 FLOW_DISSECTOR_KEY_TCP,
1510 f->key);
1511 struct flow_dissector_key_tcp *mask =
1512 skb_flow_dissector_target(f->dissector,
1513 FLOW_DISSECTOR_KEY_TCP,
1514 f->mask);
1515
1516 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1517 ntohs(mask->flags));
1518 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1519 ntohs(key->flags));
1520
1521 if (mask->flags)
d708f902 1522 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1523 }
1524
e3a2b7ed
AV		 1525 return 0;
1526}
1527
de0af0bf 1528static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1529 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 1530 struct mlx5_flow_spec *spec,
1531 struct tc_cls_flower_offload *f)
1532{
1533 struct mlx5_core_dev *dev = priv->mdev;
1534 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1535 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1536 struct mlx5_eswitch_rep *rep;
d708f902 1537 u8 match_level;
de0af0bf
RD		 1538 int err;
1539
d708f902 1540 err = __parse_cls_flower(priv, spec, f, &match_level);
de0af0bf 1541
1d447a39
SM		 1542 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1543 rep = rpriv->rep;
1544 if (rep->vport != FDB_UPLINK_VPORT &&
1545 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1546 esw->offloads.inline_mode < match_level)) {
de0af0bf
RD		 1547 netdev_warn(priv->netdev,
1548 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1549 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1550 return -EOPNOTSUPP;
1551 }
1552 }
1553
38aa51c1
OG		 1554 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1555 flow->esw_attr->match_level = match_level;
1556 else
1557 flow->nic_attr->match_level = match_level;
1558
de0af0bf
RD		 1559 return err;
1560}
1561
d79b6df6
OG		 1562struct pedit_headers {
1563 struct ethhdr eth;
1564 struct iphdr ip4;
1565 struct ipv6hdr ip6;
1566 struct tcphdr tcp;
1567 struct udphdr udp;
1568};
1569
1570static int pedit_header_offsets[] = {
1571 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1572 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1573 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1574 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1575 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1576};
1577
1578#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1579
1580static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1581 struct pedit_headers *masks,
1582 struct pedit_headers *vals)
1583{
1584 u32 *curr_pmask, *curr_pval;
1585
1586 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1587 goto out_err;
1588
1589 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1590 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1591
1592 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1593 goto out_err;
1594
1595 *curr_pmask |= mask;
1596 *curr_pval |= (val & mask);
1597
1598 return 0;
1599
1600out_err:
1601 return -EOPNOTSUPP;
1602}
1603
1604struct mlx5_fields {
1605 u8 field;
1606 u8 size;
1607 u32 offset;
1608};
1609
a8e4f0c4
OG		 1610#define OFFLOAD(fw_field, size, field, off) \
1611 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1612
d79b6df6 1613static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1614 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1615 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1616 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1617 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1618 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1619
1620 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1621 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1622 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1623
1624 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1625 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1626 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1627 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1628 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1629 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1630 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1631 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1632 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1633
1634 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1635 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1636 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1637
1638 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1639 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1640};
1641
1642/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1643 * max from the SW pedit action. On success, it says how many HW actions were
1644 * actually parsed.
1645 */
1646static int offload_pedit_fields(struct pedit_headers *masks,
1647 struct pedit_headers *vals,
1648 struct mlx5e_tc_flow_parse_attr *parse_attr)
1649{
1650 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1651 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1652 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1653 struct mlx5_fields *f;
1654 u8 cmd, field_bsize;
e3ca4e05 1655 u32 s_mask, a_mask;
d79b6df6 1656 unsigned long mask;
2b64beba
OG		 1657 __be32 mask_be32;
1658 __be16 mask_be16;
d79b6df6
OG		 1659 void *action;
1660
1661 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1662 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1663 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1664 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1665
1666 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1667 action = parse_attr->mod_hdr_actions;
1668 max_actions = parse_attr->num_mod_hdr_actions;
1669 nactions = 0;
1670
1671 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1672 f = &fields[i];
1673 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1674 s_mask = 0;
1675 a_mask = 0;
d79b6df6
OG		 1676
1677 s_masks_p = (void *)set_masks + f->offset;
1678 a_masks_p = (void *)add_masks + f->offset;
1679
1680 memcpy(&s_mask, s_masks_p, f->size);
1681 memcpy(&a_mask, a_masks_p, f->size);
1682
1683 if (!s_mask && !a_mask) /* nothing to offload here */
1684 continue;
1685
1686 if (s_mask && a_mask) {
1687 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1688 return -EOPNOTSUPP;
1689 }
1690
1691 if (nactions == max_actions) {
1692 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1693 return -EOPNOTSUPP;
1694 }
1695
1696 if (s_mask) {
1697 cmd = MLX5_ACTION_TYPE_SET;
1698 mask = s_mask;
1699 vals_p = (void *)set_vals + f->offset;
1700 /* clear to denote we consumed this field */
1701 memset(s_masks_p, 0, f->size);
1702 } else {
1703 cmd = MLX5_ACTION_TYPE_ADD;
1704 mask = a_mask;
1705 vals_p = (void *)add_vals + f->offset;
1706 /* clear to denote we consumed this field */
1707 memset(a_masks_p, 0, f->size);
1708 }
1709
d79b6df6 1710 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1711
2b64beba
OG		 1712 if (field_bsize == 32) {
1713 mask_be32 = *(__be32 *)&mask;
1714 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1715 } else if (field_bsize == 16) {
1716 mask_be16 = *(__be16 *)&mask;
1717 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1718 }
1719
d79b6df6 1720 first = find_first_bit(&mask, field_bsize);
2b64beba 1721 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1722 last = find_last_bit(&mask, field_bsize);
2b64beba
OG		 1723 if (first < next_z && next_z < last) {
1724 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1725 mask);
1726 return -EOPNOTSUPP;
1727 }
1728
1729 MLX5_SET(set_action_in, action, action_type, cmd);
1730 MLX5_SET(set_action_in, action, field, f->field);
1731
1732 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1733 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1734 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1735 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1736 }
1737
1738 if (field_bsize == 32)
2b64beba 1739 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1740 else if (field_bsize == 16)
2b64beba 1741 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1742 else if (field_bsize == 8)
2b64beba 1743 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1744
1745 action += action_size;
1746 nactions++;
1747 }
1748
1749 parse_attr->num_mod_hdr_actions = nactions;
1750 return 0;
1751}
1752
1753static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1754 const struct tc_action *a, int namespace,
1755 struct mlx5e_tc_flow_parse_attr *parse_attr)
1756{
1757 int nkeys, action_size, max_actions;
1758
1759 nkeys = tcf_pedit_nkeys(a);
1760 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1761
1762 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1763 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1764 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1765 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1766
1767 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1768 max_actions = min(max_actions, nkeys * 16);
1769
1770 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1771 if (!parse_attr->mod_hdr_actions)
1772 return -ENOMEM;
1773
1774 parse_attr->num_mod_hdr_actions = max_actions;
1775 return 0;
1776}
1777
1778static const struct pedit_headers zero_masks = {};
1779
1780static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1781 const struct tc_action *a, int namespace,
1782 struct mlx5e_tc_flow_parse_attr *parse_attr)
1783{
1784 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1785 int nkeys, i, err = -EOPNOTSUPP;
1786 u32 mask, val, offset;
1787 u8 cmd, htype;
1788
1789 nkeys = tcf_pedit_nkeys(a);
1790
1791 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1792 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1793
1794 for (i = 0; i < nkeys; i++) {
1795 htype = tcf_pedit_htype(a, i);
1796 cmd = tcf_pedit_cmd(a, i);
1797 err = -EOPNOTSUPP; /* can't be all optimistic */
1798
1799 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
b3a433de 1800 netdev_warn(priv->netdev, "legacy pedit isn't offloaded\n");
d79b6df6
OG		 1801 goto out_err;
1802 }
1803
1804 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
b3a433de 1805 netdev_warn(priv->netdev, "pedit cmd %d isn't offloaded\n", cmd);
d79b6df6
OG		 1806 goto out_err;
1807 }
1808
1809 mask = tcf_pedit_mask(a, i);
1810 val = tcf_pedit_val(a, i);
1811 offset = tcf_pedit_offset(a, i);
1812
1813 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1814 if (err)
1815 goto out_err;
1816 }
1817
1818 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1819 if (err)
1820 goto out_err;
1821
1822 err = offload_pedit_fields(masks, vals, parse_attr);
1823 if (err < 0)
1824 goto out_dealloc_parsed_actions;
1825
1826 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1827 cmd_masks = &masks[cmd];
1828 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
b3a433de 1829 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 1830 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1831 16, 1, cmd_masks, sizeof(zero_masks), true);
1832 err = -EOPNOTSUPP;
1833 goto out_dealloc_parsed_actions;
1834 }
1835 }
1836
1837 return 0;
1838
1839out_dealloc_parsed_actions:
1840 kfree(parse_attr->mod_hdr_actions);
1841out_err:
1842 return err;
1843}
1844
26c02749
OG		 1845static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1846{
1847 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1848 TCA_CSUM_UPDATE_FLAG_UDP;
1849
1850 /* The HW recalcs checksums only if re-writing headers */
1851 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1852 netdev_warn(priv->netdev,
1853 "TC csum action is only offloaded with pedit\n");
1854 return false;
1855 }
1856
1857 if (update_flags & ~prot_flags) {
1858 netdev_warn(priv->netdev,
1859 "can't offload TC csum action for some header/s - flags %#x\n",
1860 update_flags);
1861 return false;
1862 }
1863
1864 return true;
1865}
1866
bdd66ac0
OG		 1867static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
1868 struct tcf_exts *exts)
1869{
1870 const struct tc_action *a;
1871 bool modify_ip_header;
1872 LIST_HEAD(actions);
1873 u8 htype, ip_proto;
1874 void *headers_v;
1875 u16 ethertype;
1876 int nkeys, i;
1877
1878 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1879 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1880
1881 /* for non-IP we only re-write MACs, so we're okay */
1882 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
1883 goto out_ok;
1884
1885 modify_ip_header = false;
1886 tcf_exts_to_list(exts, &actions);
1887 list_for_each_entry(a, &actions, list) {
1888 if (!is_tcf_pedit(a))
1889 continue;
1890
1891 nkeys = tcf_pedit_nkeys(a);
1892 for (i = 0; i < nkeys; i++) {
1893 htype = tcf_pedit_htype(a, i);
1894 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
1895 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
1896 modify_ip_header = true;
1897 break;
1898 }
1899 }
1900 }
1901
1902 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 1903 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
1904 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
bdd66ac0
OG		 1905 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
1906 return false;
1907 }
1908
1909out_ok:
1910 return true;
1911}
1912
1913static bool actions_match_supported(struct mlx5e_priv *priv,
1914 struct tcf_exts *exts,
1915 struct mlx5e_tc_flow_parse_attr *parse_attr,
1916 struct mlx5e_tc_flow *flow)
1917{
1918 u32 actions;
1919
1920 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1921 actions = flow->esw_attr->action;
1922 else
1923 actions = flow->nic_attr->action;
1924
1925 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1926 return modify_header_match_supported(&parse_attr->spec, exts);
1927
1928 return true;
1929}
1930
5c65c564
OG		 1931static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
1932{
1933 struct mlx5_core_dev *fmdev, *pmdev;
1934 u16 func_id, peer_id;
1935
1936 fmdev = priv->mdev;
1937 pmdev = peer_priv->mdev;
1938
1939 func_id = (u16)((fmdev->pdev->bus->number << 8) | PCI_SLOT(fmdev->pdev->devfn));
1940 peer_id = (u16)((pmdev->pdev->bus->number << 8) | PCI_SLOT(pmdev->pdev->devfn));
1941
1942 return (func_id == peer_id);
1943}
1944
5c40348c 1945static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG		 1946 struct mlx5e_tc_flow_parse_attr *parse_attr,
1947 struct mlx5e_tc_flow *flow)
e3a2b7ed 1948{
aa0cbbae 1949 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1950 const struct tc_action *a;
22dc13c8 1951 LIST_HEAD(actions);
1cab1cd7 1952 u32 action = 0;
2f4fe4ca 1953 int err;
e3a2b7ed 1954
3bcc0cec 1955 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 1956 return -EINVAL;
1957
3bc4b7bf 1958 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 1959
22dc13c8
WC		 1960 tcf_exts_to_list(exts, &actions);
1961 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1962 if (is_tcf_gact_shot(a)) {
1cab1cd7 1963 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 1964 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1965 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 1966 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 1967 continue;
1968 }
1969
2f4fe4ca
OG		 1970 if (is_tcf_pedit(a)) {
1971 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1972 parse_attr);
1973 if (err)
1974 return err;
1975
1cab1cd7
OG		 1976 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1977 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2f4fe4ca
OG		 1978 continue;
1979 }
1980
26c02749 1981 if (is_tcf_csum(a)) {
1cab1cd7 1982 if (csum_offload_supported(priv, action,
26c02749
OG		 1983 tcf_csum_update_flags(a)))
1984 continue;
1985
1986 return -EOPNOTSUPP;
1987 }
1988
5c65c564
OG		 1989 if (is_tcf_mirred_egress_redirect(a)) {
1990 struct net_device *peer_dev = tcf_mirred_dev(a);
1991
1992 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
1993 same_hw_devs(priv, netdev_priv(peer_dev))) {
1994 parse_attr->mirred_ifindex = peer_dev->ifindex;
1995 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 1996 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1997 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564
OG		 1998 } else {
1999 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2000 peer_dev->name);
2001 return -EINVAL;
2002 }
2003 continue;
2004 }
2005
e3a2b7ed
AV		 2006 if (is_tcf_skbedit_mark(a)) {
2007 u32 mark = tcf_skbedit_mark(a);
2008
2009 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2010 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
2011 mark);
2012 return -EINVAL;
2013 }
2014
3bc4b7bf 2015 attr->flow_tag = mark;
1cab1cd7 2016 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 2017 continue;
2018 }
2019
2020 return -EINVAL;
2021 }
2022
1cab1cd7 2023 attr->action = action;
bdd66ac0
OG		 2024 if (!actions_match_supported(priv, exts, parse_attr, flow))
2025 return -EOPNOTSUPP;
2026
e3a2b7ed
AV		 2027 return 0;
2028}
2029
76f7444d
OG		 2030static inline int cmp_encap_info(struct ip_tunnel_key *a,
2031 struct ip_tunnel_key *b)
a54e20b4
HHZ		 2032{
2033 return memcmp(a, b, sizeof(*a));
2034}
2035
76f7444d 2036static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2037{
76f7444d 2038 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2039}
2040
2041static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
2042 struct net_device *mirred_dev,
2043 struct net_device **out_dev,
2044 struct flowi4 *fl4,
2045 struct neighbour **out_n,
a54e20b4
HHZ		 2046 int *out_ttl)
2047{
3e621b19 2048 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5ed99fb4 2049 struct mlx5e_rep_priv *uplink_rpriv;
a54e20b4
HHZ		 2050 struct rtable *rt;
2051 struct neighbour *n = NULL;
a54e20b4
HHZ		 2052
2053#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 2054 int ret;
2055
a54e20b4 2056 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 2057 ret = PTR_ERR_OR_ZERO(rt);
2058 if (ret)
2059 return ret;
a54e20b4
HHZ		 2060#else
2061 return -EOPNOTSUPP;
2062#endif
a4b97ab4 2063 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3e621b19
HHZ		 2064 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2065 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
5ed99fb4 2066 *out_dev = uplink_rpriv->netdev;
3e621b19
HHZ		 2067 else
2068 *out_dev = rt->dst.dev;
a54e20b4 2069
75c33da8 2070 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 2071 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
2072 ip_rt_put(rt);
2073 if (!n)
2074 return -ENOMEM;
2075
2076 *out_n = n;
a54e20b4
HHZ		 2077 return 0;
2078}
2079
ce99f6b9
OG		 2080static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
2081 struct net_device *mirred_dev,
2082 struct net_device **out_dev,
2083 struct flowi6 *fl6,
2084 struct neighbour **out_n,
2085 int *out_ttl)
2086{
2087 struct neighbour *n = NULL;
2088 struct dst_entry *dst;
2089
2090#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
74bd5d56 2091 struct mlx5e_rep_priv *uplink_rpriv;
ce99f6b9
OG		 2092 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2093 int ret;
2094
08820528
PB		 2095 ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
2096 fl6);
2097 if (ret < 0)
ce99f6b9 2098 return ret;
ce99f6b9
OG		 2099
2100 *out_ttl = ip6_dst_hoplimit(dst);
2101
a4b97ab4 2102 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ce99f6b9
OG		 2103 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2104 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
5ed99fb4 2105 *out_dev = uplink_rpriv->netdev;
ce99f6b9
OG		 2106 else
2107 *out_dev = dst->dev;
2108#else
2109 return -EOPNOTSUPP;
2110#endif
2111
2112 n = dst_neigh_lookup(dst, &fl6->daddr);
2113 dst_release(dst);
2114 if (!n)
2115 return -ENOMEM;
2116
2117 *out_n = n;
2118 return 0;
2119}
2120
32f3671f
OG		 2121static void gen_vxlan_header_ipv4(struct net_device *out_dev,
2122 char buf[], int encap_size,
2123 unsigned char h_dest[ETH_ALEN],
2124 int ttl,
2125 __be32 daddr,
2126 __be32 saddr,
2127 __be16 udp_dst_port,
2128 __be32 vx_vni)
a54e20b4 2129{
a54e20b4
HHZ		 2130 struct ethhdr *eth = (struct ethhdr *)buf;
2131 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
2132 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
2133 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2134
2135 memset(buf, 0, encap_size);
2136
2137 ether_addr_copy(eth->h_dest, h_dest);
2138 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2139 eth->h_proto = htons(ETH_P_IP);
2140
2141 ip->daddr = daddr;
2142 ip->saddr = saddr;
2143
2144 ip->ttl = ttl;
2145 ip->protocol = IPPROTO_UDP;
2146 ip->version = 0x4;
2147 ip->ihl = 0x5;
2148
2149 udp->dest = udp_dst_port;
2150 vxh->vx_flags = VXLAN_HF_VNI;
2151 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 2152}
2153
225aabaf
OG		 2154static void gen_vxlan_header_ipv6(struct net_device *out_dev,
2155 char buf[], int encap_size,
2156 unsigned char h_dest[ETH_ALEN],
2157 int ttl,
2158 struct in6_addr *daddr,
2159 struct in6_addr *saddr,
2160 __be16 udp_dst_port,
2161 __be32 vx_vni)
ce99f6b9 2162{
ce99f6b9
OG		 2163 struct ethhdr *eth = (struct ethhdr *)buf;
2164 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
2165 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
2166 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2167
2168 memset(buf, 0, encap_size);
2169
2170 ether_addr_copy(eth->h_dest, h_dest);
2171 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2172 eth->h_proto = htons(ETH_P_IPV6);
2173
2174 ip6_flow_hdr(ip6h, 0, 0);
2175 /* the HW fills up ipv6 payload len */
2176 ip6h->nexthdr = IPPROTO_UDP;
2177 ip6h->hop_limit = ttl;
2178 ip6h->daddr = *daddr;
2179 ip6h->saddr = *saddr;
2180
2181 udp->dest = udp_dst_port;
2182 vxh->vx_flags = VXLAN_HF_VNI;
2183 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 2184}
2185
a54e20b4
HHZ		 2186static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
2187 struct net_device *mirred_dev,
1a8552bd 2188 struct mlx5e_encap_entry *e)
a54e20b4
HHZ		 2189{
2190 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 2191 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 2192 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2193 struct net_device *out_dev;
a42485eb 2194 struct neighbour *n = NULL;
a54e20b4 2195 struct flowi4 fl4 = {};
a54e20b4 2196 char *encap_header;
32f3671f 2197 int ttl, err;
033354d5 2198 u8 nud_state;
32f3671f
OG		 2199
2200 if (max_encap_size < ipv4_encap_size) {
2201 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2202 ipv4_encap_size, max_encap_size);
2203 return -EOPNOTSUPP;
2204 }
a54e20b4 2205
32f3671f 2206 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 2207 if (!encap_header)
2208 return -ENOMEM;
2209
2210 switch (e->tunnel_type) {
2211 case MLX5_HEADER_TYPE_VXLAN:
2212 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 2213 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 2214 break;
2215 default:
2216 err = -EOPNOTSUPP;
ace74321 2217 goto free_encap;
a54e20b4 2218 }
9a941117 2219 fl4.flowi4_tos = tun_key->tos;
76f7444d 2220 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 2221 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 2222
1a8552bd 2223 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 2224 &fl4, &n, &ttl);
a54e20b4 2225 if (err)
ace74321 2226 goto free_encap;
a54e20b4 2227
232c0013
HHZ		 2228 /* used by mlx5e_detach_encap to lookup a neigh hash table
2229 * entry in the neigh hash table when a user deletes a rule
2230 */
2231 e->m_neigh.dev = n->dev;
f6dfb4c3 2232 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2233 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2234 e->out_dev = out_dev;
2235
2236 /* It's importent to add the neigh to the hash table before checking
2237 * the neigh validity state. So if we'll get a notification, in case the
2238 * neigh changes it's validity state, we would find the relevant neigh
2239 * in the hash.
2240 */
2241 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2242 if (err)
ace74321 2243 goto free_encap;
232c0013 2244
033354d5
HHZ		 2245 read_lock_bh(&n->lock);
2246 nud_state = n->nud_state;
2247 ether_addr_copy(e->h_dest, n->ha);
2248 read_unlock_bh(&n->lock);
2249
a54e20b4
HHZ		 2250 switch (e->tunnel_type) {
2251 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 2252 gen_vxlan_header_ipv4(out_dev, encap_header,
32f3671f
OG		 2253 ipv4_encap_size, e->h_dest, ttl,
2254 fl4.daddr,
2255 fl4.saddr, tun_key->tp_dst,
2256 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 2257 break;
2258 default:
2259 err = -EOPNOTSUPP;
232c0013
HHZ		 2260 goto destroy_neigh_entry;
2261 }
2262 e->encap_size = ipv4_encap_size;
2263 e->encap_header = encap_header;
2264
2265 if (!(nud_state & NUD_VALID)) {
2266 neigh_event_send(n, NULL);
27902f08
WY		 2267 err = -EAGAIN;
2268 goto out;
a54e20b4
HHZ		 2269 }
2270
2271 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 2272 ipv4_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 2273 if (err)
2274 goto destroy_neigh_entry;
2275
2276 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2277 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2278 neigh_release(n);
2279 return err;
2280
2281destroy_neigh_entry:
2282 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2283free_encap:
a54e20b4 2284 kfree(encap_header);
ace74321 2285out:
232c0013
HHZ		 2286 if (n)
2287 neigh_release(n);
a54e20b4
HHZ		 2288 return err;
2289}
2290
ce99f6b9
OG		 2291static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2292 struct net_device *mirred_dev,
1a8552bd 2293 struct mlx5e_encap_entry *e)
ce99f6b9
OG		 2294{
2295 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 2296 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 2297 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2298 struct net_device *out_dev;
ce99f6b9
OG		 2299 struct neighbour *n = NULL;
2300 struct flowi6 fl6 = {};
2301 char *encap_header;
225aabaf 2302 int err, ttl = 0;
033354d5 2303 u8 nud_state;
ce99f6b9 2304
225aabaf
OG		 2305 if (max_encap_size < ipv6_encap_size) {
2306 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2307 ipv6_encap_size, max_encap_size);
2308 return -EOPNOTSUPP;
2309 }
ce99f6b9 2310
225aabaf 2311 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 2312 if (!encap_header)
2313 return -ENOMEM;
2314
2315 switch (e->tunnel_type) {
2316 case MLX5_HEADER_TYPE_VXLAN:
2317 fl6.flowi6_proto = IPPROTO_UDP;
2318 fl6.fl6_dport = tun_key->tp_dst;
2319 break;
2320 default:
2321 err = -EOPNOTSUPP;
ace74321 2322 goto free_encap;
ce99f6b9
OG		 2323 }
2324
2325 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2326 fl6.daddr = tun_key->u.ipv6.dst;
2327 fl6.saddr = tun_key->u.ipv6.src;
2328
1a8552bd 2329 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG		 2330 &fl6, &n, &ttl);
2331 if (err)
ace74321 2332 goto free_encap;
ce99f6b9 2333
232c0013
HHZ		 2334 /* used by mlx5e_detach_encap to lookup a neigh hash table
2335 * entry in the neigh hash table when a user deletes a rule
2336 */
2337 e->m_neigh.dev = n->dev;
f6dfb4c3 2338 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2339 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2340 e->out_dev = out_dev;
2341
2342 /* It's importent to add the neigh to the hash table before checking
2343 * the neigh validity state. So if we'll get a notification, in case the
2344 * neigh changes it's validity state, we would find the relevant neigh
2345 * in the hash.
2346 */
2347 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2348 if (err)
ace74321 2349 goto free_encap;
232c0013 2350
033354d5
HHZ		 2351 read_lock_bh(&n->lock);
2352 nud_state = n->nud_state;
2353 ether_addr_copy(e->h_dest, n->ha);
2354 read_unlock_bh(&n->lock);
2355
ce99f6b9
OG		 2356 switch (e->tunnel_type) {
2357 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 2358 gen_vxlan_header_ipv6(out_dev, encap_header,
225aabaf
OG		 2359 ipv6_encap_size, e->h_dest, ttl,
2360 &fl6.daddr,
2361 &fl6.saddr, tun_key->tp_dst,
2362 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 2363 break;
2364 default:
2365 err = -EOPNOTSUPP;
232c0013
HHZ		 2366 goto destroy_neigh_entry;
2367 }
2368
2369 e->encap_size = ipv6_encap_size;
2370 e->encap_header = encap_header;
2371
2372 if (!(nud_state & NUD_VALID)) {
2373 neigh_event_send(n, NULL);
27902f08
WY		 2374 err = -EAGAIN;
2375 goto out;
ce99f6b9
OG		 2376 }
2377
2378 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 2379 ipv6_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 2380 if (err)
2381 goto destroy_neigh_entry;
2382
2383 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2384 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2385 neigh_release(n);
2386 return err;
2387
2388destroy_neigh_entry:
2389 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2390free_encap:
ce99f6b9 2391 kfree(encap_header);
ace74321 2392out:
232c0013
HHZ		 2393 if (n)
2394 neigh_release(n);
ce99f6b9
OG		 2395 return err;
2396}
2397
a54e20b4
HHZ		 2398static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2399 struct ip_tunnel_info *tun_info,
2400 struct net_device *mirred_dev,
45247bf2
OG		 2401 struct net_device **encap_dev,
2402 struct mlx5e_tc_flow *flow)
a54e20b4
HHZ		 2403{
2404 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4
MB		 2405 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw,
2406 REP_ETH);
5ed99fb4 2407 struct net_device *up_dev = uplink_rpriv->netdev;
a54e20b4 2408 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2
OG		 2409 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
2410 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2411 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2412 struct mlx5e_encap_entry *e;
45247bf2 2413 int tunnel_type, err = 0;
a54e20b4
HHZ		 2414 uintptr_t hash_key;
2415 bool found = false;
a54e20b4 2416
2fcd82e9 2417 /* udp dst port must be set */
a54e20b4 2418 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 2419 goto vxlan_encap_offload_err;
a54e20b4 2420
cd377663 2421 /* setting udp src port isn't supported */
2fcd82e9
OG		 2422 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2423vxlan_encap_offload_err:
2424 netdev_warn(priv->netdev,
2425 "must set udp dst port and not set udp src port\n");
cd377663 2426 return -EOPNOTSUPP;
2fcd82e9 2427 }
cd377663 2428
1ad9a00a 2429 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 2430 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ		 2431 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
2432 } else {
2fcd82e9
OG		 2433 netdev_warn(priv->netdev,
2434 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 2435 return -EOPNOTSUPP;
2436 }
2437
76f7444d 2438 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2439
2440 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2441 encap_hlist, hash_key) {
76f7444d 2442 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2443 found = true;
2444 break;
2445 }
2446 }
2447
b2812089 2448 /* must verify if encap is valid or not */
45247bf2
OG		 2449 if (found)
2450 goto attach_flow;
a54e20b4
HHZ		 2451
2452 e = kzalloc(sizeof(*e), GFP_KERNEL);
2453 if (!e)
2454 return -ENOMEM;
2455
76f7444d 2456 e->tun_info = *tun_info;
a54e20b4
HHZ		 2457 e->tunnel_type = tunnel_type;
2458 INIT_LIST_HEAD(&e->flows);
2459
ce99f6b9 2460 if (family == AF_INET)
1a8552bd 2461 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2462 else if (family == AF_INET6)
1a8552bd 2463 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2464
232c0013 2465 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2466 goto out_err;
2467
a54e20b4
HHZ		 2468 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2469
45247bf2
OG		 2470attach_flow:
2471 list_add(&flow->encap, &e->flows);
2472 *encap_dev = e->out_dev;
232c0013
HHZ		 2473 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2474 attr->encap_id = e->encap_id;
b2812089
VB		 2475 else
2476 err = -EAGAIN;
45247bf2 2477
232c0013 2478 return err;
a54e20b4
HHZ		 2479
2480out_err:
2481 kfree(e);
2482 return err;
2483}
2484
03a9d11e 2485static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 2486 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 2487 struct mlx5e_tc_flow *flow)
03a9d11e 2488{
ecf5bb79 2489 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2490 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 2491 struct ip_tunnel_info *info = NULL;
03a9d11e 2492 const struct tc_action *a;
22dc13c8 2493 LIST_HEAD(actions);
a54e20b4 2494 bool encap = false;
1cab1cd7 2495 u32 action = 0;
03a9d11e 2496
3bcc0cec 2497 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 2498 return -EINVAL;
2499
1d447a39 2500 attr->in_rep = rpriv->rep;
10ff5359 2501 attr->in_mdev = priv->mdev;
03a9d11e 2502
22dc13c8
WC		 2503 tcf_exts_to_list(exts, &actions);
2504 list_for_each_entry(a, &actions, list) {
03a9d11e 2505 if (is_tcf_gact_shot(a)) {
1cab1cd7
OG		 2506 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2507 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 2508 continue;
2509 }
2510
d7e75a32 2511 if (is_tcf_pedit(a)) {
31c8eba5
OG		 2512 int err;
2513
d7e75a32
OG		 2514 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
2515 parse_attr);
2516 if (err)
2517 return err;
2518
1cab1cd7 2519 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
d7e75a32
OG		 2520 continue;
2521 }
2522
26c02749 2523 if (is_tcf_csum(a)) {
1cab1cd7 2524 if (csum_offload_supported(priv, action,
26c02749
OG		 2525 tcf_csum_update_flags(a)))
2526 continue;
2527
2528 return -EOPNOTSUPP;
2529 }
2530
5724b8b5 2531 if (is_tcf_mirred_egress_redirect(a)) {
3c37745e 2532 struct net_device *out_dev;
03a9d11e 2533 struct mlx5e_priv *out_priv;
03a9d11e 2534
9f8a739e 2535 out_dev = tcf_mirred_dev(a);
03a9d11e 2536
a54e20b4
HHZ		 2537 if (switchdev_port_same_parent_id(priv->netdev,
2538 out_dev)) {
1cab1cd7
OG		 2539 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2540 MLX5_FLOW_CONTEXT_ACTION_COUNT;
a54e20b4 2541 out_priv = netdev_priv(out_dev);
1d447a39
SM		 2542 rpriv = out_priv->ppriv;
2543 attr->out_rep = rpriv->rep;
56e858df 2544 attr->out_mdev = out_priv->mdev;
a54e20b4 2545 } else if (encap) {
9f8a739e 2546 parse_attr->mirred_ifindex = out_dev->ifindex;
3c37745e
OG		 2547 parse_attr->tun_info = *info;
2548 attr->parse_attr = parse_attr;
1cab1cd7
OG		 2549 action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
2550 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2551 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3c37745e 2552 /* attr->out_rep is resolved when we handle encap */
a54e20b4 2553 } else {
03a9d11e
OG		 2554 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2555 priv->netdev->name, out_dev->name);
2556 return -EINVAL;
2557 }
a54e20b4
HHZ		 2558 continue;
2559 }
03a9d11e 2560
a54e20b4
HHZ		 2561 if (is_tcf_tunnel_set(a)) {
2562 info = tcf_tunnel_info(a);
2563 if (info)
2564 encap = true;
2565 else
2566 return -EOPNOTSUPP;
03a9d11e
OG		 2567 continue;
2568 }
2569
8b32580d 2570 if (is_tcf_vlan(a)) {
09c91ddf 2571 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
1cab1cd7 2572 action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 2573 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
1cab1cd7 2574 action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
6acfbf38
OG		 2575 attr->vlan_vid = tcf_vlan_push_vid(a);
2576 if (mlx5_eswitch_vlan_actions_supported(priv->mdev)) {
2577 attr->vlan_prio = tcf_vlan_push_prio(a);
2578 attr->vlan_proto = tcf_vlan_push_proto(a);
2579 if (!attr->vlan_proto)
2580 attr->vlan_proto = htons(ETH_P_8021Q);
2581 } else if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2582 tcf_vlan_push_prio(a)) {
2583 return -EOPNOTSUPP;
2584 }
09c91ddf
OG		 2585 } else { /* action is TCA_VLAN_ACT_MODIFY */
2586 return -EOPNOTSUPP;
8b32580d
OG		 2587 }
2588 continue;
2589 }
2590
bbd00f7e 2591 if (is_tcf_tunnel_release(a)) {
1cab1cd7 2592 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bbd00f7e
HHZ		 2593 continue;
2594 }
2595
03a9d11e
OG		 2596 return -EINVAL;
2597 }
bdd66ac0 2598
1cab1cd7 2599 attr->action = action;
bdd66ac0
OG		 2600 if (!actions_match_supported(priv, exts, parse_attr, flow))
2601 return -EOPNOTSUPP;
2602
31c8eba5 2603 return 0;
03a9d11e
OG		 2604}
2605
5fd9fc4e 2606int mlx5e_configure_flower(struct mlx5e_priv *priv,
e3a2b7ed
AV		 2607 struct tc_cls_flower_offload *f)
2608{
3bc4b7bf 2609 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 2610 struct mlx5e_tc_flow_parse_attr *parse_attr;
acff797c 2611 struct mlx5e_tc_table *tc = &priv->fs.tc;
3bc4b7bf
OG		 2612 struct mlx5e_tc_flow *flow;
2613 int attr_size, err = 0;
65ba8fb7 2614 u8 flow_flags = 0;
e3a2b7ed 2615
65ba8fb7
OG		 2616 if (esw && esw->mode == SRIOV_OFFLOADS) {
2617 flow_flags = MLX5E_TC_FLOW_ESWITCH;
2618 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf
OG		 2619 } else {
2620 flow_flags = MLX5E_TC_FLOW_NIC;
2621 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 2622 }
e3a2b7ed 2623
65ba8fb7 2624 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2625 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2626 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2627 err = -ENOMEM;
2628 goto err_free;
2629 }
2630
2631 flow->cookie = f->cookie;
65ba8fb7 2632 flow->flags = flow_flags;
e3a2b7ed 2633
17091853 2634 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV		 2635 if (err < 0)
2636 goto err_free;
2637
65ba8fb7 2638 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 2639 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123 2640 if (err < 0)
3c37745e 2641 goto err_free;
aa0cbbae 2642 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 2643 } else {
aa0cbbae 2644 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG		 2645 if (err < 0)
2646 goto err_free;
aa0cbbae 2647 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 2648 }
e3a2b7ed 2649
e3a2b7ed
AV		 2650 if (IS_ERR(flow->rule)) {
2651 err = PTR_ERR(flow->rule);
3c37745e
OG		 2652 if (err != -EAGAIN)
2653 goto err_free;
e3a2b7ed
AV		 2654 }
2655
3c37745e
OG		 2656 if (err != -EAGAIN)
2657 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2658
af1607c3
JL		 2659 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
2660 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
2661 kvfree(parse_attr);
2662
5c40348c
OG		 2663 err = rhashtable_insert_fast(&tc->ht, &flow->node,
2664 tc->ht_params);
af1607c3
JL		 2665 if (err) {
2666 mlx5e_tc_del_flow(priv, flow);
2667 kfree(flow);
2668 }
5c40348c 2669
232c0013 2670 return err;
e3a2b7ed 2671
e3a2b7ed 2672err_free:
17091853 2673 kvfree(parse_attr);
232c0013 2674 kfree(flow);
e3a2b7ed
AV		 2675 return err;
2676}
2677
2678int mlx5e_delete_flower(struct mlx5e_priv *priv,
2679 struct tc_cls_flower_offload *f)
2680{
2681 struct mlx5e_tc_flow *flow;
acff797c 2682 struct mlx5e_tc_table *tc = &priv->fs.tc;
e3a2b7ed
AV		 2683
2684 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2685 tc->ht_params);
2686 if (!flow)
2687 return -EINVAL;
2688
2689 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
2690
961e8979 2691 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 2692
2693 kfree(flow);
2694
2695 return 0;
2696}
2697
aad7e08d
AV		 2698int mlx5e_stats_flower(struct mlx5e_priv *priv,
2699 struct tc_cls_flower_offload *f)
2700{
2701 struct mlx5e_tc_table *tc = &priv->fs.tc;
2702 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 2703 struct mlx5_fc *counter;
2704 u64 bytes;
2705 u64 packets;
2706 u64 lastuse;
2707
2708 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2709 tc->ht_params);
2710 if (!flow)
2711 return -EINVAL;
2712
0b67a38f
HHZ		 2713 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2714 return 0;
2715
aad7e08d
AV		 2716 counter = mlx5_flow_rule_counter(flow->rule);
2717 if (!counter)
2718 return 0;
2719
2720 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2721
d897a638 2722 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 2723
aad7e08d
AV		 2724 return 0;
2725}
2726
e8f887ac
AV		 2727static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
2728 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2729 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2730 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2731 .automatic_shrinking = true,
2732};
2733
2734int mlx5e_tc_init(struct mlx5e_priv *priv)
2735{
acff797c 2736 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 2737
11c9c548 2738 hash_init(tc->mod_hdr_tbl);
5c65c564 2739 hash_init(tc->hairpin_tbl);
11c9c548 2740
e8f887ac
AV		 2741 tc->ht_params = mlx5e_tc_flow_ht_params;
2742 return rhashtable_init(&tc->ht, &tc->ht_params);
2743}
2744
2745static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2746{
2747 struct mlx5e_tc_flow *flow = ptr;
2748 struct mlx5e_priv *priv = arg;
2749
961e8979 2750 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 2751 kfree(flow);
2752}
2753
2754void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
2755{
acff797c 2756 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV		 2757
2758 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
2759
acff797c
MG		 2760 if (!IS_ERR_OR_NULL(tc->t)) {
2761 mlx5_destroy_flow_table(tc->t);
2762 tc->t = NULL;
e8f887ac
AV		 2763 }
2764}
Linux 6.x block layer and io_uring tree(s)