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net/mlx5: Add source e-switch owner
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
bbd00f7e 53#include "vxlan.h"
3f6d08d1 54#include "fs_core.h"
e8f887ac 55
3bc4b7bf
OG		 56struct mlx5_nic_flow_attr {
57 u32 action;
58 u32 flow_tag;
2f4fe4ca 59 u32 mod_hdr_id;
5c65c564 60 u32 hairpin_tirn;
3f6d08d1 61 struct mlx5_flow_table *hairpin_ft;
3bc4b7bf
OG		 62};
63
65ba8fb7
OG		 64enum {
65 MLX5E_TC_FLOW_ESWITCH = BIT(0),
3bc4b7bf 66 MLX5E_TC_FLOW_NIC = BIT(1),
0b67a38f 67 MLX5E_TC_FLOW_OFFLOADED = BIT(2),
5c65c564 68 MLX5E_TC_FLOW_HAIRPIN = BIT(3),
3f6d08d1 69 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(4),
65ba8fb7
OG		 70};
71
e8f887ac
AV		 72struct mlx5e_tc_flow {
73 struct rhash_head node;
74 u64 cookie;
65ba8fb7 75 u8 flags;
74491de9 76 struct mlx5_flow_handle *rule;
11c9c548
OG		 77 struct list_head encap; /* flows sharing the same encap ID */
78 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 79 struct list_head hairpin; /* flows sharing the same hairpin */
3bc4b7bf
OG		 80 union {
81 struct mlx5_esw_flow_attr esw_attr[0];
82 struct mlx5_nic_flow_attr nic_attr[0];
83 };
e8f887ac
AV		 84};
85
17091853 86struct mlx5e_tc_flow_parse_attr {
3c37745e 87 struct ip_tunnel_info tun_info;
17091853 88 struct mlx5_flow_spec spec;
d79b6df6
OG		 89 int num_mod_hdr_actions;
90 void *mod_hdr_actions;
3c37745e 91 int mirred_ifindex;
17091853
OG		 92};
93
a54e20b4
HHZ		 94enum {
95 MLX5_HEADER_TYPE_VXLAN = 0x0,
96 MLX5_HEADER_TYPE_NVGRE = 0x1,
97};
98
acff797c 99#define MLX5E_TC_TABLE_NUM_GROUPS 4
21b9c144 100#define MLX5E_TC_TABLE_MAX_GROUP_SIZE (1 << 16)
e8f887ac 101
77ab67b7
OG		 102struct mlx5e_hairpin {
103 struct mlx5_hairpin *pair;
104
105 struct mlx5_core_dev *func_mdev;
3f6d08d1 106 struct mlx5e_priv *func_priv;
77ab67b7
OG		 107 u32 tdn;
108 u32 tirn;
3f6d08d1
OG		 109
110 int num_channels;
111 struct mlx5e_rqt indir_rqt;
112 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
113 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 114};
115
5c65c564
OG		 116struct mlx5e_hairpin_entry {
117 /* a node of a hash table which keeps all the hairpin entries */
118 struct hlist_node hairpin_hlist;
119
120 /* flows sharing the same hairpin */
121 struct list_head flows;
122
d8822868 123 u16 peer_vhca_id;
106be53b 124 u8 prio;
5c65c564
OG		 125 struct mlx5e_hairpin *hp;
126};
127
11c9c548
OG		 128struct mod_hdr_key {
129 int num_actions;
130 void *actions;
131};
132
133struct mlx5e_mod_hdr_entry {
134 /* a node of a hash table which keeps all the mod_hdr entries */
135 struct hlist_node mod_hdr_hlist;
136
137 /* flows sharing the same mod_hdr entry */
138 struct list_head flows;
139
140 struct mod_hdr_key key;
141
142 u32 mod_hdr_id;
143};
144
145#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
146
147static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
148{
149 return jhash(key->actions,
150 key->num_actions * MLX5_MH_ACT_SZ, 0);
151}
152
153static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
154 struct mod_hdr_key *b)
155{
156 if (a->num_actions != b->num_actions)
157 return 1;
158
159 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
160}
161
162static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
163 struct mlx5e_tc_flow *flow,
164 struct mlx5e_tc_flow_parse_attr *parse_attr)
165{
166 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
167 int num_actions, actions_size, namespace, err;
168 struct mlx5e_mod_hdr_entry *mh;
169 struct mod_hdr_key key;
170 bool found = false;
171 u32 hash_key;
172
173 num_actions = parse_attr->num_mod_hdr_actions;
174 actions_size = MLX5_MH_ACT_SZ * num_actions;
175
176 key.actions = parse_attr->mod_hdr_actions;
177 key.num_actions = num_actions;
178
179 hash_key = hash_mod_hdr_info(&key);
180
181 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
182 namespace = MLX5_FLOW_NAMESPACE_FDB;
183 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
184 mod_hdr_hlist, hash_key) {
185 if (!cmp_mod_hdr_info(&mh->key, &key)) {
186 found = true;
187 break;
188 }
189 }
190 } else {
191 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
192 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
193 mod_hdr_hlist, hash_key) {
194 if (!cmp_mod_hdr_info(&mh->key, &key)) {
195 found = true;
196 break;
197 }
198 }
199 }
200
201 if (found)
202 goto attach_flow;
203
204 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
205 if (!mh)
206 return -ENOMEM;
207
208 mh->key.actions = (void *)mh + sizeof(*mh);
209 memcpy(mh->key.actions, key.actions, actions_size);
210 mh->key.num_actions = num_actions;
211 INIT_LIST_HEAD(&mh->flows);
212
213 err = mlx5_modify_header_alloc(priv->mdev, namespace,
214 mh->key.num_actions,
215 mh->key.actions,
216 &mh->mod_hdr_id);
217 if (err)
218 goto out_err;
219
220 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
221 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
222 else
223 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
224
225attach_flow:
226 list_add(&flow->mod_hdr, &mh->flows);
227 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
228 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
229 else
230 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
231
232 return 0;
233
234out_err:
235 kfree(mh);
236 return err;
237}
238
239static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
240 struct mlx5e_tc_flow *flow)
241{
242 struct list_head *next = flow->mod_hdr.next;
243
244 list_del(&flow->mod_hdr);
245
246 if (list_empty(next)) {
247 struct mlx5e_mod_hdr_entry *mh;
248
249 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
250
251 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
252 hash_del(&mh->mod_hdr_hlist);
253 kfree(mh);
254 }
255}
256
77ab67b7
OG		 257static
258struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
259{
260 struct net_device *netdev;
261 struct mlx5e_priv *priv;
262
263 netdev = __dev_get_by_index(net, ifindex);
264 priv = netdev_priv(netdev);
265 return priv->mdev;
266}
267
268static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
269{
270 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
271 void *tirc;
272 int err;
273
274 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
275 if (err)
276 goto alloc_tdn_err;
277
278 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
279
280 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 281 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 282 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
283
284 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
285 if (err)
286 goto create_tir_err;
287
288 return 0;
289
290create_tir_err:
291 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
292alloc_tdn_err:
293 return err;
294}
295
296static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
297{
298 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
299 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
300}
301
3f6d08d1
OG		 302static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
303{
304 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
305 struct mlx5e_priv *priv = hp->func_priv;
306 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
307
308 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
309 hp->num_channels);
310
311 for (i = 0; i < sz; i++) {
312 ix = i;
313 if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR)
314 ix = mlx5e_bits_invert(i, ilog2(sz));
315 ix = indirection_rqt[ix];
316 rqn = hp->pair->rqn[ix];
317 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
318 }
319}
320
321static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
322{
323 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
324 struct mlx5e_priv *priv = hp->func_priv;
325 struct mlx5_core_dev *mdev = priv->mdev;
326 void *rqtc;
327 u32 *in;
328
329 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
330 in = kvzalloc(inlen, GFP_KERNEL);
331 if (!in)
332 return -ENOMEM;
333
334 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
335
336 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
337 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
338
339 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
340
341 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
342 if (!err)
343 hp->indir_rqt.enabled = true;
344
345 kvfree(in);
346 return err;
347}
348
349static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
350{
351 struct mlx5e_priv *priv = hp->func_priv;
352 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
353 int tt, i, err;
354 void *tirc;
355
356 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
357 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
358 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
359
360 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
361 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
362 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
363 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
364
365 err = mlx5_core_create_tir(hp->func_mdev, in,
366 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
367 if (err) {
368 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
369 goto err_destroy_tirs;
370 }
371 }
372 return 0;
373
374err_destroy_tirs:
375 for (i = 0; i < tt; i++)
376 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
377 return err;
378}
379
380static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
381{
382 int tt;
383
384 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
385 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
386}
387
388static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
389 struct ttc_params *ttc_params)
390{
391 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
392 int tt;
393
394 memset(ttc_params, 0, sizeof(*ttc_params));
395
396 ttc_params->any_tt_tirn = hp->tirn;
397
398 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
399 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
400
401 ft_attr->max_fte = MLX5E_NUM_TT;
402 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
403 ft_attr->prio = MLX5E_TC_PRIO;
404}
405
406static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
407{
408 struct mlx5e_priv *priv = hp->func_priv;
409 struct ttc_params ttc_params;
410 int err;
411
412 err = mlx5e_hairpin_create_indirect_rqt(hp);
413 if (err)
414 return err;
415
416 err = mlx5e_hairpin_create_indirect_tirs(hp);
417 if (err)
418 goto err_create_indirect_tirs;
419
420 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
421 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
422 if (err)
423 goto err_create_ttc_table;
424
425 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
426 hp->num_channels, hp->ttc.ft.t->id);
427
428 return 0;
429
430err_create_ttc_table:
431 mlx5e_hairpin_destroy_indirect_tirs(hp);
432err_create_indirect_tirs:
433 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
434
435 return err;
436}
437
438static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
439{
440 struct mlx5e_priv *priv = hp->func_priv;
441
442 mlx5e_destroy_ttc_table(priv, &hp->ttc);
443 mlx5e_hairpin_destroy_indirect_tirs(hp);
444 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
445}
446
77ab67b7
OG		 447static struct mlx5e_hairpin *
448mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
449 int peer_ifindex)
450{
451 struct mlx5_core_dev *func_mdev, *peer_mdev;
452 struct mlx5e_hairpin *hp;
453 struct mlx5_hairpin *pair;
454 int err;
455
456 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
457 if (!hp)
458 return ERR_PTR(-ENOMEM);
459
460 func_mdev = priv->mdev;
461 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
462
463 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
464 if (IS_ERR(pair)) {
465 err = PTR_ERR(pair);
466 goto create_pair_err;
467 }
468 hp->pair = pair;
469 hp->func_mdev = func_mdev;
3f6d08d1
OG		 470 hp->func_priv = priv;
471 hp->num_channels = params->num_channels;
77ab67b7
OG		 472
473 err = mlx5e_hairpin_create_transport(hp);
474 if (err)
475 goto create_transport_err;
476
3f6d08d1
OG		 477 if (hp->num_channels > 1) {
478 err = mlx5e_hairpin_rss_init(hp);
479 if (err)
480 goto rss_init_err;
481 }
482
77ab67b7
OG		 483 return hp;
484
3f6d08d1
OG		 485rss_init_err:
486 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 487create_transport_err:
488 mlx5_core_hairpin_destroy(hp->pair);
489create_pair_err:
490 kfree(hp);
491 return ERR_PTR(err);
492}
493
494static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
495{
3f6d08d1
OG		 496 if (hp->num_channels > 1)
497 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 498 mlx5e_hairpin_destroy_transport(hp);
499 mlx5_core_hairpin_destroy(hp->pair);
500 kvfree(hp);
501}
502
106be53b
OG		 503static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
504{
505 return (peer_vhca_id << 16 | prio);
506}
507
5c65c564 508static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 509 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 510{
511 struct mlx5e_hairpin_entry *hpe;
106be53b 512 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 513
514 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 515 hairpin_hlist, hash_key) {
516 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 517 return hpe;
518 }
519
520 return NULL;
521}
522
106be53b
OG		 523#define UNKNOWN_MATCH_PRIO 8
524
525static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
526 struct mlx5_flow_spec *spec, u8 *match_prio)
527{
528 void *headers_c, *headers_v;
529 u8 prio_val, prio_mask = 0;
530 bool vlan_present;
531
532#ifdef CONFIG_MLX5_CORE_EN_DCB
533 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
534 netdev_warn(priv->netdev,
535 "only PCP trust state supported for hairpin\n");
536 return -EOPNOTSUPP;
537 }
538#endif
539 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
540 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
541
542 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
543 if (vlan_present) {
544 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
545 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
546 }
547
548 if (!vlan_present || !prio_mask) {
549 prio_val = UNKNOWN_MATCH_PRIO;
550 } else if (prio_mask != 0x7) {
551 netdev_warn(priv->netdev,
552 "masked priority match not supported for hairpin\n");
553 return -EOPNOTSUPP;
554 }
555
556 *match_prio = prio_val;
557 return 0;
558}
559
5c65c564
OG		 560static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
561 struct mlx5e_tc_flow *flow,
562 struct mlx5e_tc_flow_parse_attr *parse_attr)
563{
564 int peer_ifindex = parse_attr->mirred_ifindex;
565 struct mlx5_hairpin_params params;
d8822868 566 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 567 struct mlx5e_hairpin_entry *hpe;
568 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 569 u64 link_speed64;
570 u32 link_speed;
106be53b 571 u8 match_prio;
d8822868 572 u16 peer_id;
5c65c564
OG		 573 int err;
574
d8822868
OG		 575 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
576 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
5c65c564
OG		 577 netdev_warn(priv->netdev, "hairpin is not supported\n");
578 return -EOPNOTSUPP;
579 }
580
d8822868 581 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
106be53b
OG		 582 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio);
583 if (err)
584 return err;
585 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 586 if (hpe)
587 goto attach_flow;
588
589 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
590 if (!hpe)
591 return -ENOMEM;
592
593 INIT_LIST_HEAD(&hpe->flows);
d8822868 594 hpe->peer_vhca_id = peer_id;
106be53b 595 hpe->prio = match_prio;
5c65c564
OG		 596
597 params.log_data_size = 15;
598 params.log_data_size = min_t(u8, params.log_data_size,
599 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
600 params.log_data_size = max_t(u8, params.log_data_size,
601 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 602
eb9180f7
OG		 603 params.log_num_packets = params.log_data_size -
604 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
605 params.log_num_packets = min_t(u8, params.log_num_packets,
606 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
607
608 params.q_counter = priv->q_counter;
3f6d08d1
OG		 609 /* set hairpin pair per each 50Gbs share of the link */
610 mlx5e_get_max_linkspeed(priv->mdev, &link_speed);
611 link_speed = max_t(u32, link_speed, 50000);
612 link_speed64 = link_speed;
613 do_div(link_speed64, 50000);
614 params.num_channels = link_speed64;
615
5c65c564
OG		 616 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
617 if (IS_ERR(hp)) {
618 err = PTR_ERR(hp);
619 goto create_hairpin_err;
620 }
621
eb9180f7 622 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 623 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 624 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 625
626 hpe->hp = hp;
106be53b
OG		 627 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
628 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 629
630attach_flow:
3f6d08d1
OG		 631 if (hpe->hp->num_channels > 1) {
632 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
633 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
634 } else {
635 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
636 }
5c65c564 637 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 638
5c65c564
OG		 639 return 0;
640
641create_hairpin_err:
642 kfree(hpe);
643 return err;
644}
645
646static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
647 struct mlx5e_tc_flow *flow)
648{
649 struct list_head *next = flow->hairpin.next;
650
651 list_del(&flow->hairpin);
652
653 /* no more hairpin flows for us, release the hairpin pair */
654 if (list_empty(next)) {
655 struct mlx5e_hairpin_entry *hpe;
656
657 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
658
659 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
660 hpe->hp->pair->peer_mdev->priv.name);
661
662 mlx5e_hairpin_destroy(hpe->hp);
663 hash_del(&hpe->hairpin_hlist);
664 kfree(hpe);
665 }
666}
667
74491de9
MB		 668static struct mlx5_flow_handle *
669mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 670 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 671 struct mlx5e_tc_flow *flow)
e8f887ac 672{
aa0cbbae 673 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 674 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 675 struct mlx5_flow_destination dest[2] = {};
66958ed9 676 struct mlx5_flow_act flow_act = {
3bc4b7bf 677 .action = attr->action,
a9db0ecf 678 .has_flow_tag = true,
3bc4b7bf 679 .flow_tag = attr->flow_tag,
66958ed9
HHZ		 680 .encap_id = 0,
681 };
aad7e08d 682 struct mlx5_fc *counter = NULL;
74491de9 683 struct mlx5_flow_handle *rule;
e8f887ac 684 bool table_created = false;
5c65c564 685 int err, dest_ix = 0;
e8f887ac 686
3f6d08d1
OG		 687 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
688 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr);
689 if (err) {
690 rule = ERR_PTR(err);
691 goto err_add_hairpin_flow;
692 }
693 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
694 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
695 dest[dest_ix].ft = attr->hairpin_ft;
696 } else {
5c65c564
OG		 697 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
698 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 699 }
700 dest_ix++;
3f6d08d1
OG		 701 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
702 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
703 dest[dest_ix].ft = priv->fs.vlan.ft.t;
704 dest_ix++;
5c65c564 705 }
aad7e08d 706
5c65c564
OG		 707 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
708 counter = mlx5_fc_create(dev, true);
709 if (IS_ERR(counter)) {
710 rule = ERR_CAST(counter);
711 goto err_fc_create;
712 }
713 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
714 dest[dest_ix].counter = counter;
715 dest_ix++;
aad7e08d
AV		 716 }
717
2f4fe4ca 718 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 719 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 720 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG		 721 kfree(parse_attr->mod_hdr_actions);
722 if (err) {
723 rule = ERR_PTR(err);
724 goto err_create_mod_hdr_id;
725 }
726 }
727
acff797c 728 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 729 int tc_grp_size, tc_tbl_size;
730 u32 max_flow_counter;
731
732 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
733 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
734
735 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
736
737 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
738 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
739
acff797c
MG		 740 priv->fs.tc.t =
741 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
742 MLX5E_TC_PRIO,
21b9c144 743 tc_tbl_size,
acff797c 744 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 745 MLX5E_TC_FT_LEVEL, 0);
acff797c 746 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV		 747 netdev_err(priv->netdev,
748 "Failed to create tc offload table\n");
aad7e08d
AV		 749 rule = ERR_CAST(priv->fs.tc.t);
750 goto err_create_ft;
e8f887ac
AV		 751 }
752
753 table_created = true;
754 }
755
17091853
OG		 756 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
757 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
5c65c564 758 &flow_act, dest, dest_ix);
aad7e08d
AV		 759
760 if (IS_ERR(rule))
761 goto err_add_rule;
762
763 return rule;
e8f887ac 764
aad7e08d
AV		 765err_add_rule:
766 if (table_created) {
acff797c
MG		 767 mlx5_destroy_flow_table(priv->fs.tc.t);
768 priv->fs.tc.t = NULL;
e8f887ac 769 }
aad7e08d 770err_create_ft:
2f4fe4ca 771 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 772 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 773err_create_mod_hdr_id:
aad7e08d 774 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 775err_fc_create:
776 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
777 mlx5e_hairpin_flow_del(priv, flow);
778err_add_hairpin_flow:
e8f887ac
AV		 779 return rule;
780}
781
d85cdccb
OG		 782static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
783 struct mlx5e_tc_flow *flow)
784{
513f8f7f 785 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 786 struct mlx5_fc *counter = NULL;
787
aa0cbbae
OG		 788 counter = mlx5_flow_rule_counter(flow->rule);
789 mlx5_del_flow_rules(flow->rule);
790 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb
OG		 791
792 if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
793 mlx5_destroy_flow_table(priv->fs.tc.t);
794 priv->fs.tc.t = NULL;
795 }
2f4fe4ca 796
513f8f7f 797 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 798 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 799
800 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
801 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 802}
803
aa0cbbae
OG		 804static void mlx5e_detach_encap(struct mlx5e_priv *priv,
805 struct mlx5e_tc_flow *flow);
806
3c37745e
OG		 807static int mlx5e_attach_encap(struct mlx5e_priv *priv,
808 struct ip_tunnel_info *tun_info,
809 struct net_device *mirred_dev,
810 struct net_device **encap_dev,
811 struct mlx5e_tc_flow *flow);
812
74491de9
MB		 813static struct mlx5_flow_handle *
814mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 815 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 816 struct mlx5e_tc_flow *flow)
adb4c123
OG		 817{
818 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 819 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3c37745e
OG		 820 struct net_device *out_dev, *encap_dev = NULL;
821 struct mlx5_flow_handle *rule = NULL;
822 struct mlx5e_rep_priv *rpriv;
823 struct mlx5e_priv *out_priv;
8b32580d
OG		 824 int err;
825
3c37745e
OG		 826 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
827 out_dev = __dev_get_by_index(dev_net(priv->netdev),
828 attr->parse_attr->mirred_ifindex);
829 err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
830 out_dev, &encap_dev, flow);
831 if (err) {
832 rule = ERR_PTR(err);
833 if (err != -EAGAIN)
834 goto err_attach_encap;
835 }
836 out_priv = netdev_priv(encap_dev);
837 rpriv = out_priv->ppriv;
838 attr->out_rep = rpriv->rep;
56e858df 839 attr->out_mdev = out_priv->mdev;
3c37745e
OG		 840 }
841
8b32580d 842 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG		 843 if (err) {
844 rule = ERR_PTR(err);
845 goto err_add_vlan;
846 }
adb4c123 847
d7e75a32 848 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 849 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32
OG		 850 kfree(parse_attr->mod_hdr_actions);
851 if (err) {
852 rule = ERR_PTR(err);
853 goto err_mod_hdr;
854 }
855 }
856
3c37745e
OG		 857 /* we get here if (1) there's no error (rule being null) or when
858 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
859 */
860 if (rule != ERR_PTR(-EAGAIN)) {
861 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
862 if (IS_ERR(rule))
863 goto err_add_rule;
864 }
aa0cbbae
OG		 865 return rule;
866
867err_add_rule:
513f8f7f 868 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 869 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 870err_mod_hdr:
aa0cbbae
OG		 871 mlx5_eswitch_del_vlan_action(esw, attr);
872err_add_vlan:
873 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
874 mlx5e_detach_encap(priv, flow);
3c37745e 875err_attach_encap:
aa0cbbae
OG		 876 return rule;
877}
d85cdccb
OG		 878
879static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
880 struct mlx5e_tc_flow *flow)
881{
882 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 883 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 884
232c0013
HHZ		 885 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
886 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
513f8f7f 887 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, attr);
232c0013 888 }
d85cdccb 889
513f8f7f 890 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 891
513f8f7f 892 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
d85cdccb 893 mlx5e_detach_encap(priv, flow);
513f8f7f 894 kvfree(attr->parse_attr);
232c0013 895 }
d7e75a32 896
513f8f7f 897 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 898 mlx5e_detach_mod_hdr(priv, flow);
d85cdccb
OG		 899}
900
232c0013
HHZ		 901void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
902 struct mlx5e_encap_entry *e)
903{
3c37745e
OG		 904 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
905 struct mlx5_esw_flow_attr *esw_attr;
232c0013
HHZ		 906 struct mlx5e_tc_flow *flow;
907 int err;
908
909 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
910 e->encap_size, e->encap_header,
911 &e->encap_id);
912 if (err) {
913 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
914 err);
915 return;
916 }
917 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 918 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 919
920 list_for_each_entry(flow, &e->flows, encap) {
3c37745e
OG		 921 esw_attr = flow->esw_attr;
922 esw_attr->encap_id = e->encap_id;
923 flow->rule = mlx5_eswitch_add_offloaded_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
232c0013
HHZ		 924 if (IS_ERR(flow->rule)) {
925 err = PTR_ERR(flow->rule);
926 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
927 err);
928 continue;
929 }
930 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
931 }
932}
933
934void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
935 struct mlx5e_encap_entry *e)
936{
3c37745e 937 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
232c0013 938 struct mlx5e_tc_flow *flow;
232c0013
HHZ		 939
940 list_for_each_entry(flow, &e->flows, encap) {
941 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
942 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
3c37745e 943 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, flow->esw_attr);
232c0013
HHZ		 944 }
945 }
946
947 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
948 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
949 mlx5_encap_dealloc(priv->mdev, e->encap_id);
950 }
951}
952
f6dfb4c3
HHZ		 953void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
954{
955 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
956 u64 bytes, packets, lastuse = 0;
957 struct mlx5e_tc_flow *flow;
958 struct mlx5e_encap_entry *e;
959 struct mlx5_fc *counter;
960 struct neigh_table *tbl;
961 bool neigh_used = false;
962 struct neighbour *n;
963
964 if (m_neigh->family == AF_INET)
965 tbl = &arp_tbl;
966#if IS_ENABLED(CONFIG_IPV6)
967 else if (m_neigh->family == AF_INET6)
423c9db2 968 tbl = &nd_tbl;
f6dfb4c3
HHZ		 969#endif
970 else
971 return;
972
973 list_for_each_entry(e, &nhe->encap_list, encap_list) {
974 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
975 continue;
976 list_for_each_entry(flow, &e->flows, encap) {
977 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
978 counter = mlx5_flow_rule_counter(flow->rule);
979 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
980 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
981 neigh_used = true;
982 break;
983 }
984 }
985 }
986 }
987
988 if (neigh_used) {
989 nhe->reported_lastuse = jiffies;
990
991 /* find the relevant neigh according to the cached device and
992 * dst ip pair
993 */
994 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
995 if (!n) {
996 WARN(1, "The neighbour already freed\n");
997 return;
998 }
999
1000 neigh_event_send(n, NULL);
1001 neigh_release(n);
1002 }
1003}
1004
d85cdccb
OG		 1005static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1006 struct mlx5e_tc_flow *flow)
1007{
5067b602
RD		 1008 struct list_head *next = flow->encap.next;
1009
1010 list_del(&flow->encap);
1011 if (list_empty(next)) {
c1ae1152 1012 struct mlx5e_encap_entry *e;
5067b602 1013
c1ae1152 1014 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1015 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1016
1017 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
5067b602 1018 mlx5_encap_dealloc(priv->mdev, e->encap_id);
232c0013 1019
cdc5a7f3 1020 hash_del_rcu(&e->encap_hlist);
232c0013 1021 kfree(e->encap_header);
5067b602
RD		 1022 kfree(e);
1023 }
1024}
1025
e8f887ac 1026static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1027 struct mlx5e_tc_flow *flow)
e8f887ac 1028{
d85cdccb
OG		 1029 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1030 mlx5e_tc_del_fdb_flow(priv, flow);
1031 else
1032 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 1033}
1034
bbd00f7e
HHZ		 1035static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
1036 struct tc_cls_flower_offload *f)
1037{
1038 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1039 outer_headers);
1040 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1041 outer_headers);
1042 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1043 misc_parameters);
1044 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1045 misc_parameters);
1046
1047 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
1048 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1049
1050 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
1051 struct flow_dissector_key_keyid *key =
1052 skb_flow_dissector_target(f->dissector,
1053 FLOW_DISSECTOR_KEY_ENC_KEYID,
1054 f->key);
1055 struct flow_dissector_key_keyid *mask =
1056 skb_flow_dissector_target(f->dissector,
1057 FLOW_DISSECTOR_KEY_ENC_KEYID,
1058 f->mask);
1059 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
1060 be32_to_cpu(mask->keyid));
1061 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
1062 be32_to_cpu(key->keyid));
1063 }
1064}
1065
1066static int parse_tunnel_attr(struct mlx5e_priv *priv,
1067 struct mlx5_flow_spec *spec,
1068 struct tc_cls_flower_offload *f)
1069{
1070 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1071 outer_headers);
1072 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1073 outer_headers);
1074
2e72eb43
OG		 1075 struct flow_dissector_key_control *enc_control =
1076 skb_flow_dissector_target(f->dissector,
1077 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1078 f->key);
1079
bbd00f7e
HHZ		 1080 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
1081 struct flow_dissector_key_ports *key =
1082 skb_flow_dissector_target(f->dissector,
1083 FLOW_DISSECTOR_KEY_ENC_PORTS,
1084 f->key);
1085 struct flow_dissector_key_ports *mask =
1086 skb_flow_dissector_target(f->dissector,
1087 FLOW_DISSECTOR_KEY_ENC_PORTS,
1088 f->mask);
1ad9a00a 1089 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4 1090 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5ed99fb4 1091 struct net_device *up_dev = uplink_rpriv->netdev;
1ad9a00a 1092 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ		 1093
1094 /* Full udp dst port must be given */
1095 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 1096 goto vxlan_match_offload_err;
bbd00f7e 1097
1ad9a00a 1098 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 1099 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
1100 parse_vxlan_attr(spec, f);
2fcd82e9
OG		 1101 else {
1102 netdev_warn(priv->netdev,
1103 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 1104 return -EOPNOTSUPP;
2fcd82e9 1105 }
bbd00f7e
HHZ		 1106
1107 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1108 udp_dport, ntohs(mask->dst));
1109 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1110 udp_dport, ntohs(key->dst));
1111
cd377663
OG		 1112 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1113 udp_sport, ntohs(mask->src));
1114 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1115 udp_sport, ntohs(key->src));
bbd00f7e 1116 } else { /* udp dst port must be given */
2fcd82e9
OG		 1117vxlan_match_offload_err:
1118 netdev_warn(priv->netdev,
1119 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
1120 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1121 }
1122
2e72eb43 1123 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 1124 struct flow_dissector_key_ipv4_addrs *key =
1125 skb_flow_dissector_target(f->dissector,
1126 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1127 f->key);
1128 struct flow_dissector_key_ipv4_addrs *mask =
1129 skb_flow_dissector_target(f->dissector,
1130 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1131 f->mask);
1132 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1133 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1134 ntohl(mask->src));
1135 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1136 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1137 ntohl(key->src));
1138
1139 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1140 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1141 ntohl(mask->dst));
1142 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1143 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1144 ntohl(key->dst));
bbd00f7e 1145
2e72eb43
OG		 1146 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1147 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 1148 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1149 struct flow_dissector_key_ipv6_addrs *key =
1150 skb_flow_dissector_target(f->dissector,
1151 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1152 f->key);
1153 struct flow_dissector_key_ipv6_addrs *mask =
1154 skb_flow_dissector_target(f->dissector,
1155 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1156 f->mask);
1157
1158 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1159 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1160 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1161 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1162 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1163 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1164
1165 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1166 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1167 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1168 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1169 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1170 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1171
1172 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1173 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1174 }
bbd00f7e
HHZ		 1175
1176 /* Enforce DMAC when offloading incoming tunneled flows.
1177 * Flow counters require a match on the DMAC.
1178 */
1179 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1180 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1181 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1182 dmac_47_16), priv->netdev->dev_addr);
1183
1184 /* let software handle IP fragments */
1185 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1186 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1187
1188 return 0;
1189}
1190
de0af0bf
RD		 1191static int __parse_cls_flower(struct mlx5e_priv *priv,
1192 struct mlx5_flow_spec *spec,
1193 struct tc_cls_flower_offload *f,
1194 u8 *min_inline)
e3a2b7ed 1195{
c5bb1730
MG		 1196 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1197 outer_headers);
1198 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1199 outer_headers);
e3a2b7ed
AV		 1200 u16 addr_type = 0;
1201 u8 ip_proto = 0;
1202
de0af0bf
RD		 1203 *min_inline = MLX5_INLINE_MODE_L2;
1204
e3a2b7ed
AV		 1205 if (f->dissector->used_keys &
1206 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1207 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1208 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1209 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV		 1210 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1211 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1212 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1213 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1214 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1215 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1216 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1217 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b
OG		 1218 BIT(FLOW_DISSECTOR_KEY_TCP) |
1219 BIT(FLOW_DISSECTOR_KEY_IP))) {
e3a2b7ed
AV		 1220 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1221 f->dissector->used_keys);
1222 return -EOPNOTSUPP;
1223 }
1224
bbd00f7e
HHZ		 1225 if ((dissector_uses_key(f->dissector,
1226 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1227 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1228 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1229 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1230 struct flow_dissector_key_control *key =
1231 skb_flow_dissector_target(f->dissector,
1232 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1233 f->key);
1234 switch (key->addr_type) {
1235 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1236 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 1237 if (parse_tunnel_attr(priv, spec, f))
1238 return -EOPNOTSUPP;
1239 break;
1240 default:
1241 return -EOPNOTSUPP;
1242 }
1243
1244 /* In decap flow, header pointers should point to the inner
1245 * headers, outer header were already set by parse_tunnel_attr
1246 */
1247 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1248 inner_headers);
1249 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1250 inner_headers);
1251 }
1252
e3a2b7ed
AV		 1253 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1254 struct flow_dissector_key_control *key =
1255 skb_flow_dissector_target(f->dissector,
1dbd0d37 1256 FLOW_DISSECTOR_KEY_CONTROL,
e3a2b7ed 1257 f->key);
3f7d0eb4
OG		 1258
1259 struct flow_dissector_key_control *mask =
1260 skb_flow_dissector_target(f->dissector,
1261 FLOW_DISSECTOR_KEY_CONTROL,
1262 f->mask);
e3a2b7ed 1263 addr_type = key->addr_type;
3f7d0eb4
OG		 1264
1265 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1266 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1267 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1268 key->flags & FLOW_DIS_IS_FRAGMENT);
0827444d
OG		 1269
1270 /* the HW doesn't need L3 inline to match on frag=no */
1271 if (key->flags & FLOW_DIS_IS_FRAGMENT)
1272 *min_inline = MLX5_INLINE_MODE_IP;
3f7d0eb4 1273 }
e3a2b7ed
AV		 1274 }
1275
1276 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1277 struct flow_dissector_key_basic *key =
1278 skb_flow_dissector_target(f->dissector,
1279 FLOW_DISSECTOR_KEY_BASIC,
1280 f->key);
1281 struct flow_dissector_key_basic *mask =
1282 skb_flow_dissector_target(f->dissector,
1283 FLOW_DISSECTOR_KEY_BASIC,
1284 f->mask);
1285 ip_proto = key->ip_proto;
1286
1287 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1288 ntohs(mask->n_proto));
1289 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1290 ntohs(key->n_proto));
1291
1292 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1293 mask->ip_proto);
1294 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1295 key->ip_proto);
de0af0bf
RD		 1296
1297 if (mask->ip_proto)
1298 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 1299 }
1300
1301 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1302 struct flow_dissector_key_eth_addrs *key =
1303 skb_flow_dissector_target(f->dissector,
1304 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1305 f->key);
1306 struct flow_dissector_key_eth_addrs *mask =
1307 skb_flow_dissector_target(f->dissector,
1308 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1309 f->mask);
1310
1311 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1312 dmac_47_16),
1313 mask->dst);
1314 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1315 dmac_47_16),
1316 key->dst);
1317
1318 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1319 smac_47_16),
1320 mask->src);
1321 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1322 smac_47_16),
1323 key->src);
1324 }
1325
095b6cfd
OG		 1326 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1327 struct flow_dissector_key_vlan *key =
1328 skb_flow_dissector_target(f->dissector,
1329 FLOW_DISSECTOR_KEY_VLAN,
1330 f->key);
1331 struct flow_dissector_key_vlan *mask =
1332 skb_flow_dissector_target(f->dissector,
1333 FLOW_DISSECTOR_KEY_VLAN,
1334 f->mask);
358d79a4 1335 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY		 1336 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1337 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG		 1338
1339 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1340 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 1341
1342 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1343 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
095b6cfd
OG		 1344 }
1345 }
1346
e3a2b7ed
AV		 1347 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1348 struct flow_dissector_key_ipv4_addrs *key =
1349 skb_flow_dissector_target(f->dissector,
1350 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1351 f->key);
1352 struct flow_dissector_key_ipv4_addrs *mask =
1353 skb_flow_dissector_target(f->dissector,
1354 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1355 f->mask);
1356
1357 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1358 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1359 &mask->src, sizeof(mask->src));
1360 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1361 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1362 &key->src, sizeof(key->src));
1363 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1364 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1365 &mask->dst, sizeof(mask->dst));
1366 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1367 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1368 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1369
1370 if (mask->src || mask->dst)
1371 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 1372 }
1373
1374 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1375 struct flow_dissector_key_ipv6_addrs *key =
1376 skb_flow_dissector_target(f->dissector,
1377 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1378 f->key);
1379 struct flow_dissector_key_ipv6_addrs *mask =
1380 skb_flow_dissector_target(f->dissector,
1381 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1382 f->mask);
1383
1384 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1385 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1386 &mask->src, sizeof(mask->src));
1387 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1388 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1389 &key->src, sizeof(key->src));
1390
1391 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1392 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1393 &mask->dst, sizeof(mask->dst));
1394 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1395 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1396 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1397
1398 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1399 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
1400 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 1401 }
1402
1f97a526
OG		 1403 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1404 struct flow_dissector_key_ip *key =
1405 skb_flow_dissector_target(f->dissector,
1406 FLOW_DISSECTOR_KEY_IP,
1407 f->key);
1408 struct flow_dissector_key_ip *mask =
1409 skb_flow_dissector_target(f->dissector,
1410 FLOW_DISSECTOR_KEY_IP,
1411 f->mask);
1412
1413 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1414 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1415
1416 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1417 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1418
a8ade55f
OG		 1419 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1420 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 1421
a8ade55f
OG		 1422 if (mask->ttl &&
1423 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
1424 ft_field_support.outer_ipv4_ttl))
1f97a526 1425 return -EOPNOTSUPP;
a8ade55f
OG		 1426
1427 if (mask->tos || mask->ttl)
1428 *min_inline = MLX5_INLINE_MODE_IP;
1f97a526
OG		 1429 }
1430
e3a2b7ed
AV		 1431 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1432 struct flow_dissector_key_ports *key =
1433 skb_flow_dissector_target(f->dissector,
1434 FLOW_DISSECTOR_KEY_PORTS,
1435 f->key);
1436 struct flow_dissector_key_ports *mask =
1437 skb_flow_dissector_target(f->dissector,
1438 FLOW_DISSECTOR_KEY_PORTS,
1439 f->mask);
1440 switch (ip_proto) {
1441 case IPPROTO_TCP:
1442 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1443 tcp_sport, ntohs(mask->src));
1444 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1445 tcp_sport, ntohs(key->src));
1446
1447 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1448 tcp_dport, ntohs(mask->dst));
1449 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1450 tcp_dport, ntohs(key->dst));
1451 break;
1452
1453 case IPPROTO_UDP:
1454 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1455 udp_sport, ntohs(mask->src));
1456 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1457 udp_sport, ntohs(key->src));
1458
1459 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1460 udp_dport, ntohs(mask->dst));
1461 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1462 udp_dport, ntohs(key->dst));
1463 break;
1464 default:
1465 netdev_err(priv->netdev,
1466 "Only UDP and TCP transport are supported\n");
1467 return -EINVAL;
1468 }
de0af0bf
RD		 1469
1470 if (mask->src || mask->dst)
1471 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
e3a2b7ed
AV		 1472 }
1473
e77834ec
OG		 1474 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1475 struct flow_dissector_key_tcp *key =
1476 skb_flow_dissector_target(f->dissector,
1477 FLOW_DISSECTOR_KEY_TCP,
1478 f->key);
1479 struct flow_dissector_key_tcp *mask =
1480 skb_flow_dissector_target(f->dissector,
1481 FLOW_DISSECTOR_KEY_TCP,
1482 f->mask);
1483
1484 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1485 ntohs(mask->flags));
1486 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1487 ntohs(key->flags));
1488
1489 if (mask->flags)
1490 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
1491 }
1492
e3a2b7ed
AV		 1493 return 0;
1494}
1495
de0af0bf 1496static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1497 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 1498 struct mlx5_flow_spec *spec,
1499 struct tc_cls_flower_offload *f)
1500{
1501 struct mlx5_core_dev *dev = priv->mdev;
1502 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1503 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1504 struct mlx5_eswitch_rep *rep;
de0af0bf
RD		 1505 u8 min_inline;
1506 int err;
1507
1508 err = __parse_cls_flower(priv, spec, f, &min_inline);
1509
1d447a39
SM		 1510 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1511 rep = rpriv->rep;
1512 if (rep->vport != FDB_UPLINK_VPORT &&
1513 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
1514 esw->offloads.inline_mode < min_inline)) {
de0af0bf
RD		 1515 netdev_warn(priv->netdev,
1516 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
1517 min_inline, esw->offloads.inline_mode);
1518 return -EOPNOTSUPP;
1519 }
1520 }
1521
1522 return err;
1523}
1524
d79b6df6
OG		 1525struct pedit_headers {
1526 struct ethhdr eth;
1527 struct iphdr ip4;
1528 struct ipv6hdr ip6;
1529 struct tcphdr tcp;
1530 struct udphdr udp;
1531};
1532
1533static int pedit_header_offsets[] = {
1534 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1535 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1536 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1537 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1538 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1539};
1540
1541#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1542
1543static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1544 struct pedit_headers *masks,
1545 struct pedit_headers *vals)
1546{
1547 u32 *curr_pmask, *curr_pval;
1548
1549 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1550 goto out_err;
1551
1552 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1553 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1554
1555 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1556 goto out_err;
1557
1558 *curr_pmask |= mask;
1559 *curr_pval |= (val & mask);
1560
1561 return 0;
1562
1563out_err:
1564 return -EOPNOTSUPP;
1565}
1566
1567struct mlx5_fields {
1568 u8 field;
1569 u8 size;
1570 u32 offset;
1571};
1572
a8e4f0c4
OG		 1573#define OFFLOAD(fw_field, size, field, off) \
1574 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1575
d79b6df6 1576static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1577 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1578 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1579 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1580 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1581 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1582 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1583
1584 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1585 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1586 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1587
1588 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1589 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1590 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1591 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1592 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1593 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1594 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1595 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1596 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1597
1598 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1599 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1600 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1601
1602 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1603 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1604};
1605
1606/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1607 * max from the SW pedit action. On success, it says how many HW actions were
1608 * actually parsed.
1609 */
1610static int offload_pedit_fields(struct pedit_headers *masks,
1611 struct pedit_headers *vals,
1612 struct mlx5e_tc_flow_parse_attr *parse_attr)
1613{
1614 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1615 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1616 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1617 struct mlx5_fields *f;
1618 u8 cmd, field_bsize;
e3ca4e05 1619 u32 s_mask, a_mask;
d79b6df6 1620 unsigned long mask;
2b64beba
OG		 1621 __be32 mask_be32;
1622 __be16 mask_be16;
d79b6df6
OG		 1623 void *action;
1624
1625 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1626 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1627 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1628 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1629
1630 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1631 action = parse_attr->mod_hdr_actions;
1632 max_actions = parse_attr->num_mod_hdr_actions;
1633 nactions = 0;
1634
1635 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1636 f = &fields[i];
1637 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1638 s_mask = 0;
1639 a_mask = 0;
d79b6df6
OG		 1640
1641 s_masks_p = (void *)set_masks + f->offset;
1642 a_masks_p = (void *)add_masks + f->offset;
1643
1644 memcpy(&s_mask, s_masks_p, f->size);
1645 memcpy(&a_mask, a_masks_p, f->size);
1646
1647 if (!s_mask && !a_mask) /* nothing to offload here */
1648 continue;
1649
1650 if (s_mask && a_mask) {
1651 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1652 return -EOPNOTSUPP;
1653 }
1654
1655 if (nactions == max_actions) {
1656 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1657 return -EOPNOTSUPP;
1658 }
1659
1660 if (s_mask) {
1661 cmd = MLX5_ACTION_TYPE_SET;
1662 mask = s_mask;
1663 vals_p = (void *)set_vals + f->offset;
1664 /* clear to denote we consumed this field */
1665 memset(s_masks_p, 0, f->size);
1666 } else {
1667 cmd = MLX5_ACTION_TYPE_ADD;
1668 mask = a_mask;
1669 vals_p = (void *)add_vals + f->offset;
1670 /* clear to denote we consumed this field */
1671 memset(a_masks_p, 0, f->size);
1672 }
1673
d79b6df6 1674 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1675
2b64beba
OG		 1676 if (field_bsize == 32) {
1677 mask_be32 = *(__be32 *)&mask;
1678 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1679 } else if (field_bsize == 16) {
1680 mask_be16 = *(__be16 *)&mask;
1681 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1682 }
1683
d79b6df6 1684 first = find_first_bit(&mask, field_bsize);
2b64beba 1685 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1686 last = find_last_bit(&mask, field_bsize);
2b64beba
OG		 1687 if (first < next_z && next_z < last) {
1688 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1689 mask);
1690 return -EOPNOTSUPP;
1691 }
1692
1693 MLX5_SET(set_action_in, action, action_type, cmd);
1694 MLX5_SET(set_action_in, action, field, f->field);
1695
1696 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1697 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1698 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1699 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1700 }
1701
1702 if (field_bsize == 32)
2b64beba 1703 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1704 else if (field_bsize == 16)
2b64beba 1705 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1706 else if (field_bsize == 8)
2b64beba 1707 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1708
1709 action += action_size;
1710 nactions++;
1711 }
1712
1713 parse_attr->num_mod_hdr_actions = nactions;
1714 return 0;
1715}
1716
1717static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1718 const struct tc_action *a, int namespace,
1719 struct mlx5e_tc_flow_parse_attr *parse_attr)
1720{
1721 int nkeys, action_size, max_actions;
1722
1723 nkeys = tcf_pedit_nkeys(a);
1724 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1725
1726 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1727 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1728 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1729 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1730
1731 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1732 max_actions = min(max_actions, nkeys * 16);
1733
1734 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1735 if (!parse_attr->mod_hdr_actions)
1736 return -ENOMEM;
1737
1738 parse_attr->num_mod_hdr_actions = max_actions;
1739 return 0;
1740}
1741
1742static const struct pedit_headers zero_masks = {};
1743
1744static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1745 const struct tc_action *a, int namespace,
1746 struct mlx5e_tc_flow_parse_attr *parse_attr)
1747{
1748 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1749 int nkeys, i, err = -EOPNOTSUPP;
1750 u32 mask, val, offset;
1751 u8 cmd, htype;
1752
1753 nkeys = tcf_pedit_nkeys(a);
1754
1755 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1756 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1757
1758 for (i = 0; i < nkeys; i++) {
1759 htype = tcf_pedit_htype(a, i);
1760 cmd = tcf_pedit_cmd(a, i);
1761 err = -EOPNOTSUPP; /* can't be all optimistic */
1762
1763 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
1764 printk(KERN_WARNING "mlx5: legacy pedit isn't offloaded\n");
1765 goto out_err;
1766 }
1767
1768 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
1769 printk(KERN_WARNING "mlx5: pedit cmd %d isn't offloaded\n", cmd);
1770 goto out_err;
1771 }
1772
1773 mask = tcf_pedit_mask(a, i);
1774 val = tcf_pedit_val(a, i);
1775 offset = tcf_pedit_offset(a, i);
1776
1777 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1778 if (err)
1779 goto out_err;
1780 }
1781
1782 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1783 if (err)
1784 goto out_err;
1785
1786 err = offload_pedit_fields(masks, vals, parse_attr);
1787 if (err < 0)
1788 goto out_dealloc_parsed_actions;
1789
1790 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1791 cmd_masks = &masks[cmd];
1792 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
1793 printk(KERN_WARNING "mlx5: attempt to offload an unsupported field (cmd %d)\n",
1794 cmd);
1795 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1796 16, 1, cmd_masks, sizeof(zero_masks), true);
1797 err = -EOPNOTSUPP;
1798 goto out_dealloc_parsed_actions;
1799 }
1800 }
1801
1802 return 0;
1803
1804out_dealloc_parsed_actions:
1805 kfree(parse_attr->mod_hdr_actions);
1806out_err:
1807 return err;
1808}
1809
26c02749
OG		 1810static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1811{
1812 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1813 TCA_CSUM_UPDATE_FLAG_UDP;
1814
1815 /* The HW recalcs checksums only if re-writing headers */
1816 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1817 netdev_warn(priv->netdev,
1818 "TC csum action is only offloaded with pedit\n");
1819 return false;
1820 }
1821
1822 if (update_flags & ~prot_flags) {
1823 netdev_warn(priv->netdev,
1824 "can't offload TC csum action for some header/s - flags %#x\n",
1825 update_flags);
1826 return false;
1827 }
1828
1829 return true;
1830}
1831
bdd66ac0
OG		 1832static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
1833 struct tcf_exts *exts)
1834{
1835 const struct tc_action *a;
1836 bool modify_ip_header;
1837 LIST_HEAD(actions);
1838 u8 htype, ip_proto;
1839 void *headers_v;
1840 u16 ethertype;
1841 int nkeys, i;
1842
1843 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1844 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1845
1846 /* for non-IP we only re-write MACs, so we're okay */
1847 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
1848 goto out_ok;
1849
1850 modify_ip_header = false;
1851 tcf_exts_to_list(exts, &actions);
1852 list_for_each_entry(a, &actions, list) {
1853 if (!is_tcf_pedit(a))
1854 continue;
1855
1856 nkeys = tcf_pedit_nkeys(a);
1857 for (i = 0; i < nkeys; i++) {
1858 htype = tcf_pedit_htype(a, i);
1859 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
1860 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
1861 modify_ip_header = true;
1862 break;
1863 }
1864 }
1865 }
1866
1867 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1868 if (modify_ip_header && ip_proto != IPPROTO_TCP && ip_proto != IPPROTO_UDP) {
1869 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
1870 return false;
1871 }
1872
1873out_ok:
1874 return true;
1875}
1876
1877static bool actions_match_supported(struct mlx5e_priv *priv,
1878 struct tcf_exts *exts,
1879 struct mlx5e_tc_flow_parse_attr *parse_attr,
1880 struct mlx5e_tc_flow *flow)
1881{
1882 u32 actions;
1883
1884 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1885 actions = flow->esw_attr->action;
1886 else
1887 actions = flow->nic_attr->action;
1888
1889 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1890 return modify_header_match_supported(&parse_attr->spec, exts);
1891
1892 return true;
1893}
1894
5c65c564
OG		 1895static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
1896{
1897 struct mlx5_core_dev *fmdev, *pmdev;
1898 u16 func_id, peer_id;
1899
1900 fmdev = priv->mdev;
1901 pmdev = peer_priv->mdev;
1902
1903 func_id = (u16)((fmdev->pdev->bus->number << 8) | PCI_SLOT(fmdev->pdev->devfn));
1904 peer_id = (u16)((pmdev->pdev->bus->number << 8) | PCI_SLOT(pmdev->pdev->devfn));
1905
1906 return (func_id == peer_id);
1907}
1908
5c40348c 1909static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG		 1910 struct mlx5e_tc_flow_parse_attr *parse_attr,
1911 struct mlx5e_tc_flow *flow)
e3a2b7ed 1912{
aa0cbbae 1913 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1914 const struct tc_action *a;
22dc13c8 1915 LIST_HEAD(actions);
2f4fe4ca 1916 int err;
e3a2b7ed 1917
3bcc0cec 1918 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 1919 return -EINVAL;
1920
3bc4b7bf
OG		 1921 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1922 attr->action = 0;
e3a2b7ed 1923
22dc13c8
WC		 1924 tcf_exts_to_list(exts, &actions);
1925 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1926 if (is_tcf_gact_shot(a)) {
3bc4b7bf 1927 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 1928 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1929 flow_table_properties_nic_receive.flow_counter))
3bc4b7bf 1930 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 1931 continue;
1932 }
1933
2f4fe4ca
OG		 1934 if (is_tcf_pedit(a)) {
1935 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1936 parse_attr);
1937 if (err)
1938 return err;
1939
1940 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1941 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1942 continue;
1943 }
1944
26c02749
OG		 1945 if (is_tcf_csum(a)) {
1946 if (csum_offload_supported(priv, attr->action,
1947 tcf_csum_update_flags(a)))
1948 continue;
1949
1950 return -EOPNOTSUPP;
1951 }
1952
5c65c564
OG		 1953 if (is_tcf_mirred_egress_redirect(a)) {
1954 struct net_device *peer_dev = tcf_mirred_dev(a);
1955
1956 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
1957 same_hw_devs(priv, netdev_priv(peer_dev))) {
1958 parse_attr->mirred_ifindex = peer_dev->ifindex;
1959 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1960 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1961 MLX5_FLOW_CONTEXT_ACTION_COUNT;
1962 } else {
1963 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
1964 peer_dev->name);
1965 return -EINVAL;
1966 }
1967 continue;
1968 }
1969
e3a2b7ed
AV		 1970 if (is_tcf_skbedit_mark(a)) {
1971 u32 mark = tcf_skbedit_mark(a);
1972
1973 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
1974 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
1975 mark);
1976 return -EINVAL;
1977 }
1978
3bc4b7bf
OG		 1979 attr->flow_tag = mark;
1980 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 1981 continue;
1982 }
1983
1984 return -EINVAL;
1985 }
1986
bdd66ac0
OG		 1987 if (!actions_match_supported(priv, exts, parse_attr, flow))
1988 return -EOPNOTSUPP;
1989
e3a2b7ed
AV		 1990 return 0;
1991}
1992
76f7444d
OG		 1993static inline int cmp_encap_info(struct ip_tunnel_key *a,
1994 struct ip_tunnel_key *b)
a54e20b4
HHZ		 1995{
1996 return memcmp(a, b, sizeof(*a));
1997}
1998
76f7444d 1999static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2000{
76f7444d 2001 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2002}
2003
2004static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
2005 struct net_device *mirred_dev,
2006 struct net_device **out_dev,
2007 struct flowi4 *fl4,
2008 struct neighbour **out_n,
a54e20b4
HHZ		 2009 int *out_ttl)
2010{
3e621b19 2011 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5ed99fb4 2012 struct mlx5e_rep_priv *uplink_rpriv;
a54e20b4
HHZ		 2013 struct rtable *rt;
2014 struct neighbour *n = NULL;
a54e20b4
HHZ		 2015
2016#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 2017 int ret;
2018
a54e20b4 2019 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 2020 ret = PTR_ERR_OR_ZERO(rt);
2021 if (ret)
2022 return ret;
a54e20b4
HHZ		 2023#else
2024 return -EOPNOTSUPP;
2025#endif
a4b97ab4 2026 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3e621b19
HHZ		 2027 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2028 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
5ed99fb4 2029 *out_dev = uplink_rpriv->netdev;
3e621b19
HHZ		 2030 else
2031 *out_dev = rt->dst.dev;
a54e20b4 2032
75c33da8 2033 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 2034 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
2035 ip_rt_put(rt);
2036 if (!n)
2037 return -ENOMEM;
2038
2039 *out_n = n;
a54e20b4
HHZ		 2040 return 0;
2041}
2042
ce99f6b9
OG		 2043static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
2044 struct net_device *mirred_dev,
2045 struct net_device **out_dev,
2046 struct flowi6 *fl6,
2047 struct neighbour **out_n,
2048 int *out_ttl)
2049{
2050 struct neighbour *n = NULL;
2051 struct dst_entry *dst;
2052
2053#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
74bd5d56 2054 struct mlx5e_rep_priv *uplink_rpriv;
ce99f6b9
OG		 2055 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2056 int ret;
2057
08820528
PB		 2058 ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
2059 fl6);
2060 if (ret < 0)
ce99f6b9 2061 return ret;
ce99f6b9
OG		 2062
2063 *out_ttl = ip6_dst_hoplimit(dst);
2064
a4b97ab4 2065 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ce99f6b9
OG		 2066 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2067 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
5ed99fb4 2068 *out_dev = uplink_rpriv->netdev;
ce99f6b9
OG		 2069 else
2070 *out_dev = dst->dev;
2071#else
2072 return -EOPNOTSUPP;
2073#endif
2074
2075 n = dst_neigh_lookup(dst, &fl6->daddr);
2076 dst_release(dst);
2077 if (!n)
2078 return -ENOMEM;
2079
2080 *out_n = n;
2081 return 0;
2082}
2083
32f3671f
OG		 2084static void gen_vxlan_header_ipv4(struct net_device *out_dev,
2085 char buf[], int encap_size,
2086 unsigned char h_dest[ETH_ALEN],
2087 int ttl,
2088 __be32 daddr,
2089 __be32 saddr,
2090 __be16 udp_dst_port,
2091 __be32 vx_vni)
a54e20b4 2092{
a54e20b4
HHZ		 2093 struct ethhdr *eth = (struct ethhdr *)buf;
2094 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
2095 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
2096 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2097
2098 memset(buf, 0, encap_size);
2099
2100 ether_addr_copy(eth->h_dest, h_dest);
2101 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2102 eth->h_proto = htons(ETH_P_IP);
2103
2104 ip->daddr = daddr;
2105 ip->saddr = saddr;
2106
2107 ip->ttl = ttl;
2108 ip->protocol = IPPROTO_UDP;
2109 ip->version = 0x4;
2110 ip->ihl = 0x5;
2111
2112 udp->dest = udp_dst_port;
2113 vxh->vx_flags = VXLAN_HF_VNI;
2114 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 2115}
2116
225aabaf
OG		 2117static void gen_vxlan_header_ipv6(struct net_device *out_dev,
2118 char buf[], int encap_size,
2119 unsigned char h_dest[ETH_ALEN],
2120 int ttl,
2121 struct in6_addr *daddr,
2122 struct in6_addr *saddr,
2123 __be16 udp_dst_port,
2124 __be32 vx_vni)
ce99f6b9 2125{
ce99f6b9
OG		 2126 struct ethhdr *eth = (struct ethhdr *)buf;
2127 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
2128 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
2129 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2130
2131 memset(buf, 0, encap_size);
2132
2133 ether_addr_copy(eth->h_dest, h_dest);
2134 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2135 eth->h_proto = htons(ETH_P_IPV6);
2136
2137 ip6_flow_hdr(ip6h, 0, 0);
2138 /* the HW fills up ipv6 payload len */
2139 ip6h->nexthdr = IPPROTO_UDP;
2140 ip6h->hop_limit = ttl;
2141 ip6h->daddr = *daddr;
2142 ip6h->saddr = *saddr;
2143
2144 udp->dest = udp_dst_port;
2145 vxh->vx_flags = VXLAN_HF_VNI;
2146 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 2147}
2148
a54e20b4
HHZ		 2149static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
2150 struct net_device *mirred_dev,
1a8552bd 2151 struct mlx5e_encap_entry *e)
a54e20b4
HHZ		 2152{
2153 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 2154 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 2155 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2156 struct net_device *out_dev;
a42485eb 2157 struct neighbour *n = NULL;
a54e20b4 2158 struct flowi4 fl4 = {};
a54e20b4 2159 char *encap_header;
32f3671f 2160 int ttl, err;
033354d5 2161 u8 nud_state;
32f3671f
OG		 2162
2163 if (max_encap_size < ipv4_encap_size) {
2164 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2165 ipv4_encap_size, max_encap_size);
2166 return -EOPNOTSUPP;
2167 }
a54e20b4 2168
32f3671f 2169 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 2170 if (!encap_header)
2171 return -ENOMEM;
2172
2173 switch (e->tunnel_type) {
2174 case MLX5_HEADER_TYPE_VXLAN:
2175 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 2176 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 2177 break;
2178 default:
2179 err = -EOPNOTSUPP;
ace74321 2180 goto free_encap;
a54e20b4 2181 }
9a941117 2182 fl4.flowi4_tos = tun_key->tos;
76f7444d 2183 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 2184 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 2185
1a8552bd 2186 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 2187 &fl4, &n, &ttl);
a54e20b4 2188 if (err)
ace74321 2189 goto free_encap;
a54e20b4 2190
232c0013
HHZ		 2191 /* used by mlx5e_detach_encap to lookup a neigh hash table
2192 * entry in the neigh hash table when a user deletes a rule
2193 */
2194 e->m_neigh.dev = n->dev;
f6dfb4c3 2195 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2196 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2197 e->out_dev = out_dev;
2198
2199 /* It's importent to add the neigh to the hash table before checking
2200 * the neigh validity state. So if we'll get a notification, in case the
2201 * neigh changes it's validity state, we would find the relevant neigh
2202 * in the hash.
2203 */
2204 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2205 if (err)
ace74321 2206 goto free_encap;
232c0013 2207
033354d5
HHZ		 2208 read_lock_bh(&n->lock);
2209 nud_state = n->nud_state;
2210 ether_addr_copy(e->h_dest, n->ha);
2211 read_unlock_bh(&n->lock);
2212
a54e20b4
HHZ		 2213 switch (e->tunnel_type) {
2214 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 2215 gen_vxlan_header_ipv4(out_dev, encap_header,
32f3671f
OG		 2216 ipv4_encap_size, e->h_dest, ttl,
2217 fl4.daddr,
2218 fl4.saddr, tun_key->tp_dst,
2219 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 2220 break;
2221 default:
2222 err = -EOPNOTSUPP;
232c0013
HHZ		 2223 goto destroy_neigh_entry;
2224 }
2225 e->encap_size = ipv4_encap_size;
2226 e->encap_header = encap_header;
2227
2228 if (!(nud_state & NUD_VALID)) {
2229 neigh_event_send(n, NULL);
27902f08
WY		 2230 err = -EAGAIN;
2231 goto out;
a54e20b4
HHZ		 2232 }
2233
2234 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 2235 ipv4_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 2236 if (err)
2237 goto destroy_neigh_entry;
2238
2239 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2240 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2241 neigh_release(n);
2242 return err;
2243
2244destroy_neigh_entry:
2245 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2246free_encap:
a54e20b4 2247 kfree(encap_header);
ace74321 2248out:
232c0013
HHZ		 2249 if (n)
2250 neigh_release(n);
a54e20b4
HHZ		 2251 return err;
2252}
2253
ce99f6b9
OG		 2254static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2255 struct net_device *mirred_dev,
1a8552bd 2256 struct mlx5e_encap_entry *e)
ce99f6b9
OG		 2257{
2258 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 2259 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 2260 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2261 struct net_device *out_dev;
ce99f6b9
OG		 2262 struct neighbour *n = NULL;
2263 struct flowi6 fl6 = {};
2264 char *encap_header;
225aabaf 2265 int err, ttl = 0;
033354d5 2266 u8 nud_state;
ce99f6b9 2267
225aabaf
OG		 2268 if (max_encap_size < ipv6_encap_size) {
2269 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2270 ipv6_encap_size, max_encap_size);
2271 return -EOPNOTSUPP;
2272 }
ce99f6b9 2273
225aabaf 2274 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 2275 if (!encap_header)
2276 return -ENOMEM;
2277
2278 switch (e->tunnel_type) {
2279 case MLX5_HEADER_TYPE_VXLAN:
2280 fl6.flowi6_proto = IPPROTO_UDP;
2281 fl6.fl6_dport = tun_key->tp_dst;
2282 break;
2283 default:
2284 err = -EOPNOTSUPP;
ace74321 2285 goto free_encap;
ce99f6b9
OG		 2286 }
2287
2288 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2289 fl6.daddr = tun_key->u.ipv6.dst;
2290 fl6.saddr = tun_key->u.ipv6.src;
2291
1a8552bd 2292 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG		 2293 &fl6, &n, &ttl);
2294 if (err)
ace74321 2295 goto free_encap;
ce99f6b9 2296
232c0013
HHZ		 2297 /* used by mlx5e_detach_encap to lookup a neigh hash table
2298 * entry in the neigh hash table when a user deletes a rule
2299 */
2300 e->m_neigh.dev = n->dev;
f6dfb4c3 2301 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2302 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2303 e->out_dev = out_dev;
2304
2305 /* It's importent to add the neigh to the hash table before checking
2306 * the neigh validity state. So if we'll get a notification, in case the
2307 * neigh changes it's validity state, we would find the relevant neigh
2308 * in the hash.
2309 */
2310 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2311 if (err)
ace74321 2312 goto free_encap;
232c0013 2313
033354d5
HHZ		 2314 read_lock_bh(&n->lock);
2315 nud_state = n->nud_state;
2316 ether_addr_copy(e->h_dest, n->ha);
2317 read_unlock_bh(&n->lock);
2318
ce99f6b9
OG		 2319 switch (e->tunnel_type) {
2320 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 2321 gen_vxlan_header_ipv6(out_dev, encap_header,
225aabaf
OG		 2322 ipv6_encap_size, e->h_dest, ttl,
2323 &fl6.daddr,
2324 &fl6.saddr, tun_key->tp_dst,
2325 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 2326 break;
2327 default:
2328 err = -EOPNOTSUPP;
232c0013
HHZ		 2329 goto destroy_neigh_entry;
2330 }
2331
2332 e->encap_size = ipv6_encap_size;
2333 e->encap_header = encap_header;
2334
2335 if (!(nud_state & NUD_VALID)) {
2336 neigh_event_send(n, NULL);
27902f08
WY		 2337 err = -EAGAIN;
2338 goto out;
ce99f6b9
OG		 2339 }
2340
2341 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 2342 ipv6_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 2343 if (err)
2344 goto destroy_neigh_entry;
2345
2346 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2347 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2348 neigh_release(n);
2349 return err;
2350
2351destroy_neigh_entry:
2352 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2353free_encap:
ce99f6b9 2354 kfree(encap_header);
ace74321 2355out:
232c0013
HHZ		 2356 if (n)
2357 neigh_release(n);
ce99f6b9
OG		 2358 return err;
2359}
2360
a54e20b4
HHZ		 2361static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2362 struct ip_tunnel_info *tun_info,
2363 struct net_device *mirred_dev,
45247bf2
OG		 2364 struct net_device **encap_dev,
2365 struct mlx5e_tc_flow *flow)
a54e20b4
HHZ		 2366{
2367 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4
MB		 2368 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw,
2369 REP_ETH);
5ed99fb4 2370 struct net_device *up_dev = uplink_rpriv->netdev;
a54e20b4 2371 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2
OG		 2372 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
2373 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2374 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2375 struct mlx5e_encap_entry *e;
45247bf2 2376 int tunnel_type, err = 0;
a54e20b4
HHZ		 2377 uintptr_t hash_key;
2378 bool found = false;
a54e20b4 2379
2fcd82e9 2380 /* udp dst port must be set */
a54e20b4 2381 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 2382 goto vxlan_encap_offload_err;
a54e20b4 2383
cd377663 2384 /* setting udp src port isn't supported */
2fcd82e9
OG		 2385 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2386vxlan_encap_offload_err:
2387 netdev_warn(priv->netdev,
2388 "must set udp dst port and not set udp src port\n");
cd377663 2389 return -EOPNOTSUPP;
2fcd82e9 2390 }
cd377663 2391
1ad9a00a 2392 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 2393 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ		 2394 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
2395 } else {
2fcd82e9
OG		 2396 netdev_warn(priv->netdev,
2397 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 2398 return -EOPNOTSUPP;
2399 }
2400
76f7444d 2401 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2402
2403 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2404 encap_hlist, hash_key) {
76f7444d 2405 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2406 found = true;
2407 break;
2408 }
2409 }
2410
b2812089 2411 /* must verify if encap is valid or not */
45247bf2
OG		 2412 if (found)
2413 goto attach_flow;
a54e20b4
HHZ		 2414
2415 e = kzalloc(sizeof(*e), GFP_KERNEL);
2416 if (!e)
2417 return -ENOMEM;
2418
76f7444d 2419 e->tun_info = *tun_info;
a54e20b4
HHZ		 2420 e->tunnel_type = tunnel_type;
2421 INIT_LIST_HEAD(&e->flows);
2422
ce99f6b9 2423 if (family == AF_INET)
1a8552bd 2424 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2425 else if (family == AF_INET6)
1a8552bd 2426 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2427
232c0013 2428 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2429 goto out_err;
2430
a54e20b4
HHZ		 2431 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2432
45247bf2
OG		 2433attach_flow:
2434 list_add(&flow->encap, &e->flows);
2435 *encap_dev = e->out_dev;
232c0013
HHZ		 2436 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2437 attr->encap_id = e->encap_id;
b2812089
VB		 2438 else
2439 err = -EAGAIN;
45247bf2 2440
232c0013 2441 return err;
a54e20b4
HHZ		 2442
2443out_err:
2444 kfree(e);
2445 return err;
2446}
2447
03a9d11e 2448static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 2449 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 2450 struct mlx5e_tc_flow *flow)
03a9d11e 2451{
ecf5bb79 2452 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2453 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 2454 struct ip_tunnel_info *info = NULL;
03a9d11e 2455 const struct tc_action *a;
22dc13c8 2456 LIST_HEAD(actions);
a54e20b4 2457 bool encap = false;
232c0013 2458 int err = 0;
03a9d11e 2459
3bcc0cec 2460 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 2461 return -EINVAL;
2462
776b12b6 2463 memset(attr, 0, sizeof(*attr));
1d447a39 2464 attr->in_rep = rpriv->rep;
03a9d11e 2465
22dc13c8
WC		 2466 tcf_exts_to_list(exts, &actions);
2467 list_for_each_entry(a, &actions, list) {
03a9d11e 2468 if (is_tcf_gact_shot(a)) {
8b32580d
OG		 2469 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2470 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 2471 continue;
2472 }
2473
d7e75a32
OG		 2474 if (is_tcf_pedit(a)) {
2475 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
2476 parse_attr);
2477 if (err)
2478 return err;
2479
2480 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2481 continue;
2482 }
2483
26c02749
OG		 2484 if (is_tcf_csum(a)) {
2485 if (csum_offload_supported(priv, attr->action,
2486 tcf_csum_update_flags(a)))
2487 continue;
2488
2489 return -EOPNOTSUPP;
2490 }
2491
5724b8b5 2492 if (is_tcf_mirred_egress_redirect(a)) {
3c37745e 2493 struct net_device *out_dev;
03a9d11e 2494 struct mlx5e_priv *out_priv;
03a9d11e 2495
9f8a739e 2496 out_dev = tcf_mirred_dev(a);
03a9d11e 2497
a54e20b4
HHZ		 2498 if (switchdev_port_same_parent_id(priv->netdev,
2499 out_dev)) {
2500 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2501 MLX5_FLOW_CONTEXT_ACTION_COUNT;
2502 out_priv = netdev_priv(out_dev);
1d447a39
SM		 2503 rpriv = out_priv->ppriv;
2504 attr->out_rep = rpriv->rep;
56e858df 2505 attr->out_mdev = out_priv->mdev;
a54e20b4 2506 } else if (encap) {
9f8a739e 2507 parse_attr->mirred_ifindex = out_dev->ifindex;
3c37745e
OG		 2508 parse_attr->tun_info = *info;
2509 attr->parse_attr = parse_attr;
a54e20b4
HHZ		 2510 attr->action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
2511 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2512 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3c37745e 2513 /* attr->out_rep is resolved when we handle encap */
a54e20b4 2514 } else {
03a9d11e
OG		 2515 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2516 priv->netdev->name, out_dev->name);
2517 return -EINVAL;
2518 }
a54e20b4
HHZ		 2519 continue;
2520 }
03a9d11e 2521
a54e20b4
HHZ		 2522 if (is_tcf_tunnel_set(a)) {
2523 info = tcf_tunnel_info(a);
2524 if (info)
2525 encap = true;
2526 else
2527 return -EOPNOTSUPP;
03a9d11e
OG		 2528 continue;
2529 }
2530
8b32580d 2531 if (is_tcf_vlan(a)) {
09c91ddf 2532 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
8b32580d 2533 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 2534 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
8b32580d 2535 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
6acfbf38
OG		 2536 attr->vlan_vid = tcf_vlan_push_vid(a);
2537 if (mlx5_eswitch_vlan_actions_supported(priv->mdev)) {
2538 attr->vlan_prio = tcf_vlan_push_prio(a);
2539 attr->vlan_proto = tcf_vlan_push_proto(a);
2540 if (!attr->vlan_proto)
2541 attr->vlan_proto = htons(ETH_P_8021Q);
2542 } else if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2543 tcf_vlan_push_prio(a)) {
2544 return -EOPNOTSUPP;
2545 }
09c91ddf
OG		 2546 } else { /* action is TCA_VLAN_ACT_MODIFY */
2547 return -EOPNOTSUPP;
8b32580d
OG		 2548 }
2549 continue;
2550 }
2551
bbd00f7e
HHZ		 2552 if (is_tcf_tunnel_release(a)) {
2553 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2554 continue;
2555 }
2556
03a9d11e
OG		 2557 return -EINVAL;
2558 }
bdd66ac0
OG		 2559
2560 if (!actions_match_supported(priv, exts, parse_attr, flow))
2561 return -EOPNOTSUPP;
2562
232c0013 2563 return err;
03a9d11e
OG		 2564}
2565
5fd9fc4e 2566int mlx5e_configure_flower(struct mlx5e_priv *priv,
e3a2b7ed
AV		 2567 struct tc_cls_flower_offload *f)
2568{
3bc4b7bf 2569 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 2570 struct mlx5e_tc_flow_parse_attr *parse_attr;
acff797c 2571 struct mlx5e_tc_table *tc = &priv->fs.tc;
3bc4b7bf
OG		 2572 struct mlx5e_tc_flow *flow;
2573 int attr_size, err = 0;
65ba8fb7 2574 u8 flow_flags = 0;
e3a2b7ed 2575
65ba8fb7
OG		 2576 if (esw && esw->mode == SRIOV_OFFLOADS) {
2577 flow_flags = MLX5E_TC_FLOW_ESWITCH;
2578 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf
OG		 2579 } else {
2580 flow_flags = MLX5E_TC_FLOW_NIC;
2581 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 2582 }
e3a2b7ed 2583
65ba8fb7 2584 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2585 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2586 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2587 err = -ENOMEM;
2588 goto err_free;
2589 }
2590
2591 flow->cookie = f->cookie;
65ba8fb7 2592 flow->flags = flow_flags;
e3a2b7ed 2593
17091853 2594 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV		 2595 if (err < 0)
2596 goto err_free;
2597
65ba8fb7 2598 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 2599 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123 2600 if (err < 0)
3c37745e 2601 goto err_free;
aa0cbbae 2602 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 2603 } else {
aa0cbbae 2604 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG		 2605 if (err < 0)
2606 goto err_free;
aa0cbbae 2607 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 2608 }
e3a2b7ed 2609
e3a2b7ed
AV		 2610 if (IS_ERR(flow->rule)) {
2611 err = PTR_ERR(flow->rule);
3c37745e
OG		 2612 if (err != -EAGAIN)
2613 goto err_free;
e3a2b7ed
AV		 2614 }
2615
3c37745e
OG		 2616 if (err != -EAGAIN)
2617 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2618
af1607c3
JL		 2619 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
2620 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
2621 kvfree(parse_attr);
2622
5c40348c
OG		 2623 err = rhashtable_insert_fast(&tc->ht, &flow->node,
2624 tc->ht_params);
af1607c3
JL		 2625 if (err) {
2626 mlx5e_tc_del_flow(priv, flow);
2627 kfree(flow);
2628 }
5c40348c 2629
232c0013 2630 return err;
e3a2b7ed 2631
e3a2b7ed 2632err_free:
17091853 2633 kvfree(parse_attr);
232c0013 2634 kfree(flow);
e3a2b7ed
AV		 2635 return err;
2636}
2637
2638int mlx5e_delete_flower(struct mlx5e_priv *priv,
2639 struct tc_cls_flower_offload *f)
2640{
2641 struct mlx5e_tc_flow *flow;
acff797c 2642 struct mlx5e_tc_table *tc = &priv->fs.tc;
e3a2b7ed
AV		 2643
2644 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2645 tc->ht_params);
2646 if (!flow)
2647 return -EINVAL;
2648
2649 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
2650
961e8979 2651 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 2652
2653 kfree(flow);
2654
2655 return 0;
2656}
2657
aad7e08d
AV		 2658int mlx5e_stats_flower(struct mlx5e_priv *priv,
2659 struct tc_cls_flower_offload *f)
2660{
2661 struct mlx5e_tc_table *tc = &priv->fs.tc;
2662 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 2663 struct mlx5_fc *counter;
2664 u64 bytes;
2665 u64 packets;
2666 u64 lastuse;
2667
2668 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2669 tc->ht_params);
2670 if (!flow)
2671 return -EINVAL;
2672
0b67a38f
HHZ		 2673 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2674 return 0;
2675
aad7e08d
AV		 2676 counter = mlx5_flow_rule_counter(flow->rule);
2677 if (!counter)
2678 return 0;
2679
2680 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2681
d897a638 2682 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 2683
aad7e08d
AV		 2684 return 0;
2685}
2686
e8f887ac
AV		 2687static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
2688 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2689 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2690 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2691 .automatic_shrinking = true,
2692};
2693
2694int mlx5e_tc_init(struct mlx5e_priv *priv)
2695{
acff797c 2696 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 2697
11c9c548 2698 hash_init(tc->mod_hdr_tbl);
5c65c564 2699 hash_init(tc->hairpin_tbl);
11c9c548 2700
e8f887ac
AV		 2701 tc->ht_params = mlx5e_tc_flow_ht_params;
2702 return rhashtable_init(&tc->ht, &tc->ht_params);
2703}
2704
2705static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2706{
2707 struct mlx5e_tc_flow *flow = ptr;
2708 struct mlx5e_priv *priv = arg;
2709
961e8979 2710 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 2711 kfree(flow);
2712}
2713
2714void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
2715{
acff797c 2716 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV		 2717
2718 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
2719
acff797c
MG		 2720 if (!IS_ERR_OR_NULL(tc->t)) {
2721 mlx5_destroy_flow_table(tc->t);
2722 tc->t = NULL;
e8f887ac
AV		 2723 }
2724}
Linux 6.x block layer and io_uring tree(s)