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net/mlx5: FPGA, Call DMA unmap with the right size
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
bbd00f7e 53#include "vxlan.h"
3f6d08d1 54#include "fs_core.h"
2c81bfd5 55#include "en/port.h"
e8f887ac 56
3bc4b7bf
OG		 57struct mlx5_nic_flow_attr {
58 u32 action;
59 u32 flow_tag;
2f4fe4ca 60 u32 mod_hdr_id;
5c65c564 61 u32 hairpin_tirn;
38aa51c1 62 u8 match_level;
3f6d08d1 63 struct mlx5_flow_table *hairpin_ft;
3bc4b7bf
OG		 64};
65
60bd4af8
OG		 66#define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
67
65ba8fb7 68enum {
60bd4af8
OG		 69 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
70 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
71 MLX5E_TC_FLOW_ESWITCH = BIT(MLX5E_TC_FLOW_BASE),
72 MLX5E_TC_FLOW_NIC = BIT(MLX5E_TC_FLOW_BASE + 1),
73 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE + 2),
74 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 3),
75 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 4),
65ba8fb7
OG		 76};
77
e4ad91f2
CM		 78#define MLX5E_TC_MAX_SPLITS 1
79
e8f887ac
AV		 80struct mlx5e_tc_flow {
81 struct rhash_head node;
655dc3d2 82 struct mlx5e_priv *priv;
e8f887ac 83 u64 cookie;
65ba8fb7 84 u8 flags;
e4ad91f2 85 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
11c9c548
OG		 86 struct list_head encap; /* flows sharing the same encap ID */
87 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 88 struct list_head hairpin; /* flows sharing the same hairpin */
3bc4b7bf
OG		 89 union {
90 struct mlx5_esw_flow_attr esw_attr[0];
91 struct mlx5_nic_flow_attr nic_attr[0];
92 };
e8f887ac
AV		 93};
94
17091853 95struct mlx5e_tc_flow_parse_attr {
3c37745e 96 struct ip_tunnel_info tun_info;
17091853 97 struct mlx5_flow_spec spec;
d79b6df6
OG		 98 int num_mod_hdr_actions;
99 void *mod_hdr_actions;
3c37745e 100 int mirred_ifindex;
17091853
OG		 101};
102
a54e20b4
HHZ		 103enum {
104 MLX5_HEADER_TYPE_VXLAN = 0x0,
105 MLX5_HEADER_TYPE_NVGRE = 0x1,
106};
107
acff797c 108#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 109#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 110
77ab67b7
OG		 111struct mlx5e_hairpin {
112 struct mlx5_hairpin *pair;
113
114 struct mlx5_core_dev *func_mdev;
3f6d08d1 115 struct mlx5e_priv *func_priv;
77ab67b7
OG		 116 u32 tdn;
117 u32 tirn;
3f6d08d1
OG		 118
119 int num_channels;
120 struct mlx5e_rqt indir_rqt;
121 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
122 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 123};
124
5c65c564
OG		 125struct mlx5e_hairpin_entry {
126 /* a node of a hash table which keeps all the hairpin entries */
127 struct hlist_node hairpin_hlist;
128
129 /* flows sharing the same hairpin */
130 struct list_head flows;
131
d8822868 132 u16 peer_vhca_id;
106be53b 133 u8 prio;
5c65c564
OG		 134 struct mlx5e_hairpin *hp;
135};
136
11c9c548
OG		 137struct mod_hdr_key {
138 int num_actions;
139 void *actions;
140};
141
142struct mlx5e_mod_hdr_entry {
143 /* a node of a hash table which keeps all the mod_hdr entries */
144 struct hlist_node mod_hdr_hlist;
145
146 /* flows sharing the same mod_hdr entry */
147 struct list_head flows;
148
149 struct mod_hdr_key key;
150
151 u32 mod_hdr_id;
152};
153
154#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
155
156static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
157{
158 return jhash(key->actions,
159 key->num_actions * MLX5_MH_ACT_SZ, 0);
160}
161
162static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
163 struct mod_hdr_key *b)
164{
165 if (a->num_actions != b->num_actions)
166 return 1;
167
168 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
169}
170
171static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
172 struct mlx5e_tc_flow *flow,
173 struct mlx5e_tc_flow_parse_attr *parse_attr)
174{
175 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
176 int num_actions, actions_size, namespace, err;
177 struct mlx5e_mod_hdr_entry *mh;
178 struct mod_hdr_key key;
179 bool found = false;
180 u32 hash_key;
181
182 num_actions = parse_attr->num_mod_hdr_actions;
183 actions_size = MLX5_MH_ACT_SZ * num_actions;
184
185 key.actions = parse_attr->mod_hdr_actions;
186 key.num_actions = num_actions;
187
188 hash_key = hash_mod_hdr_info(&key);
189
190 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
191 namespace = MLX5_FLOW_NAMESPACE_FDB;
192 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
193 mod_hdr_hlist, hash_key) {
194 if (!cmp_mod_hdr_info(&mh->key, &key)) {
195 found = true;
196 break;
197 }
198 }
199 } else {
200 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
201 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
202 mod_hdr_hlist, hash_key) {
203 if (!cmp_mod_hdr_info(&mh->key, &key)) {
204 found = true;
205 break;
206 }
207 }
208 }
209
210 if (found)
211 goto attach_flow;
212
213 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
214 if (!mh)
215 return -ENOMEM;
216
217 mh->key.actions = (void *)mh + sizeof(*mh);
218 memcpy(mh->key.actions, key.actions, actions_size);
219 mh->key.num_actions = num_actions;
220 INIT_LIST_HEAD(&mh->flows);
221
222 err = mlx5_modify_header_alloc(priv->mdev, namespace,
223 mh->key.num_actions,
224 mh->key.actions,
225 &mh->mod_hdr_id);
226 if (err)
227 goto out_err;
228
229 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
230 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
231 else
232 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
233
234attach_flow:
235 list_add(&flow->mod_hdr, &mh->flows);
236 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
237 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
238 else
239 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
240
241 return 0;
242
243out_err:
244 kfree(mh);
245 return err;
246}
247
248static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
249 struct mlx5e_tc_flow *flow)
250{
251 struct list_head *next = flow->mod_hdr.next;
252
253 list_del(&flow->mod_hdr);
254
255 if (list_empty(next)) {
256 struct mlx5e_mod_hdr_entry *mh;
257
258 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
259
260 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
261 hash_del(&mh->mod_hdr_hlist);
262 kfree(mh);
263 }
264}
265
77ab67b7
OG		 266static
267struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
268{
269 struct net_device *netdev;
270 struct mlx5e_priv *priv;
271
272 netdev = __dev_get_by_index(net, ifindex);
273 priv = netdev_priv(netdev);
274 return priv->mdev;
275}
276
277static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
278{
279 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
280 void *tirc;
281 int err;
282
283 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
284 if (err)
285 goto alloc_tdn_err;
286
287 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
288
289 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 290 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 291 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
292
293 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
294 if (err)
295 goto create_tir_err;
296
297 return 0;
298
299create_tir_err:
300 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
301alloc_tdn_err:
302 return err;
303}
304
305static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
306{
307 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
308 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
309}
310
3f6d08d1
OG		 311static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
312{
313 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
314 struct mlx5e_priv *priv = hp->func_priv;
315 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
316
317 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
318 hp->num_channels);
319
320 for (i = 0; i < sz; i++) {
321 ix = i;
322 if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR)
323 ix = mlx5e_bits_invert(i, ilog2(sz));
324 ix = indirection_rqt[ix];
325 rqn = hp->pair->rqn[ix];
326 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
327 }
328}
329
330static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
331{
332 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
333 struct mlx5e_priv *priv = hp->func_priv;
334 struct mlx5_core_dev *mdev = priv->mdev;
335 void *rqtc;
336 u32 *in;
337
338 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
339 in = kvzalloc(inlen, GFP_KERNEL);
340 if (!in)
341 return -ENOMEM;
342
343 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
344
345 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
346 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
347
348 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
349
350 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
351 if (!err)
352 hp->indir_rqt.enabled = true;
353
354 kvfree(in);
355 return err;
356}
357
358static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
359{
360 struct mlx5e_priv *priv = hp->func_priv;
361 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
362 int tt, i, err;
363 void *tirc;
364
365 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
366 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
367 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
368
369 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
370 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
371 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
372 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
373
374 err = mlx5_core_create_tir(hp->func_mdev, in,
375 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
376 if (err) {
377 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
378 goto err_destroy_tirs;
379 }
380 }
381 return 0;
382
383err_destroy_tirs:
384 for (i = 0; i < tt; i++)
385 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
386 return err;
387}
388
389static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
390{
391 int tt;
392
393 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
394 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
395}
396
397static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
398 struct ttc_params *ttc_params)
399{
400 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
401 int tt;
402
403 memset(ttc_params, 0, sizeof(*ttc_params));
404
405 ttc_params->any_tt_tirn = hp->tirn;
406
407 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
408 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
409
410 ft_attr->max_fte = MLX5E_NUM_TT;
411 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
412 ft_attr->prio = MLX5E_TC_PRIO;
413}
414
415static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
416{
417 struct mlx5e_priv *priv = hp->func_priv;
418 struct ttc_params ttc_params;
419 int err;
420
421 err = mlx5e_hairpin_create_indirect_rqt(hp);
422 if (err)
423 return err;
424
425 err = mlx5e_hairpin_create_indirect_tirs(hp);
426 if (err)
427 goto err_create_indirect_tirs;
428
429 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
430 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
431 if (err)
432 goto err_create_ttc_table;
433
434 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
435 hp->num_channels, hp->ttc.ft.t->id);
436
437 return 0;
438
439err_create_ttc_table:
440 mlx5e_hairpin_destroy_indirect_tirs(hp);
441err_create_indirect_tirs:
442 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
443
444 return err;
445}
446
447static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
448{
449 struct mlx5e_priv *priv = hp->func_priv;
450
451 mlx5e_destroy_ttc_table(priv, &hp->ttc);
452 mlx5e_hairpin_destroy_indirect_tirs(hp);
453 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
454}
455
77ab67b7
OG		 456static struct mlx5e_hairpin *
457mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
458 int peer_ifindex)
459{
460 struct mlx5_core_dev *func_mdev, *peer_mdev;
461 struct mlx5e_hairpin *hp;
462 struct mlx5_hairpin *pair;
463 int err;
464
465 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
466 if (!hp)
467 return ERR_PTR(-ENOMEM);
468
469 func_mdev = priv->mdev;
470 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
471
472 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
473 if (IS_ERR(pair)) {
474 err = PTR_ERR(pair);
475 goto create_pair_err;
476 }
477 hp->pair = pair;
478 hp->func_mdev = func_mdev;
3f6d08d1
OG		 479 hp->func_priv = priv;
480 hp->num_channels = params->num_channels;
77ab67b7
OG		 481
482 err = mlx5e_hairpin_create_transport(hp);
483 if (err)
484 goto create_transport_err;
485
3f6d08d1
OG		 486 if (hp->num_channels > 1) {
487 err = mlx5e_hairpin_rss_init(hp);
488 if (err)
489 goto rss_init_err;
490 }
491
77ab67b7
OG		 492 return hp;
493
3f6d08d1
OG		 494rss_init_err:
495 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 496create_transport_err:
497 mlx5_core_hairpin_destroy(hp->pair);
498create_pair_err:
499 kfree(hp);
500 return ERR_PTR(err);
501}
502
503static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
504{
3f6d08d1
OG		 505 if (hp->num_channels > 1)
506 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 507 mlx5e_hairpin_destroy_transport(hp);
508 mlx5_core_hairpin_destroy(hp->pair);
509 kvfree(hp);
510}
511
106be53b
OG		 512static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
513{
514 return (peer_vhca_id << 16 | prio);
515}
516
5c65c564 517static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 518 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 519{
520 struct mlx5e_hairpin_entry *hpe;
106be53b 521 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 522
523 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 524 hairpin_hlist, hash_key) {
525 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 526 return hpe;
527 }
528
529 return NULL;
530}
531
106be53b
OG		 532#define UNKNOWN_MATCH_PRIO 8
533
534static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
535 struct mlx5_flow_spec *spec, u8 *match_prio)
536{
537 void *headers_c, *headers_v;
538 u8 prio_val, prio_mask = 0;
539 bool vlan_present;
540
541#ifdef CONFIG_MLX5_CORE_EN_DCB
542 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
543 netdev_warn(priv->netdev,
544 "only PCP trust state supported for hairpin\n");
545 return -EOPNOTSUPP;
546 }
547#endif
548 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
549 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
550
551 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
552 if (vlan_present) {
553 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
554 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
555 }
556
557 if (!vlan_present || !prio_mask) {
558 prio_val = UNKNOWN_MATCH_PRIO;
559 } else if (prio_mask != 0x7) {
560 netdev_warn(priv->netdev,
561 "masked priority match not supported for hairpin\n");
562 return -EOPNOTSUPP;
563 }
564
565 *match_prio = prio_val;
566 return 0;
567}
568
5c65c564
OG		 569static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
570 struct mlx5e_tc_flow *flow,
571 struct mlx5e_tc_flow_parse_attr *parse_attr)
572{
573 int peer_ifindex = parse_attr->mirred_ifindex;
574 struct mlx5_hairpin_params params;
d8822868 575 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 576 struct mlx5e_hairpin_entry *hpe;
577 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 578 u64 link_speed64;
579 u32 link_speed;
106be53b 580 u8 match_prio;
d8822868 581 u16 peer_id;
5c65c564
OG		 582 int err;
583
d8822868
OG		 584 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
585 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
5c65c564
OG		 586 netdev_warn(priv->netdev, "hairpin is not supported\n");
587 return -EOPNOTSUPP;
588 }
589
d8822868 590 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
106be53b
OG		 591 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio);
592 if (err)
593 return err;
594 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 595 if (hpe)
596 goto attach_flow;
597
598 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
599 if (!hpe)
600 return -ENOMEM;
601
602 INIT_LIST_HEAD(&hpe->flows);
d8822868 603 hpe->peer_vhca_id = peer_id;
106be53b 604 hpe->prio = match_prio;
5c65c564
OG		 605
606 params.log_data_size = 15;
607 params.log_data_size = min_t(u8, params.log_data_size,
608 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
609 params.log_data_size = max_t(u8, params.log_data_size,
610 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 611
eb9180f7
OG		 612 params.log_num_packets = params.log_data_size -
613 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
614 params.log_num_packets = min_t(u8, params.log_num_packets,
615 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
616
617 params.q_counter = priv->q_counter;
3f6d08d1 618 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 619 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 620 link_speed = max_t(u32, link_speed, 50000);
621 link_speed64 = link_speed;
622 do_div(link_speed64, 50000);
623 params.num_channels = link_speed64;
624
5c65c564
OG		 625 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
626 if (IS_ERR(hp)) {
627 err = PTR_ERR(hp);
628 goto create_hairpin_err;
629 }
630
eb9180f7 631 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 632 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 633 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 634
635 hpe->hp = hp;
106be53b
OG		 636 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
637 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 638
639attach_flow:
3f6d08d1
OG		 640 if (hpe->hp->num_channels > 1) {
641 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
642 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
643 } else {
644 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
645 }
5c65c564 646 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 647
5c65c564
OG		 648 return 0;
649
650create_hairpin_err:
651 kfree(hpe);
652 return err;
653}
654
655static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
656 struct mlx5e_tc_flow *flow)
657{
658 struct list_head *next = flow->hairpin.next;
659
660 list_del(&flow->hairpin);
661
662 /* no more hairpin flows for us, release the hairpin pair */
663 if (list_empty(next)) {
664 struct mlx5e_hairpin_entry *hpe;
665
666 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
667
668 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
669 hpe->hp->pair->peer_mdev->priv.name);
670
671 mlx5e_hairpin_destroy(hpe->hp);
672 hash_del(&hpe->hairpin_hlist);
673 kfree(hpe);
674 }
675}
676
74491de9
MB		 677static struct mlx5_flow_handle *
678mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 679 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 680 struct mlx5e_tc_flow *flow)
e8f887ac 681{
aa0cbbae 682 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 683 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 684 struct mlx5_flow_destination dest[2] = {};
66958ed9 685 struct mlx5_flow_act flow_act = {
3bc4b7bf 686 .action = attr->action,
a9db0ecf 687 .has_flow_tag = true,
3bc4b7bf 688 .flow_tag = attr->flow_tag,
66958ed9
HHZ		 689 .encap_id = 0,
690 };
aad7e08d 691 struct mlx5_fc *counter = NULL;
74491de9 692 struct mlx5_flow_handle *rule;
e8f887ac 693 bool table_created = false;
5c65c564 694 int err, dest_ix = 0;
e8f887ac 695
3f6d08d1
OG		 696 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
697 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr);
698 if (err) {
699 rule = ERR_PTR(err);
700 goto err_add_hairpin_flow;
701 }
702 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
703 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
704 dest[dest_ix].ft = attr->hairpin_ft;
705 } else {
5c65c564
OG		 706 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
707 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 708 }
709 dest_ix++;
3f6d08d1
OG		 710 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
711 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
712 dest[dest_ix].ft = priv->fs.vlan.ft.t;
713 dest_ix++;
5c65c564 714 }
aad7e08d 715
5c65c564
OG		 716 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
717 counter = mlx5_fc_create(dev, true);
718 if (IS_ERR(counter)) {
719 rule = ERR_CAST(counter);
720 goto err_fc_create;
721 }
722 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
723 dest[dest_ix].counter = counter;
724 dest_ix++;
aad7e08d
AV		 725 }
726
2f4fe4ca 727 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 728 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 729 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG		 730 kfree(parse_attr->mod_hdr_actions);
731 if (err) {
732 rule = ERR_PTR(err);
733 goto err_create_mod_hdr_id;
734 }
735 }
736
acff797c 737 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 738 int tc_grp_size, tc_tbl_size;
739 u32 max_flow_counter;
740
741 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
742 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
743
744 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
745
746 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
747 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
748
acff797c
MG		 749 priv->fs.tc.t =
750 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
751 MLX5E_TC_PRIO,
21b9c144 752 tc_tbl_size,
acff797c 753 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 754 MLX5E_TC_FT_LEVEL, 0);
acff797c 755 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV		 756 netdev_err(priv->netdev,
757 "Failed to create tc offload table\n");
aad7e08d
AV		 758 rule = ERR_CAST(priv->fs.tc.t);
759 goto err_create_ft;
e8f887ac
AV		 760 }
761
762 table_created = true;
763 }
764
38aa51c1
OG		 765 if (attr->match_level != MLX5_MATCH_NONE)
766 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
767
17091853 768 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
5c65c564 769 &flow_act, dest, dest_ix);
aad7e08d
AV		 770
771 if (IS_ERR(rule))
772 goto err_add_rule;
773
774 return rule;
e8f887ac 775
aad7e08d
AV		 776err_add_rule:
777 if (table_created) {
acff797c
MG		 778 mlx5_destroy_flow_table(priv->fs.tc.t);
779 priv->fs.tc.t = NULL;
e8f887ac 780 }
aad7e08d 781err_create_ft:
2f4fe4ca 782 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 783 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 784err_create_mod_hdr_id:
aad7e08d 785 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 786err_fc_create:
787 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
788 mlx5e_hairpin_flow_del(priv, flow);
789err_add_hairpin_flow:
e8f887ac
AV		 790 return rule;
791}
792
d85cdccb
OG		 793static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
794 struct mlx5e_tc_flow *flow)
795{
513f8f7f 796 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 797 struct mlx5_fc *counter = NULL;
798
e4ad91f2
CM		 799 counter = mlx5_flow_rule_counter(flow->rule[0]);
800 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 801 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 802
b3a433de 803 if (!mlx5e_tc_num_filters(priv) && priv->fs.tc.t) {
d85cdccb
OG		 804 mlx5_destroy_flow_table(priv->fs.tc.t);
805 priv->fs.tc.t = NULL;
806 }
2f4fe4ca 807
513f8f7f 808 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 809 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 810
811 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
812 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 813}
814
aa0cbbae
OG		 815static void mlx5e_detach_encap(struct mlx5e_priv *priv,
816 struct mlx5e_tc_flow *flow);
817
3c37745e
OG		 818static int mlx5e_attach_encap(struct mlx5e_priv *priv,
819 struct ip_tunnel_info *tun_info,
820 struct net_device *mirred_dev,
821 struct net_device **encap_dev,
822 struct mlx5e_tc_flow *flow);
823
74491de9
MB		 824static struct mlx5_flow_handle *
825mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 826 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 827 struct mlx5e_tc_flow *flow)
adb4c123
OG		 828{
829 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae 830 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
3c37745e
OG		 831 struct net_device *out_dev, *encap_dev = NULL;
832 struct mlx5_flow_handle *rule = NULL;
833 struct mlx5e_rep_priv *rpriv;
834 struct mlx5e_priv *out_priv;
8b32580d
OG		 835 int err;
836
3c37745e
OG		 837 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
838 out_dev = __dev_get_by_index(dev_net(priv->netdev),
839 attr->parse_attr->mirred_ifindex);
840 err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
841 out_dev, &encap_dev, flow);
842 if (err) {
843 rule = ERR_PTR(err);
844 if (err != -EAGAIN)
845 goto err_attach_encap;
846 }
847 out_priv = netdev_priv(encap_dev);
848 rpriv = out_priv->ppriv;
592d3651
CM		 849 attr->out_rep[attr->out_count] = rpriv->rep;
850 attr->out_mdev[attr->out_count++] = out_priv->mdev;
3c37745e
OG		 851 }
852
8b32580d 853 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG		 854 if (err) {
855 rule = ERR_PTR(err);
856 goto err_add_vlan;
857 }
adb4c123 858
d7e75a32 859 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 860 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32
OG		 861 kfree(parse_attr->mod_hdr_actions);
862 if (err) {
863 rule = ERR_PTR(err);
864 goto err_mod_hdr;
865 }
866 }
867
3c37745e
OG		 868 /* we get here if (1) there's no error (rule being null) or when
869 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
870 */
871 if (rule != ERR_PTR(-EAGAIN)) {
872 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
873 if (IS_ERR(rule))
874 goto err_add_rule;
e4ad91f2
CM		 875
876 if (attr->mirror_count) {
877 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, &parse_attr->spec, attr);
878 if (IS_ERR(flow->rule[1]))
879 goto err_fwd_rule;
880 }
3c37745e 881 }
aa0cbbae
OG		 882 return rule;
883
e4ad91f2
CM		 884err_fwd_rule:
885 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
886 rule = flow->rule[1];
aa0cbbae 887err_add_rule:
513f8f7f 888 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 889 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 890err_mod_hdr:
aa0cbbae
OG		 891 mlx5_eswitch_del_vlan_action(esw, attr);
892err_add_vlan:
893 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
894 mlx5e_detach_encap(priv, flow);
3c37745e 895err_attach_encap:
aa0cbbae
OG		 896 return rule;
897}
d85cdccb
OG		 898
899static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
900 struct mlx5e_tc_flow *flow)
901{
902 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 903 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 904
232c0013
HHZ		 905 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
906 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
e4ad91f2
CM		 907 if (attr->mirror_count)
908 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[1], attr);
909 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
232c0013 910 }
d85cdccb 911
513f8f7f 912 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 913
513f8f7f 914 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
d85cdccb 915 mlx5e_detach_encap(priv, flow);
513f8f7f 916 kvfree(attr->parse_attr);
232c0013 917 }
d7e75a32 918
513f8f7f 919 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 920 mlx5e_detach_mod_hdr(priv, flow);
d85cdccb
OG		 921}
922
232c0013
HHZ		 923void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
924 struct mlx5e_encap_entry *e)
925{
3c37745e
OG		 926 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
927 struct mlx5_esw_flow_attr *esw_attr;
232c0013
HHZ		 928 struct mlx5e_tc_flow *flow;
929 int err;
930
931 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
932 e->encap_size, e->encap_header,
933 &e->encap_id);
934 if (err) {
935 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
936 err);
937 return;
938 }
939 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 940 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 941
942 list_for_each_entry(flow, &e->flows, encap) {
3c37745e
OG		 943 esw_attr = flow->esw_attr;
944 esw_attr->encap_id = e->encap_id;
e4ad91f2
CM		 945 flow->rule[0] = mlx5_eswitch_add_offloaded_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
946 if (IS_ERR(flow->rule[0])) {
947 err = PTR_ERR(flow->rule[0]);
232c0013
HHZ		 948 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
949 err);
950 continue;
951 }
e4ad91f2
CM		 952
953 if (esw_attr->mirror_count) {
954 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, &esw_attr->parse_attr->spec, esw_attr);
955 if (IS_ERR(flow->rule[1])) {
956 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], esw_attr);
957 err = PTR_ERR(flow->rule[1]);
958 mlx5_core_warn(priv->mdev, "Failed to update cached mirror flow, %d\n",
959 err);
960 continue;
961 }
962 }
963
232c0013
HHZ		 964 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
965 }
966}
967
968void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
969 struct mlx5e_encap_entry *e)
970{
3c37745e 971 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
232c0013 972 struct mlx5e_tc_flow *flow;
232c0013
HHZ		 973
974 list_for_each_entry(flow, &e->flows, encap) {
975 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
e4ad91f2
CM		 976 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
977
232c0013 978 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
e4ad91f2
CM		 979 if (attr->mirror_count)
980 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[1], attr);
981 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
232c0013
HHZ		 982 }
983 }
984
985 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
986 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
987 mlx5_encap_dealloc(priv->mdev, e->encap_id);
988 }
989}
990
f6dfb4c3
HHZ		 991void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
992{
993 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
994 u64 bytes, packets, lastuse = 0;
995 struct mlx5e_tc_flow *flow;
996 struct mlx5e_encap_entry *e;
997 struct mlx5_fc *counter;
998 struct neigh_table *tbl;
999 bool neigh_used = false;
1000 struct neighbour *n;
1001
1002 if (m_neigh->family == AF_INET)
1003 tbl = &arp_tbl;
1004#if IS_ENABLED(CONFIG_IPV6)
1005 else if (m_neigh->family == AF_INET6)
423c9db2 1006 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1007#endif
1008 else
1009 return;
1010
1011 list_for_each_entry(e, &nhe->encap_list, encap_list) {
1012 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1013 continue;
1014 list_for_each_entry(flow, &e->flows, encap) {
1015 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
e4ad91f2 1016 counter = mlx5_flow_rule_counter(flow->rule[0]);
f6dfb4c3
HHZ		 1017 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1018 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1019 neigh_used = true;
1020 break;
1021 }
1022 }
1023 }
e36d4810
RD		 1024 if (neigh_used)
1025 break;
f6dfb4c3
HHZ		 1026 }
1027
1028 if (neigh_used) {
1029 nhe->reported_lastuse = jiffies;
1030
1031 /* find the relevant neigh according to the cached device and
1032 * dst ip pair
1033 */
1034 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
1035 if (!n) {
1036 WARN(1, "The neighbour already freed\n");
1037 return;
1038 }
1039
1040 neigh_event_send(n, NULL);
1041 neigh_release(n);
1042 }
1043}
1044
d85cdccb
OG		 1045static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1046 struct mlx5e_tc_flow *flow)
1047{
5067b602
RD		 1048 struct list_head *next = flow->encap.next;
1049
1050 list_del(&flow->encap);
1051 if (list_empty(next)) {
c1ae1152 1052 struct mlx5e_encap_entry *e;
5067b602 1053
c1ae1152 1054 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1055 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1056
1057 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
5067b602 1058 mlx5_encap_dealloc(priv->mdev, e->encap_id);
232c0013 1059
cdc5a7f3 1060 hash_del_rcu(&e->encap_hlist);
232c0013 1061 kfree(e->encap_header);
5067b602
RD		 1062 kfree(e);
1063 }
1064}
1065
e8f887ac 1066static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1067 struct mlx5e_tc_flow *flow)
e8f887ac 1068{
d85cdccb
OG		 1069 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1070 mlx5e_tc_del_fdb_flow(priv, flow);
1071 else
1072 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 1073}
1074
bbd00f7e
HHZ		 1075static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
1076 struct tc_cls_flower_offload *f)
1077{
1078 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1079 outer_headers);
1080 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1081 outer_headers);
1082 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1083 misc_parameters);
1084 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1085 misc_parameters);
1086
1087 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
1088 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1089
1090 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
1091 struct flow_dissector_key_keyid *key =
1092 skb_flow_dissector_target(f->dissector,
1093 FLOW_DISSECTOR_KEY_ENC_KEYID,
1094 f->key);
1095 struct flow_dissector_key_keyid *mask =
1096 skb_flow_dissector_target(f->dissector,
1097 FLOW_DISSECTOR_KEY_ENC_KEYID,
1098 f->mask);
1099 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
1100 be32_to_cpu(mask->keyid));
1101 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
1102 be32_to_cpu(key->keyid));
1103 }
1104}
1105
1106static int parse_tunnel_attr(struct mlx5e_priv *priv,
1107 struct mlx5_flow_spec *spec,
1108 struct tc_cls_flower_offload *f)
1109{
1110 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1111 outer_headers);
1112 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1113 outer_headers);
1114
2e72eb43
OG		 1115 struct flow_dissector_key_control *enc_control =
1116 skb_flow_dissector_target(f->dissector,
1117 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1118 f->key);
1119
bbd00f7e
HHZ		 1120 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
1121 struct flow_dissector_key_ports *key =
1122 skb_flow_dissector_target(f->dissector,
1123 FLOW_DISSECTOR_KEY_ENC_PORTS,
1124 f->key);
1125 struct flow_dissector_key_ports *mask =
1126 skb_flow_dissector_target(f->dissector,
1127 FLOW_DISSECTOR_KEY_ENC_PORTS,
1128 f->mask);
1ad9a00a 1129 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4 1130 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5ed99fb4 1131 struct net_device *up_dev = uplink_rpriv->netdev;
1ad9a00a 1132 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ		 1133
1134 /* Full udp dst port must be given */
1135 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 1136 goto vxlan_match_offload_err;
bbd00f7e 1137
1ad9a00a 1138 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 1139 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
1140 parse_vxlan_attr(spec, f);
2fcd82e9
OG		 1141 else {
1142 netdev_warn(priv->netdev,
1143 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 1144 return -EOPNOTSUPP;
2fcd82e9 1145 }
bbd00f7e
HHZ		 1146
1147 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1148 udp_dport, ntohs(mask->dst));
1149 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1150 udp_dport, ntohs(key->dst));
1151
cd377663
OG		 1152 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1153 udp_sport, ntohs(mask->src));
1154 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1155 udp_sport, ntohs(key->src));
bbd00f7e 1156 } else { /* udp dst port must be given */
2fcd82e9
OG		 1157vxlan_match_offload_err:
1158 netdev_warn(priv->netdev,
1159 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
1160 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1161 }
1162
2e72eb43 1163 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 1164 struct flow_dissector_key_ipv4_addrs *key =
1165 skb_flow_dissector_target(f->dissector,
1166 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1167 f->key);
1168 struct flow_dissector_key_ipv4_addrs *mask =
1169 skb_flow_dissector_target(f->dissector,
1170 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1171 f->mask);
1172 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1173 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1174 ntohl(mask->src));
1175 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1176 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1177 ntohl(key->src));
1178
1179 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1180 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1181 ntohl(mask->dst));
1182 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1183 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1184 ntohl(key->dst));
bbd00f7e 1185
2e72eb43
OG		 1186 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1187 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 1188 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1189 struct flow_dissector_key_ipv6_addrs *key =
1190 skb_flow_dissector_target(f->dissector,
1191 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1192 f->key);
1193 struct flow_dissector_key_ipv6_addrs *mask =
1194 skb_flow_dissector_target(f->dissector,
1195 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1196 f->mask);
1197
1198 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1199 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1200 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1201 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1202 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1203 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1204
1205 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1206 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1207 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1208 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1209 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1210 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1211
1212 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1213 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1214 }
bbd00f7e
HHZ		 1215
1216 /* Enforce DMAC when offloading incoming tunneled flows.
1217 * Flow counters require a match on the DMAC.
1218 */
1219 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1220 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1221 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1222 dmac_47_16), priv->netdev->dev_addr);
1223
1224 /* let software handle IP fragments */
1225 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1226 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1227
1228 return 0;
1229}
1230
de0af0bf
RD		 1231static int __parse_cls_flower(struct mlx5e_priv *priv,
1232 struct mlx5_flow_spec *spec,
1233 struct tc_cls_flower_offload *f,
d708f902 1234 u8 *match_level)
e3a2b7ed 1235{
c5bb1730
MG		 1236 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1237 outer_headers);
1238 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1239 outer_headers);
e3a2b7ed
AV		 1240 u16 addr_type = 0;
1241 u8 ip_proto = 0;
1242
d708f902 1243 *match_level = MLX5_MATCH_NONE;
de0af0bf 1244
e3a2b7ed
AV		 1245 if (f->dissector->used_keys &
1246 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1247 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1248 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1249 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV		 1250 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1251 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1252 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1253 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1254 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1255 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1256 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1257 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b
OG		 1258 BIT(FLOW_DISSECTOR_KEY_TCP) |
1259 BIT(FLOW_DISSECTOR_KEY_IP))) {
e3a2b7ed
AV		 1260 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1261 f->dissector->used_keys);
1262 return -EOPNOTSUPP;
1263 }
1264
bbd00f7e
HHZ		 1265 if ((dissector_uses_key(f->dissector,
1266 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1267 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1268 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1269 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1270 struct flow_dissector_key_control *key =
1271 skb_flow_dissector_target(f->dissector,
1272 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1273 f->key);
1274 switch (key->addr_type) {
1275 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1276 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 1277 if (parse_tunnel_attr(priv, spec, f))
1278 return -EOPNOTSUPP;
1279 break;
1280 default:
1281 return -EOPNOTSUPP;
1282 }
1283
1284 /* In decap flow, header pointers should point to the inner
1285 * headers, outer header were already set by parse_tunnel_attr
1286 */
1287 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1288 inner_headers);
1289 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1290 inner_headers);
1291 }
1292
e3a2b7ed
AV		 1293 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1294 struct flow_dissector_key_eth_addrs *key =
1295 skb_flow_dissector_target(f->dissector,
1296 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1297 f->key);
1298 struct flow_dissector_key_eth_addrs *mask =
1299 skb_flow_dissector_target(f->dissector,
1300 FLOW_DISSECTOR_KEY_ETH_ADDRS,
1301 f->mask);
1302
1303 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1304 dmac_47_16),
1305 mask->dst);
1306 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1307 dmac_47_16),
1308 key->dst);
1309
1310 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1311 smac_47_16),
1312 mask->src);
1313 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1314 smac_47_16),
1315 key->src);
54782900
OG		 1316
1317 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
d708f902 1318 *match_level = MLX5_MATCH_L2;
e3a2b7ed
AV		 1319 }
1320
095b6cfd
OG		 1321 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1322 struct flow_dissector_key_vlan *key =
1323 skb_flow_dissector_target(f->dissector,
1324 FLOW_DISSECTOR_KEY_VLAN,
1325 f->key);
1326 struct flow_dissector_key_vlan *mask =
1327 skb_flow_dissector_target(f->dissector,
1328 FLOW_DISSECTOR_KEY_VLAN,
1329 f->mask);
358d79a4 1330 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY		 1331 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
1332 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG		 1333
1334 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1335 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 1336
1337 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1338 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
54782900 1339
d708f902 1340 *match_level = MLX5_MATCH_L2;
54782900
OG		 1341 }
1342 }
1343
1344 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1345 struct flow_dissector_key_basic *key =
1346 skb_flow_dissector_target(f->dissector,
1347 FLOW_DISSECTOR_KEY_BASIC,
1348 f->key);
1349 struct flow_dissector_key_basic *mask =
1350 skb_flow_dissector_target(f->dissector,
1351 FLOW_DISSECTOR_KEY_BASIC,
1352 f->mask);
1353 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1354 ntohs(mask->n_proto));
1355 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1356 ntohs(key->n_proto));
1357
1358 if (mask->n_proto)
d708f902 1359 *match_level = MLX5_MATCH_L2;
54782900
OG		 1360 }
1361
1362 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1363 struct flow_dissector_key_control *key =
1364 skb_flow_dissector_target(f->dissector,
1365 FLOW_DISSECTOR_KEY_CONTROL,
1366 f->key);
1367
1368 struct flow_dissector_key_control *mask =
1369 skb_flow_dissector_target(f->dissector,
1370 FLOW_DISSECTOR_KEY_CONTROL,
1371 f->mask);
1372 addr_type = key->addr_type;
1373
1374 /* the HW doesn't support frag first/later */
1375 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1376 return -EOPNOTSUPP;
1377
1378 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1379 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1380 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1381 key->flags & FLOW_DIS_IS_FRAGMENT);
1382
1383 /* the HW doesn't need L3 inline to match on frag=no */
1384 if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
d708f902 1385 *match_level = MLX5_INLINE_MODE_L2;
54782900
OG		 1386 /* *** L2 attributes parsing up to here *** */
1387 else
d708f902 1388 *match_level = MLX5_INLINE_MODE_IP;
095b6cfd
OG		 1389 }
1390 }
1391
54782900
OG		 1392 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1393 struct flow_dissector_key_basic *key =
1394 skb_flow_dissector_target(f->dissector,
1395 FLOW_DISSECTOR_KEY_BASIC,
1396 f->key);
1397 struct flow_dissector_key_basic *mask =
1398 skb_flow_dissector_target(f->dissector,
1399 FLOW_DISSECTOR_KEY_BASIC,
1400 f->mask);
1401 ip_proto = key->ip_proto;
1402
1403 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1404 mask->ip_proto);
1405 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1406 key->ip_proto);
1407
1408 if (mask->ip_proto)
d708f902 1409 *match_level = MLX5_MATCH_L3;
54782900
OG		 1410 }
1411
e3a2b7ed
AV		 1412 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1413 struct flow_dissector_key_ipv4_addrs *key =
1414 skb_flow_dissector_target(f->dissector,
1415 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1416 f->key);
1417 struct flow_dissector_key_ipv4_addrs *mask =
1418 skb_flow_dissector_target(f->dissector,
1419 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1420 f->mask);
1421
1422 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1423 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1424 &mask->src, sizeof(mask->src));
1425 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1426 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1427 &key->src, sizeof(key->src));
1428 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1429 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1430 &mask->dst, sizeof(mask->dst));
1431 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1432 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1433 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1434
1435 if (mask->src || mask->dst)
d708f902 1436 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1437 }
1438
1439 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1440 struct flow_dissector_key_ipv6_addrs *key =
1441 skb_flow_dissector_target(f->dissector,
1442 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1443 f->key);
1444 struct flow_dissector_key_ipv6_addrs *mask =
1445 skb_flow_dissector_target(f->dissector,
1446 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1447 f->mask);
1448
1449 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1450 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1451 &mask->src, sizeof(mask->src));
1452 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1453 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1454 &key->src, sizeof(key->src));
1455
1456 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1457 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1458 &mask->dst, sizeof(mask->dst));
1459 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1460 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1461 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1462
1463 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1464 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
d708f902 1465 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1466 }
1467
1f97a526
OG		 1468 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1469 struct flow_dissector_key_ip *key =
1470 skb_flow_dissector_target(f->dissector,
1471 FLOW_DISSECTOR_KEY_IP,
1472 f->key);
1473 struct flow_dissector_key_ip *mask =
1474 skb_flow_dissector_target(f->dissector,
1475 FLOW_DISSECTOR_KEY_IP,
1476 f->mask);
1477
1478 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1479 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1480
1481 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1482 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1483
a8ade55f
OG		 1484 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1485 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 1486
a8ade55f
OG		 1487 if (mask->ttl &&
1488 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
1489 ft_field_support.outer_ipv4_ttl))
1f97a526 1490 return -EOPNOTSUPP;
a8ade55f
OG		 1491
1492 if (mask->tos || mask->ttl)
d708f902 1493 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1494 }
1495
54782900
OG		 1496 /* *** L3 attributes parsing up to here *** */
1497
e3a2b7ed
AV		 1498 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1499 struct flow_dissector_key_ports *key =
1500 skb_flow_dissector_target(f->dissector,
1501 FLOW_DISSECTOR_KEY_PORTS,
1502 f->key);
1503 struct flow_dissector_key_ports *mask =
1504 skb_flow_dissector_target(f->dissector,
1505 FLOW_DISSECTOR_KEY_PORTS,
1506 f->mask);
1507 switch (ip_proto) {
1508 case IPPROTO_TCP:
1509 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1510 tcp_sport, ntohs(mask->src));
1511 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1512 tcp_sport, ntohs(key->src));
1513
1514 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1515 tcp_dport, ntohs(mask->dst));
1516 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1517 tcp_dport, ntohs(key->dst));
1518 break;
1519
1520 case IPPROTO_UDP:
1521 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1522 udp_sport, ntohs(mask->src));
1523 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1524 udp_sport, ntohs(key->src));
1525
1526 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1527 udp_dport, ntohs(mask->dst));
1528 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1529 udp_dport, ntohs(key->dst));
1530 break;
1531 default:
1532 netdev_err(priv->netdev,
1533 "Only UDP and TCP transport are supported\n");
1534 return -EINVAL;
1535 }
de0af0bf
RD		 1536
1537 if (mask->src || mask->dst)
d708f902 1538 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1539 }
1540
e77834ec
OG		 1541 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1542 struct flow_dissector_key_tcp *key =
1543 skb_flow_dissector_target(f->dissector,
1544 FLOW_DISSECTOR_KEY_TCP,
1545 f->key);
1546 struct flow_dissector_key_tcp *mask =
1547 skb_flow_dissector_target(f->dissector,
1548 FLOW_DISSECTOR_KEY_TCP,
1549 f->mask);
1550
1551 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1552 ntohs(mask->flags));
1553 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1554 ntohs(key->flags));
1555
1556 if (mask->flags)
d708f902 1557 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1558 }
1559
e3a2b7ed
AV		 1560 return 0;
1561}
1562
de0af0bf 1563static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1564 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 1565 struct mlx5_flow_spec *spec,
1566 struct tc_cls_flower_offload *f)
1567{
1568 struct mlx5_core_dev *dev = priv->mdev;
1569 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1570 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1571 struct mlx5_eswitch_rep *rep;
d708f902 1572 u8 match_level;
de0af0bf
RD		 1573 int err;
1574
d708f902 1575 err = __parse_cls_flower(priv, spec, f, &match_level);
de0af0bf 1576
1d447a39
SM		 1577 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1578 rep = rpriv->rep;
1579 if (rep->vport != FDB_UPLINK_VPORT &&
1580 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1581 esw->offloads.inline_mode < match_level)) {
de0af0bf
RD		 1582 netdev_warn(priv->netdev,
1583 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1584 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1585 return -EOPNOTSUPP;
1586 }
1587 }
1588
38aa51c1
OG		 1589 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1590 flow->esw_attr->match_level = match_level;
1591 else
1592 flow->nic_attr->match_level = match_level;
1593
de0af0bf
RD		 1594 return err;
1595}
1596
d79b6df6
OG		 1597struct pedit_headers {
1598 struct ethhdr eth;
1599 struct iphdr ip4;
1600 struct ipv6hdr ip6;
1601 struct tcphdr tcp;
1602 struct udphdr udp;
1603};
1604
1605static int pedit_header_offsets[] = {
1606 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1607 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1608 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1609 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1610 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1611};
1612
1613#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1614
1615static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1616 struct pedit_headers *masks,
1617 struct pedit_headers *vals)
1618{
1619 u32 *curr_pmask, *curr_pval;
1620
1621 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1622 goto out_err;
1623
1624 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1625 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1626
1627 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1628 goto out_err;
1629
1630 *curr_pmask |= mask;
1631 *curr_pval |= (val & mask);
1632
1633 return 0;
1634
1635out_err:
1636 return -EOPNOTSUPP;
1637}
1638
1639struct mlx5_fields {
1640 u8 field;
1641 u8 size;
1642 u32 offset;
1643};
1644
a8e4f0c4
OG		 1645#define OFFLOAD(fw_field, size, field, off) \
1646 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1647
d79b6df6 1648static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1649 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1650 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1651 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1652 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1653 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1654
1655 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1656 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1657 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1658
1659 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1660 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1661 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1662 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1663 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1664 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1665 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1666 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1667 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1668
1669 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1670 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1671 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1672
1673 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1674 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1675};
1676
1677/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1678 * max from the SW pedit action. On success, it says how many HW actions were
1679 * actually parsed.
1680 */
1681static int offload_pedit_fields(struct pedit_headers *masks,
1682 struct pedit_headers *vals,
1683 struct mlx5e_tc_flow_parse_attr *parse_attr)
1684{
1685 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1686 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1687 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1688 struct mlx5_fields *f;
1689 u8 cmd, field_bsize;
e3ca4e05 1690 u32 s_mask, a_mask;
d79b6df6 1691 unsigned long mask;
2b64beba
OG		 1692 __be32 mask_be32;
1693 __be16 mask_be16;
d79b6df6
OG		 1694 void *action;
1695
1696 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1697 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1698 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1699 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1700
1701 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1702 action = parse_attr->mod_hdr_actions;
1703 max_actions = parse_attr->num_mod_hdr_actions;
1704 nactions = 0;
1705
1706 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1707 f = &fields[i];
1708 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1709 s_mask = 0;
1710 a_mask = 0;
d79b6df6
OG		 1711
1712 s_masks_p = (void *)set_masks + f->offset;
1713 a_masks_p = (void *)add_masks + f->offset;
1714
1715 memcpy(&s_mask, s_masks_p, f->size);
1716 memcpy(&a_mask, a_masks_p, f->size);
1717
1718 if (!s_mask && !a_mask) /* nothing to offload here */
1719 continue;
1720
1721 if (s_mask && a_mask) {
1722 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1723 return -EOPNOTSUPP;
1724 }
1725
1726 if (nactions == max_actions) {
1727 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1728 return -EOPNOTSUPP;
1729 }
1730
1731 if (s_mask) {
1732 cmd = MLX5_ACTION_TYPE_SET;
1733 mask = s_mask;
1734 vals_p = (void *)set_vals + f->offset;
1735 /* clear to denote we consumed this field */
1736 memset(s_masks_p, 0, f->size);
1737 } else {
1738 cmd = MLX5_ACTION_TYPE_ADD;
1739 mask = a_mask;
1740 vals_p = (void *)add_vals + f->offset;
1741 /* clear to denote we consumed this field */
1742 memset(a_masks_p, 0, f->size);
1743 }
1744
d79b6df6 1745 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1746
2b64beba
OG		 1747 if (field_bsize == 32) {
1748 mask_be32 = *(__be32 *)&mask;
1749 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1750 } else if (field_bsize == 16) {
1751 mask_be16 = *(__be16 *)&mask;
1752 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1753 }
1754
d79b6df6 1755 first = find_first_bit(&mask, field_bsize);
2b64beba 1756 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1757 last = find_last_bit(&mask, field_bsize);
2b64beba
OG		 1758 if (first < next_z && next_z < last) {
1759 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1760 mask);
1761 return -EOPNOTSUPP;
1762 }
1763
1764 MLX5_SET(set_action_in, action, action_type, cmd);
1765 MLX5_SET(set_action_in, action, field, f->field);
1766
1767 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1768 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1769 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1770 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1771 }
1772
1773 if (field_bsize == 32)
2b64beba 1774 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1775 else if (field_bsize == 16)
2b64beba 1776 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1777 else if (field_bsize == 8)
2b64beba 1778 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1779
1780 action += action_size;
1781 nactions++;
1782 }
1783
1784 parse_attr->num_mod_hdr_actions = nactions;
1785 return 0;
1786}
1787
1788static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1789 const struct tc_action *a, int namespace,
1790 struct mlx5e_tc_flow_parse_attr *parse_attr)
1791{
1792 int nkeys, action_size, max_actions;
1793
1794 nkeys = tcf_pedit_nkeys(a);
1795 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1796
1797 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1798 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1799 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1800 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1801
1802 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1803 max_actions = min(max_actions, nkeys * 16);
1804
1805 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1806 if (!parse_attr->mod_hdr_actions)
1807 return -ENOMEM;
1808
1809 parse_attr->num_mod_hdr_actions = max_actions;
1810 return 0;
1811}
1812
1813static const struct pedit_headers zero_masks = {};
1814
1815static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1816 const struct tc_action *a, int namespace,
1817 struct mlx5e_tc_flow_parse_attr *parse_attr)
1818{
1819 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1820 int nkeys, i, err = -EOPNOTSUPP;
1821 u32 mask, val, offset;
1822 u8 cmd, htype;
1823
1824 nkeys = tcf_pedit_nkeys(a);
1825
1826 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1827 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1828
1829 for (i = 0; i < nkeys; i++) {
1830 htype = tcf_pedit_htype(a, i);
1831 cmd = tcf_pedit_cmd(a, i);
1832 err = -EOPNOTSUPP; /* can't be all optimistic */
1833
1834 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
b3a433de 1835 netdev_warn(priv->netdev, "legacy pedit isn't offloaded\n");
d79b6df6
OG		 1836 goto out_err;
1837 }
1838
1839 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
b3a433de 1840 netdev_warn(priv->netdev, "pedit cmd %d isn't offloaded\n", cmd);
d79b6df6
OG		 1841 goto out_err;
1842 }
1843
1844 mask = tcf_pedit_mask(a, i);
1845 val = tcf_pedit_val(a, i);
1846 offset = tcf_pedit_offset(a, i);
1847
1848 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1849 if (err)
1850 goto out_err;
1851 }
1852
1853 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1854 if (err)
1855 goto out_err;
1856
1857 err = offload_pedit_fields(masks, vals, parse_attr);
1858 if (err < 0)
1859 goto out_dealloc_parsed_actions;
1860
1861 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1862 cmd_masks = &masks[cmd];
1863 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
b3a433de 1864 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 1865 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1866 16, 1, cmd_masks, sizeof(zero_masks), true);
1867 err = -EOPNOTSUPP;
1868 goto out_dealloc_parsed_actions;
1869 }
1870 }
1871
1872 return 0;
1873
1874out_dealloc_parsed_actions:
1875 kfree(parse_attr->mod_hdr_actions);
1876out_err:
1877 return err;
1878}
1879
26c02749
OG		 1880static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1881{
1882 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1883 TCA_CSUM_UPDATE_FLAG_UDP;
1884
1885 /* The HW recalcs checksums only if re-writing headers */
1886 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1887 netdev_warn(priv->netdev,
1888 "TC csum action is only offloaded with pedit\n");
1889 return false;
1890 }
1891
1892 if (update_flags & ~prot_flags) {
1893 netdev_warn(priv->netdev,
1894 "can't offload TC csum action for some header/s - flags %#x\n",
1895 update_flags);
1896 return false;
1897 }
1898
1899 return true;
1900}
1901
bdd66ac0
OG		 1902static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
1903 struct tcf_exts *exts)
1904{
1905 const struct tc_action *a;
1906 bool modify_ip_header;
1907 LIST_HEAD(actions);
1908 u8 htype, ip_proto;
1909 void *headers_v;
1910 u16 ethertype;
1911 int nkeys, i;
1912
1913 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1914 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
1915
1916 /* for non-IP we only re-write MACs, so we're okay */
1917 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
1918 goto out_ok;
1919
1920 modify_ip_header = false;
1921 tcf_exts_to_list(exts, &actions);
1922 list_for_each_entry(a, &actions, list) {
1923 if (!is_tcf_pedit(a))
1924 continue;
1925
1926 nkeys = tcf_pedit_nkeys(a);
1927 for (i = 0; i < nkeys; i++) {
1928 htype = tcf_pedit_htype(a, i);
1929 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
1930 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
1931 modify_ip_header = true;
1932 break;
1933 }
1934 }
1935 }
1936
1937 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 1938 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
1939 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
bdd66ac0
OG		 1940 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
1941 return false;
1942 }
1943
1944out_ok:
1945 return true;
1946}
1947
1948static bool actions_match_supported(struct mlx5e_priv *priv,
1949 struct tcf_exts *exts,
1950 struct mlx5e_tc_flow_parse_attr *parse_attr,
1951 struct mlx5e_tc_flow *flow)
1952{
1953 u32 actions;
1954
1955 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1956 actions = flow->esw_attr->action;
1957 else
1958 actions = flow->nic_attr->action;
1959
1960 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1961 return modify_header_match_supported(&parse_attr->spec, exts);
1962
1963 return true;
1964}
1965
5c65c564
OG		 1966static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
1967{
1968 struct mlx5_core_dev *fmdev, *pmdev;
1969 u16 func_id, peer_id;
1970
1971 fmdev = priv->mdev;
1972 pmdev = peer_priv->mdev;
1973
1974 func_id = (u16)((fmdev->pdev->bus->number << 8) | PCI_SLOT(fmdev->pdev->devfn));
1975 peer_id = (u16)((pmdev->pdev->bus->number << 8) | PCI_SLOT(pmdev->pdev->devfn));
1976
1977 return (func_id == peer_id);
1978}
1979
5c40348c 1980static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG		 1981 struct mlx5e_tc_flow_parse_attr *parse_attr,
1982 struct mlx5e_tc_flow *flow)
e3a2b7ed 1983{
aa0cbbae 1984 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1985 const struct tc_action *a;
22dc13c8 1986 LIST_HEAD(actions);
1cab1cd7 1987 u32 action = 0;
2f4fe4ca 1988 int err;
e3a2b7ed 1989
3bcc0cec 1990 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 1991 return -EINVAL;
1992
3bc4b7bf 1993 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 1994
22dc13c8
WC		 1995 tcf_exts_to_list(exts, &actions);
1996 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1997 if (is_tcf_gact_shot(a)) {
1cab1cd7 1998 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 1999 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2000 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2001 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 2002 continue;
2003 }
2004
2f4fe4ca
OG		 2005 if (is_tcf_pedit(a)) {
2006 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
2007 parse_attr);
2008 if (err)
2009 return err;
2010
1cab1cd7
OG		 2011 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2012 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2f4fe4ca
OG		 2013 continue;
2014 }
2015
26c02749 2016 if (is_tcf_csum(a)) {
1cab1cd7 2017 if (csum_offload_supported(priv, action,
26c02749
OG		 2018 tcf_csum_update_flags(a)))
2019 continue;
2020
2021 return -EOPNOTSUPP;
2022 }
2023
5c65c564
OG		 2024 if (is_tcf_mirred_egress_redirect(a)) {
2025 struct net_device *peer_dev = tcf_mirred_dev(a);
2026
2027 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2028 same_hw_devs(priv, netdev_priv(peer_dev))) {
2029 parse_attr->mirred_ifindex = peer_dev->ifindex;
2030 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 2031 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2032 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564
OG		 2033 } else {
2034 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2035 peer_dev->name);
2036 return -EINVAL;
2037 }
2038 continue;
2039 }
2040
e3a2b7ed
AV		 2041 if (is_tcf_skbedit_mark(a)) {
2042 u32 mark = tcf_skbedit_mark(a);
2043
2044 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
2045 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
2046 mark);
2047 return -EINVAL;
2048 }
2049
3bc4b7bf 2050 attr->flow_tag = mark;
1cab1cd7 2051 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 2052 continue;
2053 }
2054
2055 return -EINVAL;
2056 }
2057
1cab1cd7 2058 attr->action = action;
bdd66ac0
OG		 2059 if (!actions_match_supported(priv, exts, parse_attr, flow))
2060 return -EOPNOTSUPP;
2061
e3a2b7ed
AV		 2062 return 0;
2063}
2064
76f7444d
OG		 2065static inline int cmp_encap_info(struct ip_tunnel_key *a,
2066 struct ip_tunnel_key *b)
a54e20b4
HHZ		 2067{
2068 return memcmp(a, b, sizeof(*a));
2069}
2070
76f7444d 2071static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2072{
76f7444d 2073 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2074}
2075
2076static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
2077 struct net_device *mirred_dev,
2078 struct net_device **out_dev,
2079 struct flowi4 *fl4,
2080 struct neighbour **out_n,
a54e20b4
HHZ		 2081 int *out_ttl)
2082{
3e621b19 2083 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5ed99fb4 2084 struct mlx5e_rep_priv *uplink_rpriv;
a54e20b4
HHZ		 2085 struct rtable *rt;
2086 struct neighbour *n = NULL;
a54e20b4
HHZ		 2087
2088#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 2089 int ret;
2090
a54e20b4 2091 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 2092 ret = PTR_ERR_OR_ZERO(rt);
2093 if (ret)
2094 return ret;
a54e20b4
HHZ		 2095#else
2096 return -EOPNOTSUPP;
2097#endif
a4b97ab4 2098 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3e621b19
HHZ		 2099 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2100 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
5ed99fb4 2101 *out_dev = uplink_rpriv->netdev;
3e621b19
HHZ		 2102 else
2103 *out_dev = rt->dst.dev;
a54e20b4 2104
75c33da8 2105 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 2106 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
2107 ip_rt_put(rt);
2108 if (!n)
2109 return -ENOMEM;
2110
2111 *out_n = n;
a54e20b4
HHZ		 2112 return 0;
2113}
2114
b1d90e6b
RL		 2115static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2116 struct net_device *peer_netdev)
2117{
2118 struct mlx5e_priv *peer_priv;
2119
2120 peer_priv = netdev_priv(peer_netdev);
2121
2122 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2123 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2124 same_hw_devs(priv, peer_priv) &&
2125 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2126 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2127}
2128
ce99f6b9
OG		 2129static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
2130 struct net_device *mirred_dev,
2131 struct net_device **out_dev,
2132 struct flowi6 *fl6,
2133 struct neighbour **out_n,
2134 int *out_ttl)
2135{
2136 struct neighbour *n = NULL;
2137 struct dst_entry *dst;
2138
2139#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
74bd5d56 2140 struct mlx5e_rep_priv *uplink_rpriv;
ce99f6b9
OG		 2141 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2142 int ret;
2143
08820528
PB		 2144 ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
2145 fl6);
2146 if (ret < 0)
ce99f6b9 2147 return ret;
ce99f6b9
OG		 2148
2149 *out_ttl = ip6_dst_hoplimit(dst);
2150
a4b97ab4 2151 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ce99f6b9
OG		 2152 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2153 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
5ed99fb4 2154 *out_dev = uplink_rpriv->netdev;
ce99f6b9
OG		 2155 else
2156 *out_dev = dst->dev;
2157#else
2158 return -EOPNOTSUPP;
2159#endif
2160
2161 n = dst_neigh_lookup(dst, &fl6->daddr);
2162 dst_release(dst);
2163 if (!n)
2164 return -ENOMEM;
2165
2166 *out_n = n;
2167 return 0;
2168}
2169
32f3671f
OG		 2170static void gen_vxlan_header_ipv4(struct net_device *out_dev,
2171 char buf[], int encap_size,
2172 unsigned char h_dest[ETH_ALEN],
2173 int ttl,
2174 __be32 daddr,
2175 __be32 saddr,
2176 __be16 udp_dst_port,
2177 __be32 vx_vni)
a54e20b4 2178{
a54e20b4
HHZ		 2179 struct ethhdr *eth = (struct ethhdr *)buf;
2180 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
2181 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
2182 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2183
2184 memset(buf, 0, encap_size);
2185
2186 ether_addr_copy(eth->h_dest, h_dest);
2187 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2188 eth->h_proto = htons(ETH_P_IP);
2189
2190 ip->daddr = daddr;
2191 ip->saddr = saddr;
2192
2193 ip->ttl = ttl;
2194 ip->protocol = IPPROTO_UDP;
2195 ip->version = 0x4;
2196 ip->ihl = 0x5;
2197
2198 udp->dest = udp_dst_port;
2199 vxh->vx_flags = VXLAN_HF_VNI;
2200 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 2201}
2202
225aabaf
OG		 2203static void gen_vxlan_header_ipv6(struct net_device *out_dev,
2204 char buf[], int encap_size,
2205 unsigned char h_dest[ETH_ALEN],
2206 int ttl,
2207 struct in6_addr *daddr,
2208 struct in6_addr *saddr,
2209 __be16 udp_dst_port,
2210 __be32 vx_vni)
ce99f6b9 2211{
ce99f6b9
OG		 2212 struct ethhdr *eth = (struct ethhdr *)buf;
2213 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
2214 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
2215 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2216
2217 memset(buf, 0, encap_size);
2218
2219 ether_addr_copy(eth->h_dest, h_dest);
2220 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2221 eth->h_proto = htons(ETH_P_IPV6);
2222
2223 ip6_flow_hdr(ip6h, 0, 0);
2224 /* the HW fills up ipv6 payload len */
2225 ip6h->nexthdr = IPPROTO_UDP;
2226 ip6h->hop_limit = ttl;
2227 ip6h->daddr = *daddr;
2228 ip6h->saddr = *saddr;
2229
2230 udp->dest = udp_dst_port;
2231 vxh->vx_flags = VXLAN_HF_VNI;
2232 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 2233}
2234
a54e20b4
HHZ		 2235static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
2236 struct net_device *mirred_dev,
1a8552bd 2237 struct mlx5e_encap_entry *e)
a54e20b4
HHZ		 2238{
2239 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 2240 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 2241 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2242 struct net_device *out_dev;
a42485eb 2243 struct neighbour *n = NULL;
a54e20b4 2244 struct flowi4 fl4 = {};
a54e20b4 2245 char *encap_header;
32f3671f 2246 int ttl, err;
033354d5 2247 u8 nud_state;
32f3671f
OG		 2248
2249 if (max_encap_size < ipv4_encap_size) {
2250 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2251 ipv4_encap_size, max_encap_size);
2252 return -EOPNOTSUPP;
2253 }
a54e20b4 2254
32f3671f 2255 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 2256 if (!encap_header)
2257 return -ENOMEM;
2258
2259 switch (e->tunnel_type) {
2260 case MLX5_HEADER_TYPE_VXLAN:
2261 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 2262 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 2263 break;
2264 default:
2265 err = -EOPNOTSUPP;
ace74321 2266 goto free_encap;
a54e20b4 2267 }
9a941117 2268 fl4.flowi4_tos = tun_key->tos;
76f7444d 2269 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 2270 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 2271
1a8552bd 2272 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 2273 &fl4, &n, &ttl);
a54e20b4 2274 if (err)
ace74321 2275 goto free_encap;
a54e20b4 2276
232c0013
HHZ		 2277 /* used by mlx5e_detach_encap to lookup a neigh hash table
2278 * entry in the neigh hash table when a user deletes a rule
2279 */
2280 e->m_neigh.dev = n->dev;
f6dfb4c3 2281 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2282 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2283 e->out_dev = out_dev;
2284
2285 /* It's importent to add the neigh to the hash table before checking
2286 * the neigh validity state. So if we'll get a notification, in case the
2287 * neigh changes it's validity state, we would find the relevant neigh
2288 * in the hash.
2289 */
2290 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2291 if (err)
ace74321 2292 goto free_encap;
232c0013 2293
033354d5
HHZ		 2294 read_lock_bh(&n->lock);
2295 nud_state = n->nud_state;
2296 ether_addr_copy(e->h_dest, n->ha);
2297 read_unlock_bh(&n->lock);
2298
a54e20b4
HHZ		 2299 switch (e->tunnel_type) {
2300 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 2301 gen_vxlan_header_ipv4(out_dev, encap_header,
32f3671f
OG		 2302 ipv4_encap_size, e->h_dest, ttl,
2303 fl4.daddr,
2304 fl4.saddr, tun_key->tp_dst,
2305 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 2306 break;
2307 default:
2308 err = -EOPNOTSUPP;
232c0013
HHZ		 2309 goto destroy_neigh_entry;
2310 }
2311 e->encap_size = ipv4_encap_size;
2312 e->encap_header = encap_header;
2313
2314 if (!(nud_state & NUD_VALID)) {
2315 neigh_event_send(n, NULL);
27902f08
WY		 2316 err = -EAGAIN;
2317 goto out;
a54e20b4
HHZ		 2318 }
2319
2320 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 2321 ipv4_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 2322 if (err)
2323 goto destroy_neigh_entry;
2324
2325 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2326 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2327 neigh_release(n);
2328 return err;
2329
2330destroy_neigh_entry:
2331 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2332free_encap:
a54e20b4 2333 kfree(encap_header);
ace74321 2334out:
232c0013
HHZ		 2335 if (n)
2336 neigh_release(n);
a54e20b4
HHZ		 2337 return err;
2338}
2339
ce99f6b9
OG		 2340static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2341 struct net_device *mirred_dev,
1a8552bd 2342 struct mlx5e_encap_entry *e)
ce99f6b9
OG		 2343{
2344 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 2345 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 2346 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2347 struct net_device *out_dev;
ce99f6b9
OG		 2348 struct neighbour *n = NULL;
2349 struct flowi6 fl6 = {};
2350 char *encap_header;
225aabaf 2351 int err, ttl = 0;
033354d5 2352 u8 nud_state;
ce99f6b9 2353
225aabaf
OG		 2354 if (max_encap_size < ipv6_encap_size) {
2355 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2356 ipv6_encap_size, max_encap_size);
2357 return -EOPNOTSUPP;
2358 }
ce99f6b9 2359
225aabaf 2360 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 2361 if (!encap_header)
2362 return -ENOMEM;
2363
2364 switch (e->tunnel_type) {
2365 case MLX5_HEADER_TYPE_VXLAN:
2366 fl6.flowi6_proto = IPPROTO_UDP;
2367 fl6.fl6_dport = tun_key->tp_dst;
2368 break;
2369 default:
2370 err = -EOPNOTSUPP;
ace74321 2371 goto free_encap;
ce99f6b9
OG		 2372 }
2373
2374 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2375 fl6.daddr = tun_key->u.ipv6.dst;
2376 fl6.saddr = tun_key->u.ipv6.src;
2377
1a8552bd 2378 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG		 2379 &fl6, &n, &ttl);
2380 if (err)
ace74321 2381 goto free_encap;
ce99f6b9 2382
232c0013
HHZ		 2383 /* used by mlx5e_detach_encap to lookup a neigh hash table
2384 * entry in the neigh hash table when a user deletes a rule
2385 */
2386 e->m_neigh.dev = n->dev;
f6dfb4c3 2387 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2388 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2389 e->out_dev = out_dev;
2390
2391 /* It's importent to add the neigh to the hash table before checking
2392 * the neigh validity state. So if we'll get a notification, in case the
2393 * neigh changes it's validity state, we would find the relevant neigh
2394 * in the hash.
2395 */
2396 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2397 if (err)
ace74321 2398 goto free_encap;
232c0013 2399
033354d5
HHZ		 2400 read_lock_bh(&n->lock);
2401 nud_state = n->nud_state;
2402 ether_addr_copy(e->h_dest, n->ha);
2403 read_unlock_bh(&n->lock);
2404
ce99f6b9
OG		 2405 switch (e->tunnel_type) {
2406 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 2407 gen_vxlan_header_ipv6(out_dev, encap_header,
225aabaf
OG		 2408 ipv6_encap_size, e->h_dest, ttl,
2409 &fl6.daddr,
2410 &fl6.saddr, tun_key->tp_dst,
2411 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 2412 break;
2413 default:
2414 err = -EOPNOTSUPP;
232c0013
HHZ		 2415 goto destroy_neigh_entry;
2416 }
2417
2418 e->encap_size = ipv6_encap_size;
2419 e->encap_header = encap_header;
2420
2421 if (!(nud_state & NUD_VALID)) {
2422 neigh_event_send(n, NULL);
27902f08
WY		 2423 err = -EAGAIN;
2424 goto out;
ce99f6b9
OG		 2425 }
2426
2427 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 2428 ipv6_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 2429 if (err)
2430 goto destroy_neigh_entry;
2431
2432 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2433 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2434 neigh_release(n);
2435 return err;
2436
2437destroy_neigh_entry:
2438 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2439free_encap:
ce99f6b9 2440 kfree(encap_header);
ace74321 2441out:
232c0013
HHZ		 2442 if (n)
2443 neigh_release(n);
ce99f6b9
OG		 2444 return err;
2445}
2446
a54e20b4
HHZ		 2447static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2448 struct ip_tunnel_info *tun_info,
2449 struct net_device *mirred_dev,
45247bf2
OG		 2450 struct net_device **encap_dev,
2451 struct mlx5e_tc_flow *flow)
a54e20b4
HHZ		 2452{
2453 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a4b97ab4
MB		 2454 struct mlx5e_rep_priv *uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw,
2455 REP_ETH);
5ed99fb4 2456 struct net_device *up_dev = uplink_rpriv->netdev;
a54e20b4 2457 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2
OG		 2458 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
2459 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2460 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2461 struct mlx5e_encap_entry *e;
45247bf2 2462 int tunnel_type, err = 0;
a54e20b4
HHZ		 2463 uintptr_t hash_key;
2464 bool found = false;
a54e20b4 2465
2fcd82e9 2466 /* udp dst port must be set */
a54e20b4 2467 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 2468 goto vxlan_encap_offload_err;
a54e20b4 2469
cd377663 2470 /* setting udp src port isn't supported */
2fcd82e9
OG		 2471 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2472vxlan_encap_offload_err:
2473 netdev_warn(priv->netdev,
2474 "must set udp dst port and not set udp src port\n");
cd377663 2475 return -EOPNOTSUPP;
2fcd82e9 2476 }
cd377663 2477
1ad9a00a 2478 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 2479 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ		 2480 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
2481 } else {
2fcd82e9
OG		 2482 netdev_warn(priv->netdev,
2483 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 2484 return -EOPNOTSUPP;
2485 }
2486
76f7444d 2487 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2488
2489 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2490 encap_hlist, hash_key) {
76f7444d 2491 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2492 found = true;
2493 break;
2494 }
2495 }
2496
b2812089 2497 /* must verify if encap is valid or not */
45247bf2
OG		 2498 if (found)
2499 goto attach_flow;
a54e20b4
HHZ		 2500
2501 e = kzalloc(sizeof(*e), GFP_KERNEL);
2502 if (!e)
2503 return -ENOMEM;
2504
76f7444d 2505 e->tun_info = *tun_info;
a54e20b4
HHZ		 2506 e->tunnel_type = tunnel_type;
2507 INIT_LIST_HEAD(&e->flows);
2508
ce99f6b9 2509 if (family == AF_INET)
1a8552bd 2510 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2511 else if (family == AF_INET6)
1a8552bd 2512 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2513
232c0013 2514 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2515 goto out_err;
2516
a54e20b4
HHZ		 2517 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2518
45247bf2
OG		 2519attach_flow:
2520 list_add(&flow->encap, &e->flows);
2521 *encap_dev = e->out_dev;
232c0013
HHZ		 2522 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2523 attr->encap_id = e->encap_id;
b2812089
VB		 2524 else
2525 err = -EAGAIN;
45247bf2 2526
232c0013 2527 return err;
a54e20b4
HHZ		 2528
2529out_err:
2530 kfree(e);
2531 return err;
2532}
2533
03a9d11e 2534static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 2535 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 2536 struct mlx5e_tc_flow *flow)
03a9d11e 2537{
ecf5bb79 2538 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2539 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 2540 struct ip_tunnel_info *info = NULL;
03a9d11e 2541 const struct tc_action *a;
22dc13c8 2542 LIST_HEAD(actions);
a54e20b4 2543 bool encap = false;
1cab1cd7 2544 u32 action = 0;
03a9d11e 2545
3bcc0cec 2546 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 2547 return -EINVAL;
2548
1d447a39 2549 attr->in_rep = rpriv->rep;
10ff5359 2550 attr->in_mdev = priv->mdev;
03a9d11e 2551
22dc13c8
WC		 2552 tcf_exts_to_list(exts, &actions);
2553 list_for_each_entry(a, &actions, list) {
03a9d11e 2554 if (is_tcf_gact_shot(a)) {
1cab1cd7
OG		 2555 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2556 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 2557 continue;
2558 }
2559
d7e75a32 2560 if (is_tcf_pedit(a)) {
31c8eba5
OG		 2561 int err;
2562
d7e75a32
OG		 2563 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
2564 parse_attr);
2565 if (err)
2566 return err;
2567
1cab1cd7 2568 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
592d3651 2569 attr->mirror_count = attr->out_count;
d7e75a32
OG		 2570 continue;
2571 }
2572
26c02749 2573 if (is_tcf_csum(a)) {
1cab1cd7 2574 if (csum_offload_supported(priv, action,
26c02749
OG		 2575 tcf_csum_update_flags(a)))
2576 continue;
2577
2578 return -EOPNOTSUPP;
2579 }
2580
592d3651 2581 if (is_tcf_mirred_egress_redirect(a) || is_tcf_mirred_egress_mirror(a)) {
03a9d11e 2582 struct mlx5e_priv *out_priv;
592d3651 2583 struct net_device *out_dev;
03a9d11e 2584
9f8a739e 2585 out_dev = tcf_mirred_dev(a);
03a9d11e 2586
592d3651
CM		 2587 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
2588 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2589 attr->out_count);
2590 return -EOPNOTSUPP;
2591 }
2592
a54e20b4 2593 if (switchdev_port_same_parent_id(priv->netdev,
b1d90e6b
RL		 2594 out_dev) ||
2595 is_merged_eswitch_dev(priv, out_dev)) {
1cab1cd7
OG		 2596 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2597 MLX5_FLOW_CONTEXT_ACTION_COUNT;
a54e20b4 2598 out_priv = netdev_priv(out_dev);
1d447a39 2599 rpriv = out_priv->ppriv;
592d3651
CM		 2600 attr->out_rep[attr->out_count] = rpriv->rep;
2601 attr->out_mdev[attr->out_count++] = out_priv->mdev;
a54e20b4 2602 } else if (encap) {
9f8a739e 2603 parse_attr->mirred_ifindex = out_dev->ifindex;
3c37745e
OG		 2604 parse_attr->tun_info = *info;
2605 attr->parse_attr = parse_attr;
1cab1cd7
OG		 2606 action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
2607 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2608 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3c37745e 2609 /* attr->out_rep is resolved when we handle encap */
a54e20b4 2610 } else {
03a9d11e
OG		 2611 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2612 priv->netdev->name, out_dev->name);
2613 return -EINVAL;
2614 }
a54e20b4
HHZ		 2615 continue;
2616 }
03a9d11e 2617
a54e20b4
HHZ		 2618 if (is_tcf_tunnel_set(a)) {
2619 info = tcf_tunnel_info(a);
2620 if (info)
2621 encap = true;
2622 else
2623 return -EOPNOTSUPP;
592d3651 2624 attr->mirror_count = attr->out_count;
03a9d11e
OG		 2625 continue;
2626 }
2627
8b32580d 2628 if (is_tcf_vlan(a)) {
09c91ddf 2629 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
1cab1cd7 2630 action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 2631 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
1cab1cd7 2632 action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
6acfbf38
OG		 2633 attr->vlan_vid = tcf_vlan_push_vid(a);
2634 if (mlx5_eswitch_vlan_actions_supported(priv->mdev)) {
2635 attr->vlan_prio = tcf_vlan_push_prio(a);
2636 attr->vlan_proto = tcf_vlan_push_proto(a);
2637 if (!attr->vlan_proto)
2638 attr->vlan_proto = htons(ETH_P_8021Q);
2639 } else if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2640 tcf_vlan_push_prio(a)) {
2641 return -EOPNOTSUPP;
2642 }
09c91ddf
OG		 2643 } else { /* action is TCA_VLAN_ACT_MODIFY */
2644 return -EOPNOTSUPP;
8b32580d 2645 }
592d3651 2646 attr->mirror_count = attr->out_count;
8b32580d
OG		 2647 continue;
2648 }
2649
bbd00f7e 2650 if (is_tcf_tunnel_release(a)) {
1cab1cd7 2651 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bbd00f7e
HHZ		 2652 continue;
2653 }
2654
03a9d11e
OG		 2655 return -EINVAL;
2656 }
bdd66ac0 2657
1cab1cd7 2658 attr->action = action;
bdd66ac0
OG		 2659 if (!actions_match_supported(priv, exts, parse_attr, flow))
2660 return -EOPNOTSUPP;
2661
592d3651
CM		 2662 if (attr->out_count > 1 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
2663 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2664 return -EOPNOTSUPP;
2665 }
2666
31c8eba5 2667 return 0;
03a9d11e
OG		 2668}
2669
60bd4af8
OG		 2670static void get_flags(int flags, u8 *flow_flags)
2671{
2672 u8 __flow_flags = 0;
2673
2674 if (flags & MLX5E_TC_INGRESS)
2675 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
2676 if (flags & MLX5E_TC_EGRESS)
2677 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
2678
2679 *flow_flags = __flow_flags;
2680}
2681
05866c82
OG		 2682static const struct rhashtable_params tc_ht_params = {
2683 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2684 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2685 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2686 .automatic_shrinking = true,
2687};
2688
2689static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv)
2690{
655dc3d2
OG		 2691 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2692 struct mlx5e_rep_priv *uplink_rpriv;
2693
2694 if (MLX5_VPORT_MANAGER(priv->mdev) && esw->mode == SRIOV_OFFLOADS) {
2695 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2696 return &uplink_rpriv->tc_ht;
2697 } else
2698 return &priv->fs.tc.ht;
05866c82
OG		 2699}
2700
5fd9fc4e 2701int mlx5e_configure_flower(struct mlx5e_priv *priv,
60bd4af8 2702 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 2703{
3bc4b7bf 2704 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 2705 struct mlx5e_tc_flow_parse_attr *parse_attr;
05866c82 2706 struct rhashtable *tc_ht = get_tc_ht(priv);
3bc4b7bf
OG		 2707 struct mlx5e_tc_flow *flow;
2708 int attr_size, err = 0;
65ba8fb7 2709 u8 flow_flags = 0;
e3a2b7ed 2710
60bd4af8
OG		 2711 get_flags(flags, &flow_flags);
2712
8f8ae895
OG		 2713 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
2714 if (flow) {
2715 netdev_warn_once(priv->netdev, "flow cookie %lx already exists, ignoring\n", f->cookie);
2716 return 0;
2717 }
2718
65ba8fb7 2719 if (esw && esw->mode == SRIOV_OFFLOADS) {
60bd4af8 2720 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
65ba8fb7 2721 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf 2722 } else {
60bd4af8 2723 flow_flags |= MLX5E_TC_FLOW_NIC;
3bc4b7bf 2724 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 2725 }
e3a2b7ed 2726
65ba8fb7 2727 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 2728 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 2729 if (!parse_attr || !flow) {
e3a2b7ed
AV		 2730 err = -ENOMEM;
2731 goto err_free;
2732 }
2733
2734 flow->cookie = f->cookie;
65ba8fb7 2735 flow->flags = flow_flags;
655dc3d2 2736 flow->priv = priv;
e3a2b7ed 2737
17091853 2738 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV		 2739 if (err < 0)
2740 goto err_free;
2741
65ba8fb7 2742 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 2743 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123 2744 if (err < 0)
3c37745e 2745 goto err_free;
e4ad91f2 2746 flow->rule[0] = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 2747 } else {
aa0cbbae 2748 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG		 2749 if (err < 0)
2750 goto err_free;
e4ad91f2 2751 flow->rule[0] = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 2752 }
e3a2b7ed 2753
e4ad91f2
CM		 2754 if (IS_ERR(flow->rule[0])) {
2755 err = PTR_ERR(flow->rule[0]);
3c37745e
OG		 2756 if (err != -EAGAIN)
2757 goto err_free;
e3a2b7ed
AV		 2758 }
2759
3c37745e
OG		 2760 if (err != -EAGAIN)
2761 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
2762
af1607c3
JL		 2763 if (!(flow->flags & MLX5E_TC_FLOW_ESWITCH) ||
2764 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
2765 kvfree(parse_attr);
2766
05866c82 2767 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
af1607c3
JL		 2768 if (err) {
2769 mlx5e_tc_del_flow(priv, flow);
2770 kfree(flow);
2771 }
5c40348c 2772
232c0013 2773 return err;
e3a2b7ed 2774
e3a2b7ed 2775err_free:
17091853 2776 kvfree(parse_attr);
232c0013 2777 kfree(flow);
e3a2b7ed
AV		 2778 return err;
2779}
2780
8f8ae895
OG		 2781#define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
2782#define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
2783
2784static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
2785{
2786 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
2787 return true;
2788
2789 return false;
2790}
2791
e3a2b7ed 2792int mlx5e_delete_flower(struct mlx5e_priv *priv,
60bd4af8 2793 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 2794{
05866c82 2795 struct rhashtable *tc_ht = get_tc_ht(priv);
e3a2b7ed 2796 struct mlx5e_tc_flow *flow;
e3a2b7ed 2797
05866c82 2798 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 2799 if (!flow || !same_flow_direction(flow, flags))
e3a2b7ed
AV		 2800 return -EINVAL;
2801
05866c82 2802 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
e3a2b7ed 2803
961e8979 2804 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 2805
2806 kfree(flow);
2807
2808 return 0;
2809}
2810
aad7e08d 2811int mlx5e_stats_flower(struct mlx5e_priv *priv,
60bd4af8 2812 struct tc_cls_flower_offload *f, int flags)
aad7e08d 2813{
05866c82 2814 struct rhashtable *tc_ht = get_tc_ht(priv);
aad7e08d 2815 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 2816 struct mlx5_fc *counter;
2817 u64 bytes;
2818 u64 packets;
2819 u64 lastuse;
2820
05866c82 2821 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 2822 if (!flow || !same_flow_direction(flow, flags))
aad7e08d
AV		 2823 return -EINVAL;
2824
0b67a38f
HHZ		 2825 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2826 return 0;
2827
e4ad91f2 2828 counter = mlx5_flow_rule_counter(flow->rule[0]);
aad7e08d
AV		 2829 if (!counter)
2830 return 0;
2831
2832 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2833
d897a638 2834 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 2835
aad7e08d
AV		 2836 return 0;
2837}
2838
655dc3d2 2839int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 2840{
acff797c 2841 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 2842
11c9c548 2843 hash_init(tc->mod_hdr_tbl);
5c65c564 2844 hash_init(tc->hairpin_tbl);
11c9c548 2845
05866c82 2846 return rhashtable_init(&tc->ht, &tc_ht_params);
e8f887ac
AV		 2847}
2848
2849static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2850{
2851 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 2852 struct mlx5e_priv *priv = flow->priv;
e8f887ac 2853
961e8979 2854 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 2855 kfree(flow);
2856}
2857
655dc3d2 2858void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 2859{
acff797c 2860 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 2861
655dc3d2 2862 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 2863
acff797c
MG		 2864 if (!IS_ERR_OR_NULL(tc->t)) {
2865 mlx5_destroy_flow_table(tc->t);
2866 tc->t = NULL;
e8f887ac
AV		 2867 }
2868}
655dc3d2
OG		 2869
2870int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
2871{
2872 return rhashtable_init(tc_ht, &tc_ht_params);
2873}
2874
2875void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
2876{
2877 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
2878}
Linux 6.x block layer and io_uring tree(s)