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net/mlx5e: Avoid overriding the user provided priority for offloaded tc rules
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
358aa5ce 53#include "lib/vxlan.h"
3f6d08d1 54#include "fs_core.h"
2c81bfd5 55#include "en/port.h"
e8f887ac 56
3bc4b7bf
OG		 57struct mlx5_nic_flow_attr {
58 u32 action;
59 u32 flow_tag;
2f4fe4ca 60 u32 mod_hdr_id;
5c65c564 61 u32 hairpin_tirn;
38aa51c1 62 u8 match_level;
3f6d08d1 63 struct mlx5_flow_table *hairpin_ft;
b8aee822 64 struct mlx5_fc *counter;
3bc4b7bf
OG		 65};
66
60bd4af8
OG		 67#define MLX5E_TC_FLOW_BASE (MLX5E_TC_LAST_EXPORTED_BIT + 1)
68
65ba8fb7 69enum {
60bd4af8
OG		 70 MLX5E_TC_FLOW_INGRESS = MLX5E_TC_INGRESS,
71 MLX5E_TC_FLOW_EGRESS = MLX5E_TC_EGRESS,
72 MLX5E_TC_FLOW_ESWITCH = BIT(MLX5E_TC_FLOW_BASE),
73 MLX5E_TC_FLOW_NIC = BIT(MLX5E_TC_FLOW_BASE + 1),
74 MLX5E_TC_FLOW_OFFLOADED = BIT(MLX5E_TC_FLOW_BASE + 2),
75 MLX5E_TC_FLOW_HAIRPIN = BIT(MLX5E_TC_FLOW_BASE + 3),
76 MLX5E_TC_FLOW_HAIRPIN_RSS = BIT(MLX5E_TC_FLOW_BASE + 4),
5dbe906f 77 MLX5E_TC_FLOW_SLOW = BIT(MLX5E_TC_FLOW_BASE + 5),
65ba8fb7
OG		 78};
79
e4ad91f2
CM		 80#define MLX5E_TC_MAX_SPLITS 1
81
e8f887ac
AV		 82struct mlx5e_tc_flow {
83 struct rhash_head node;
655dc3d2 84 struct mlx5e_priv *priv;
e8f887ac 85 u64 cookie;
5dbe906f 86 u16 flags;
e4ad91f2 87 struct mlx5_flow_handle *rule[MLX5E_TC_MAX_SPLITS + 1];
11c9c548
OG		 88 struct list_head encap; /* flows sharing the same encap ID */
89 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
5c65c564 90 struct list_head hairpin; /* flows sharing the same hairpin */
3bc4b7bf
OG		 91 union {
92 struct mlx5_esw_flow_attr esw_attr[0];
93 struct mlx5_nic_flow_attr nic_attr[0];
94 };
e8f887ac
AV		 95};
96
17091853 97struct mlx5e_tc_flow_parse_attr {
3c37745e 98 struct ip_tunnel_info tun_info;
17091853 99 struct mlx5_flow_spec spec;
d79b6df6
OG		 100 int num_mod_hdr_actions;
101 void *mod_hdr_actions;
3c37745e 102 int mirred_ifindex;
17091853
OG		 103};
104
acff797c 105#define MLX5E_TC_TABLE_NUM_GROUPS 4
b3a433de 106#define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(16)
e8f887ac 107
77ab67b7
OG		 108struct mlx5e_hairpin {
109 struct mlx5_hairpin *pair;
110
111 struct mlx5_core_dev *func_mdev;
3f6d08d1 112 struct mlx5e_priv *func_priv;
77ab67b7
OG		 113 u32 tdn;
114 u32 tirn;
3f6d08d1
OG		 115
116 int num_channels;
117 struct mlx5e_rqt indir_rqt;
118 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
119 struct mlx5e_ttc_table ttc;
77ab67b7
OG		 120};
121
5c65c564
OG		 122struct mlx5e_hairpin_entry {
123 /* a node of a hash table which keeps all the hairpin entries */
124 struct hlist_node hairpin_hlist;
125
126 /* flows sharing the same hairpin */
127 struct list_head flows;
128
d8822868 129 u16 peer_vhca_id;
106be53b 130 u8 prio;
5c65c564
OG		 131 struct mlx5e_hairpin *hp;
132};
133
11c9c548
OG		 134struct mod_hdr_key {
135 int num_actions;
136 void *actions;
137};
138
139struct mlx5e_mod_hdr_entry {
140 /* a node of a hash table which keeps all the mod_hdr entries */
141 struct hlist_node mod_hdr_hlist;
142
143 /* flows sharing the same mod_hdr entry */
144 struct list_head flows;
145
146 struct mod_hdr_key key;
147
148 u32 mod_hdr_id;
149};
150
151#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
152
153static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
154{
155 return jhash(key->actions,
156 key->num_actions * MLX5_MH_ACT_SZ, 0);
157}
158
159static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
160 struct mod_hdr_key *b)
161{
162 if (a->num_actions != b->num_actions)
163 return 1;
164
165 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
166}
167
168static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
169 struct mlx5e_tc_flow *flow,
170 struct mlx5e_tc_flow_parse_attr *parse_attr)
171{
172 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
173 int num_actions, actions_size, namespace, err;
174 struct mlx5e_mod_hdr_entry *mh;
175 struct mod_hdr_key key;
176 bool found = false;
177 u32 hash_key;
178
179 num_actions = parse_attr->num_mod_hdr_actions;
180 actions_size = MLX5_MH_ACT_SZ * num_actions;
181
182 key.actions = parse_attr->mod_hdr_actions;
183 key.num_actions = num_actions;
184
185 hash_key = hash_mod_hdr_info(&key);
186
187 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
188 namespace = MLX5_FLOW_NAMESPACE_FDB;
189 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
190 mod_hdr_hlist, hash_key) {
191 if (!cmp_mod_hdr_info(&mh->key, &key)) {
192 found = true;
193 break;
194 }
195 }
196 } else {
197 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
198 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
199 mod_hdr_hlist, hash_key) {
200 if (!cmp_mod_hdr_info(&mh->key, &key)) {
201 found = true;
202 break;
203 }
204 }
205 }
206
207 if (found)
208 goto attach_flow;
209
210 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
211 if (!mh)
212 return -ENOMEM;
213
214 mh->key.actions = (void *)mh + sizeof(*mh);
215 memcpy(mh->key.actions, key.actions, actions_size);
216 mh->key.num_actions = num_actions;
217 INIT_LIST_HEAD(&mh->flows);
218
219 err = mlx5_modify_header_alloc(priv->mdev, namespace,
220 mh->key.num_actions,
221 mh->key.actions,
222 &mh->mod_hdr_id);
223 if (err)
224 goto out_err;
225
226 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
227 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
228 else
229 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
230
231attach_flow:
232 list_add(&flow->mod_hdr, &mh->flows);
233 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
234 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
235 else
236 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
237
238 return 0;
239
240out_err:
241 kfree(mh);
242 return err;
243}
244
245static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
246 struct mlx5e_tc_flow *flow)
247{
248 struct list_head *next = flow->mod_hdr.next;
249
250 list_del(&flow->mod_hdr);
251
252 if (list_empty(next)) {
253 struct mlx5e_mod_hdr_entry *mh;
254
255 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
256
257 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
258 hash_del(&mh->mod_hdr_hlist);
259 kfree(mh);
260 }
261}
262
77ab67b7
OG		 263static
264struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
265{
266 struct net_device *netdev;
267 struct mlx5e_priv *priv;
268
269 netdev = __dev_get_by_index(net, ifindex);
270 priv = netdev_priv(netdev);
271 return priv->mdev;
272}
273
274static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
275{
276 u32 in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
277 void *tirc;
278 int err;
279
280 err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
281 if (err)
282 goto alloc_tdn_err;
283
284 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
285
286 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
ddae74ac 287 MLX5_SET(tirc, tirc, inline_rqn, hp->pair->rqn[0]);
77ab67b7
OG		 288 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
289
290 err = mlx5_core_create_tir(hp->func_mdev, in, MLX5_ST_SZ_BYTES(create_tir_in), &hp->tirn);
291 if (err)
292 goto create_tir_err;
293
294 return 0;
295
296create_tir_err:
297 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
298alloc_tdn_err:
299 return err;
300}
301
302static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
303{
304 mlx5_core_destroy_tir(hp->func_mdev, hp->tirn);
305 mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
306}
307
3f6d08d1
OG		 308static void mlx5e_hairpin_fill_rqt_rqns(struct mlx5e_hairpin *hp, void *rqtc)
309{
310 u32 indirection_rqt[MLX5E_INDIR_RQT_SIZE], rqn;
311 struct mlx5e_priv *priv = hp->func_priv;
312 int i, ix, sz = MLX5E_INDIR_RQT_SIZE;
313
314 mlx5e_build_default_indir_rqt(indirection_rqt, sz,
315 hp->num_channels);
316
317 for (i = 0; i < sz; i++) {
318 ix = i;
319 if (priv->channels.params.rss_hfunc == ETH_RSS_HASH_XOR)
320 ix = mlx5e_bits_invert(i, ilog2(sz));
321 ix = indirection_rqt[ix];
322 rqn = hp->pair->rqn[ix];
323 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
324 }
325}
326
327static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
328{
329 int inlen, err, sz = MLX5E_INDIR_RQT_SIZE;
330 struct mlx5e_priv *priv = hp->func_priv;
331 struct mlx5_core_dev *mdev = priv->mdev;
332 void *rqtc;
333 u32 *in;
334
335 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
336 in = kvzalloc(inlen, GFP_KERNEL);
337 if (!in)
338 return -ENOMEM;
339
340 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
341
342 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
343 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
344
345 mlx5e_hairpin_fill_rqt_rqns(hp, rqtc);
346
347 err = mlx5_core_create_rqt(mdev, in, inlen, &hp->indir_rqt.rqtn);
348 if (!err)
349 hp->indir_rqt.enabled = true;
350
351 kvfree(in);
352 return err;
353}
354
355static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
356{
357 struct mlx5e_priv *priv = hp->func_priv;
358 u32 in[MLX5_ST_SZ_DW(create_tir_in)];
359 int tt, i, err;
360 void *tirc;
361
362 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
363 memset(in, 0, MLX5_ST_SZ_BYTES(create_tir_in));
364 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
365
366 MLX5_SET(tirc, tirc, transport_domain, hp->tdn);
367 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
368 MLX5_SET(tirc, tirc, indirect_table, hp->indir_rqt.rqtn);
369 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
370
371 err = mlx5_core_create_tir(hp->func_mdev, in,
372 MLX5_ST_SZ_BYTES(create_tir_in), &hp->indir_tirn[tt]);
373 if (err) {
374 mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
375 goto err_destroy_tirs;
376 }
377 }
378 return 0;
379
380err_destroy_tirs:
381 for (i = 0; i < tt; i++)
382 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[i]);
383 return err;
384}
385
386static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
387{
388 int tt;
389
390 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
391 mlx5_core_destroy_tir(hp->func_mdev, hp->indir_tirn[tt]);
392}
393
394static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
395 struct ttc_params *ttc_params)
396{
397 struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
398 int tt;
399
400 memset(ttc_params, 0, sizeof(*ttc_params));
401
402 ttc_params->any_tt_tirn = hp->tirn;
403
404 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
405 ttc_params->indir_tirn[tt] = hp->indir_tirn[tt];
406
407 ft_attr->max_fte = MLX5E_NUM_TT;
408 ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
409 ft_attr->prio = MLX5E_TC_PRIO;
410}
411
412static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
413{
414 struct mlx5e_priv *priv = hp->func_priv;
415 struct ttc_params ttc_params;
416 int err;
417
418 err = mlx5e_hairpin_create_indirect_rqt(hp);
419 if (err)
420 return err;
421
422 err = mlx5e_hairpin_create_indirect_tirs(hp);
423 if (err)
424 goto err_create_indirect_tirs;
425
426 mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
427 err = mlx5e_create_ttc_table(priv, &ttc_params, &hp->ttc);
428 if (err)
429 goto err_create_ttc_table;
430
431 netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
432 hp->num_channels, hp->ttc.ft.t->id);
433
434 return 0;
435
436err_create_ttc_table:
437 mlx5e_hairpin_destroy_indirect_tirs(hp);
438err_create_indirect_tirs:
439 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
440
441 return err;
442}
443
444static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
445{
446 struct mlx5e_priv *priv = hp->func_priv;
447
448 mlx5e_destroy_ttc_table(priv, &hp->ttc);
449 mlx5e_hairpin_destroy_indirect_tirs(hp);
450 mlx5e_destroy_rqt(priv, &hp->indir_rqt);
451}
452
77ab67b7
OG		 453static struct mlx5e_hairpin *
454mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
455 int peer_ifindex)
456{
457 struct mlx5_core_dev *func_mdev, *peer_mdev;
458 struct mlx5e_hairpin *hp;
459 struct mlx5_hairpin *pair;
460 int err;
461
462 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
463 if (!hp)
464 return ERR_PTR(-ENOMEM);
465
466 func_mdev = priv->mdev;
467 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
468
469 pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
470 if (IS_ERR(pair)) {
471 err = PTR_ERR(pair);
472 goto create_pair_err;
473 }
474 hp->pair = pair;
475 hp->func_mdev = func_mdev;
3f6d08d1
OG		 476 hp->func_priv = priv;
477 hp->num_channels = params->num_channels;
77ab67b7
OG		 478
479 err = mlx5e_hairpin_create_transport(hp);
480 if (err)
481 goto create_transport_err;
482
3f6d08d1
OG		 483 if (hp->num_channels > 1) {
484 err = mlx5e_hairpin_rss_init(hp);
485 if (err)
486 goto rss_init_err;
487 }
488
77ab67b7
OG		 489 return hp;
490
3f6d08d1
OG		 491rss_init_err:
492 mlx5e_hairpin_destroy_transport(hp);
77ab67b7
OG		 493create_transport_err:
494 mlx5_core_hairpin_destroy(hp->pair);
495create_pair_err:
496 kfree(hp);
497 return ERR_PTR(err);
498}
499
500static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
501{
3f6d08d1
OG		 502 if (hp->num_channels > 1)
503 mlx5e_hairpin_rss_cleanup(hp);
77ab67b7
OG		 504 mlx5e_hairpin_destroy_transport(hp);
505 mlx5_core_hairpin_destroy(hp->pair);
506 kvfree(hp);
507}
508
106be53b
OG		 509static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
510{
511 return (peer_vhca_id << 16 | prio);
512}
513
5c65c564 514static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
106be53b 515 u16 peer_vhca_id, u8 prio)
5c65c564
OG		 516{
517 struct mlx5e_hairpin_entry *hpe;
106be53b 518 u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
5c65c564
OG		 519
520 hash_for_each_possible(priv->fs.tc.hairpin_tbl, hpe,
106be53b
OG		 521 hairpin_hlist, hash_key) {
522 if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio)
5c65c564
OG		 523 return hpe;
524 }
525
526 return NULL;
527}
528
106be53b
OG		 529#define UNKNOWN_MATCH_PRIO 8
530
531static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
e98bedf5
EB		 532 struct mlx5_flow_spec *spec, u8 *match_prio,
533 struct netlink_ext_ack *extack)
106be53b
OG		 534{
535 void *headers_c, *headers_v;
536 u8 prio_val, prio_mask = 0;
537 bool vlan_present;
538
539#ifdef CONFIG_MLX5_CORE_EN_DCB
540 if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
e98bedf5
EB		 541 NL_SET_ERR_MSG_MOD(extack,
542 "only PCP trust state supported for hairpin");
106be53b
OG		 543 return -EOPNOTSUPP;
544 }
545#endif
546 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
547 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
548
549 vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
550 if (vlan_present) {
551 prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
552 prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
553 }
554
555 if (!vlan_present || !prio_mask) {
556 prio_val = UNKNOWN_MATCH_PRIO;
557 } else if (prio_mask != 0x7) {
e98bedf5
EB		 558 NL_SET_ERR_MSG_MOD(extack,
559 "masked priority match not supported for hairpin");
106be53b
OG		 560 return -EOPNOTSUPP;
561 }
562
563 *match_prio = prio_val;
564 return 0;
565}
566
5c65c564
OG		 567static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
568 struct mlx5e_tc_flow *flow,
e98bedf5
EB		 569 struct mlx5e_tc_flow_parse_attr *parse_attr,
570 struct netlink_ext_ack *extack)
5c65c564
OG		 571{
572 int peer_ifindex = parse_attr->mirred_ifindex;
573 struct mlx5_hairpin_params params;
d8822868 574 struct mlx5_core_dev *peer_mdev;
5c65c564
OG		 575 struct mlx5e_hairpin_entry *hpe;
576 struct mlx5e_hairpin *hp;
3f6d08d1
OG		 577 u64 link_speed64;
578 u32 link_speed;
106be53b 579 u8 match_prio;
d8822868 580 u16 peer_id;
5c65c564
OG		 581 int err;
582
d8822868
OG		 583 peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
584 if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
e98bedf5 585 NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
5c65c564
OG		 586 return -EOPNOTSUPP;
587 }
588
d8822868 589 peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
e98bedf5
EB		 590 err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
591 extack);
106be53b
OG		 592 if (err)
593 return err;
594 hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
5c65c564
OG		 595 if (hpe)
596 goto attach_flow;
597
598 hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
599 if (!hpe)
600 return -ENOMEM;
601
602 INIT_LIST_HEAD(&hpe->flows);
d8822868 603 hpe->peer_vhca_id = peer_id;
106be53b 604 hpe->prio = match_prio;
5c65c564
OG		 605
606 params.log_data_size = 15;
607 params.log_data_size = min_t(u8, params.log_data_size,
608 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
609 params.log_data_size = max_t(u8, params.log_data_size,
610 MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz));
5c65c564 611
eb9180f7
OG		 612 params.log_num_packets = params.log_data_size -
613 MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev);
614 params.log_num_packets = min_t(u8, params.log_num_packets,
615 MLX5_CAP_GEN(priv->mdev, log_max_hairpin_num_packets));
616
617 params.q_counter = priv->q_counter;
3f6d08d1 618 /* set hairpin pair per each 50Gbs share of the link */
2c81bfd5 619 mlx5e_port_max_linkspeed(priv->mdev, &link_speed);
3f6d08d1
OG		 620 link_speed = max_t(u32, link_speed, 50000);
621 link_speed64 = link_speed;
622 do_div(link_speed64, 50000);
623 params.num_channels = link_speed64;
624
5c65c564
OG		 625 hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
626 if (IS_ERR(hp)) {
627 err = PTR_ERR(hp);
628 goto create_hairpin_err;
629 }
630
eb9180f7 631 netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
ddae74ac 632 hp->tirn, hp->pair->rqn[0], hp->pair->peer_mdev->priv.name,
eb9180f7 633 hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
5c65c564
OG		 634
635 hpe->hp = hp;
106be53b
OG		 636 hash_add(priv->fs.tc.hairpin_tbl, &hpe->hairpin_hlist,
637 hash_hairpin_info(peer_id, match_prio));
5c65c564
OG		 638
639attach_flow:
3f6d08d1
OG		 640 if (hpe->hp->num_channels > 1) {
641 flow->flags |= MLX5E_TC_FLOW_HAIRPIN_RSS;
642 flow->nic_attr->hairpin_ft = hpe->hp->ttc.ft.t;
643 } else {
644 flow->nic_attr->hairpin_tirn = hpe->hp->tirn;
645 }
5c65c564 646 list_add(&flow->hairpin, &hpe->flows);
3f6d08d1 647
5c65c564
OG		 648 return 0;
649
650create_hairpin_err:
651 kfree(hpe);
652 return err;
653}
654
655static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
656 struct mlx5e_tc_flow *flow)
657{
658 struct list_head *next = flow->hairpin.next;
659
660 list_del(&flow->hairpin);
661
662 /* no more hairpin flows for us, release the hairpin pair */
663 if (list_empty(next)) {
664 struct mlx5e_hairpin_entry *hpe;
665
666 hpe = list_entry(next, struct mlx5e_hairpin_entry, flows);
667
668 netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
669 hpe->hp->pair->peer_mdev->priv.name);
670
671 mlx5e_hairpin_destroy(hpe->hp);
672 hash_del(&hpe->hairpin_hlist);
673 kfree(hpe);
674 }
675}
676
c83954ab 677static int
74491de9 678mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 679 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 680 struct mlx5e_tc_flow *flow,
681 struct netlink_ext_ack *extack)
e8f887ac 682{
aa0cbbae 683 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 684 struct mlx5_core_dev *dev = priv->mdev;
5c65c564 685 struct mlx5_flow_destination dest[2] = {};
66958ed9 686 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 687 .action = attr->action,
688 .flow_tag = attr->flow_tag,
60786f09 689 .reformat_id = 0,
42f7ad67 690 .flags = FLOW_ACT_HAS_TAG | FLOW_ACT_NO_APPEND,
66958ed9 691 };
aad7e08d 692 struct mlx5_fc *counter = NULL;
e8f887ac 693 bool table_created = false;
5c65c564 694 int err, dest_ix = 0;
e8f887ac 695
3f6d08d1 696 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN) {
e98bedf5 697 err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
3f6d08d1 698 if (err) {
3f6d08d1
OG		 699 goto err_add_hairpin_flow;
700 }
701 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN_RSS) {
702 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
703 dest[dest_ix].ft = attr->hairpin_ft;
704 } else {
5c65c564
OG		 705 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
706 dest[dest_ix].tir_num = attr->hairpin_tirn;
5c65c564
OG		 707 }
708 dest_ix++;
3f6d08d1
OG		 709 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
710 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
711 dest[dest_ix].ft = priv->fs.vlan.ft.t;
712 dest_ix++;
5c65c564 713 }
aad7e08d 714
5c65c564
OG		 715 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
716 counter = mlx5_fc_create(dev, true);
717 if (IS_ERR(counter)) {
c83954ab 718 err = PTR_ERR(counter);
5c65c564
OG		 719 goto err_fc_create;
720 }
721 dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
171c7625 722 dest[dest_ix].counter_id = mlx5_fc_id(counter);
5c65c564 723 dest_ix++;
b8aee822 724 attr->counter = counter;
aad7e08d
AV		 725 }
726
2f4fe4ca 727 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 728 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 729 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca 730 kfree(parse_attr->mod_hdr_actions);
c83954ab 731 if (err)
2f4fe4ca 732 goto err_create_mod_hdr_id;
2f4fe4ca
OG		 733 }
734
acff797c 735 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
21b9c144
OG		 736 int tc_grp_size, tc_tbl_size;
737 u32 max_flow_counter;
738
739 max_flow_counter = (MLX5_CAP_GEN(dev, max_flow_counter_31_16) << 16) |
740 MLX5_CAP_GEN(dev, max_flow_counter_15_0);
741
742 tc_grp_size = min_t(int, max_flow_counter, MLX5E_TC_TABLE_MAX_GROUP_SIZE);
743
744 tc_tbl_size = min_t(int, tc_grp_size * MLX5E_TC_TABLE_NUM_GROUPS,
745 BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev, log_max_ft_size)));
746
acff797c
MG		 747 priv->fs.tc.t =
748 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
749 MLX5E_TC_PRIO,
21b9c144 750 tc_tbl_size,
acff797c 751 MLX5E_TC_TABLE_NUM_GROUPS,
3f6d08d1 752 MLX5E_TC_FT_LEVEL, 0);
acff797c 753 if (IS_ERR(priv->fs.tc.t)) {
e98bedf5
EB		 754 NL_SET_ERR_MSG_MOD(extack,
755 "Failed to create tc offload table\n");
e8f887ac
AV		 756 netdev_err(priv->netdev,
757 "Failed to create tc offload table\n");
c83954ab 758 err = PTR_ERR(priv->fs.tc.t);
aad7e08d 759 goto err_create_ft;
e8f887ac
AV		 760 }
761
762 table_created = true;
763 }
764
38aa51c1
OG		 765 if (attr->match_level != MLX5_MATCH_NONE)
766 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
767
c83954ab
RL		 768 flow->rule[0] = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
769 &flow_act, dest, dest_ix);
aad7e08d 770
c83954ab
RL		 771 if (IS_ERR(flow->rule[0])) {
772 err = PTR_ERR(flow->rule[0]);
aad7e08d 773 goto err_add_rule;
c83954ab 774 }
aad7e08d 775
c83954ab 776 return 0;
e8f887ac 777
aad7e08d
AV		 778err_add_rule:
779 if (table_created) {
acff797c
MG		 780 mlx5_destroy_flow_table(priv->fs.tc.t);
781 priv->fs.tc.t = NULL;
e8f887ac 782 }
aad7e08d 783err_create_ft:
2f4fe4ca 784 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 785 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 786err_create_mod_hdr_id:
aad7e08d 787 mlx5_fc_destroy(dev, counter);
5c65c564
OG		 788err_fc_create:
789 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
790 mlx5e_hairpin_flow_del(priv, flow);
791err_add_hairpin_flow:
c83954ab 792 return err;
e8f887ac
AV		 793}
794
d85cdccb
OG		 795static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
796 struct mlx5e_tc_flow *flow)
797{
513f8f7f 798 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 799 struct mlx5_fc *counter = NULL;
800
b8aee822 801 counter = attr->counter;
e4ad91f2 802 mlx5_del_flow_rules(flow->rule[0]);
aa0cbbae 803 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb 804
b3a433de 805 if (!mlx5e_tc_num_filters(priv) && priv->fs.tc.t) {
d85cdccb
OG		 806 mlx5_destroy_flow_table(priv->fs.tc.t);
807 priv->fs.tc.t = NULL;
808 }
2f4fe4ca 809
513f8f7f 810 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 811 mlx5e_detach_mod_hdr(priv, flow);
5c65c564
OG		 812
813 if (flow->flags & MLX5E_TC_FLOW_HAIRPIN)
814 mlx5e_hairpin_flow_del(priv, flow);
d85cdccb
OG		 815}
816
aa0cbbae
OG		 817static void mlx5e_detach_encap(struct mlx5e_priv *priv,
818 struct mlx5e_tc_flow *flow);
819
3c37745e
OG		 820static int mlx5e_attach_encap(struct mlx5e_priv *priv,
821 struct ip_tunnel_info *tun_info,
822 struct net_device *mirred_dev,
823 struct net_device **encap_dev,
e98bedf5
EB		 824 struct mlx5e_tc_flow *flow,
825 struct netlink_ext_ack *extack);
3c37745e 826
6d2a3ed0
OG		 827static struct mlx5_flow_handle *
828mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
829 struct mlx5e_tc_flow *flow,
830 struct mlx5_flow_spec *spec,
831 struct mlx5_esw_flow_attr *attr)
832{
833 struct mlx5_flow_handle *rule;
834
835 rule = mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
836 if (IS_ERR(rule))
837 return rule;
838
839 if (attr->mirror_count) {
840 flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
841 if (IS_ERR(flow->rule[1])) {
842 mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
843 return flow->rule[1];
844 }
845 }
846
847 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
848 return rule;
849}
850
851static void
852mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
853 struct mlx5e_tc_flow *flow,
854 struct mlx5_esw_flow_attr *attr)
855{
856 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
857
858 if (attr->mirror_count)
859 mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
860
861 mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
862}
863
5dbe906f
PB		 864static struct mlx5_flow_handle *
865mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
866 struct mlx5e_tc_flow *flow,
867 struct mlx5_flow_spec *spec,
868 struct mlx5_esw_flow_attr *slow_attr)
869{
870 struct mlx5_flow_handle *rule;
871
872 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
873 slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
874 slow_attr->mirror_count = 0,
875 slow_attr->dest_chain = FDB_SLOW_PATH_CHAIN,
876
877 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
878 if (!IS_ERR(rule))
879 flow->flags |= MLX5E_TC_FLOW_SLOW;
880
881 return rule;
882}
883
884static void
885mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
886 struct mlx5e_tc_flow *flow,
887 struct mlx5_esw_flow_attr *slow_attr)
888{
889 memcpy(slow_attr, flow->esw_attr, sizeof(*slow_attr));
890 mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
891 flow->flags &= ~MLX5E_TC_FLOW_SLOW;
892}
893
c83954ab 894static int
74491de9 895mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 896 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 897 struct mlx5e_tc_flow *flow,
898 struct netlink_ext_ack *extack)
adb4c123
OG		 899{
900 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
bf07aa73 901 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
aa0cbbae 902 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
bf07aa73 903 u16 max_prio = mlx5_eswitch_get_prio_range(esw);
3c37745e 904 struct net_device *out_dev, *encap_dev = NULL;
b8aee822 905 struct mlx5_fc *counter = NULL;
3c37745e
OG		 906 struct mlx5e_rep_priv *rpriv;
907 struct mlx5e_priv *out_priv;
c83954ab 908 int err = 0, encap_err = 0;
8b32580d 909
d14f6f2a
OG		 910 if (!mlx5_eswitch_prios_supported(esw) && attr->prio != 1) {
911 NL_SET_ERR_MSG(extack, "E-switch priorities unsupported, upgrade FW");
912 return -EOPNOTSUPP;
913 }
bf07aa73
PB		 914
915 if (attr->chain > max_chain) {
916 NL_SET_ERR_MSG(extack, "Requested chain is out of supported range");
917 err = -EOPNOTSUPP;
918 goto err_max_prio_chain;
919 }
920
921 if (attr->prio > max_prio) {
922 NL_SET_ERR_MSG(extack, "Requested priority is out of supported range");
923 err = -EOPNOTSUPP;
924 goto err_max_prio_chain;
925 }
e52c2802 926
60786f09 927 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) {
3c37745e
OG		 928 out_dev = __dev_get_by_index(dev_net(priv->netdev),
929 attr->parse_attr->mirred_ifindex);
c83954ab
RL		 930 encap_err = mlx5e_attach_encap(priv, &parse_attr->tun_info,
931 out_dev, &encap_dev, flow,
932 extack);
933 if (encap_err && encap_err != -EAGAIN) {
934 err = encap_err;
935 goto err_attach_encap;
3c37745e
OG		 936 }
937 out_priv = netdev_priv(encap_dev);
938 rpriv = out_priv->ppriv;
592d3651
CM		 939 attr->out_rep[attr->out_count] = rpriv->rep;
940 attr->out_mdev[attr->out_count++] = out_priv->mdev;
3c37745e
OG		 941 }
942
8b32580d 943 err = mlx5_eswitch_add_vlan_action(esw, attr);
c83954ab 944 if (err)
aa0cbbae 945 goto err_add_vlan;
adb4c123 946
d7e75a32 947 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 948 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 949 kfree(parse_attr->mod_hdr_actions);
c83954ab 950 if (err)
d7e75a32 951 goto err_mod_hdr;
d7e75a32
OG		 952 }
953
b8aee822
MB		 954 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
955 counter = mlx5_fc_create(esw->dev, true);
956 if (IS_ERR(counter)) {
c83954ab 957 err = PTR_ERR(counter);
b8aee822
MB		 958 goto err_create_counter;
959 }
960
961 attr->counter = counter;
962 }
963
c83954ab 964 /* we get here if (1) there's no error or when
3c37745e
OG		 965 * (2) there's an encap action and we're on -EAGAIN (no valid neigh)
966 */
5dbe906f
PB		 967 if (encap_err == -EAGAIN) {
968 /* continue with goto slow path rule instead */
969 struct mlx5_esw_flow_attr slow_attr;
970
971 flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec, &slow_attr);
972 } else {
6d2a3ed0 973 flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
3c37745e 974 }
c83954ab 975
5dbe906f
PB		 976 if (IS_ERR(flow->rule[0])) {
977 err = PTR_ERR(flow->rule[0]);
978 goto err_add_rule;
979 }
980
981 return 0;
aa0cbbae
OG		 982
983err_add_rule:
b8aee822
MB		 984 mlx5_fc_destroy(esw->dev, counter);
985err_create_counter:
513f8f7f 986 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 987 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 988err_mod_hdr:
aa0cbbae
OG		 989 mlx5_eswitch_del_vlan_action(esw, attr);
990err_add_vlan:
60786f09 991 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
aa0cbbae 992 mlx5e_detach_encap(priv, flow);
3c37745e 993err_attach_encap:
bf07aa73 994err_max_prio_chain:
c83954ab 995 return err;
aa0cbbae 996}
d85cdccb
OG		 997
998static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
999 struct mlx5e_tc_flow *flow)
1000{
1001 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 1002 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
5dbe906f 1003 struct mlx5_esw_flow_attr slow_attr;
d85cdccb 1004
5dbe906f
PB		 1005 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
1006 if (flow->flags & MLX5E_TC_FLOW_SLOW)
1007 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1008 else
1009 mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
1010 }
d85cdccb 1011
513f8f7f 1012 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 1013
60786f09 1014 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT) {
d85cdccb 1015 mlx5e_detach_encap(priv, flow);
513f8f7f 1016 kvfree(attr->parse_attr);
232c0013 1017 }
d7e75a32 1018
513f8f7f 1019 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 1020 mlx5e_detach_mod_hdr(priv, flow);
b8aee822
MB		 1021
1022 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1023 mlx5_fc_destroy(esw->dev, attr->counter);
d85cdccb
OG		 1024}
1025
232c0013
HHZ		 1026void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
1027 struct mlx5e_encap_entry *e)
1028{
3c37745e 1029 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 1030 struct mlx5_esw_flow_attr slow_attr, *esw_attr;
6d2a3ed0
OG		 1031 struct mlx5_flow_handle *rule;
1032 struct mlx5_flow_spec *spec;
232c0013
HHZ		 1033 struct mlx5e_tc_flow *flow;
1034 int err;
1035
60786f09
MB		 1036 err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
1037 e->encap_size, e->encap_header,
31ca3648 1038 MLX5_FLOW_NAMESPACE_FDB,
60786f09 1039 &e->encap_id);
232c0013
HHZ		 1040 if (err) {
1041 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
1042 err);
1043 return;
1044 }
1045 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1046 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 1047
1048 list_for_each_entry(flow, &e->flows, encap) {
3c37745e
OG		 1049 esw_attr = flow->esw_attr;
1050 esw_attr->encap_id = e->encap_id;
6d2a3ed0
OG		 1051 spec = &esw_attr->parse_attr->spec;
1052
5dbe906f 1053 /* update from slow path rule to encap rule */
6d2a3ed0
OG		 1054 rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, esw_attr);
1055 if (IS_ERR(rule)) {
1056 err = PTR_ERR(rule);
232c0013
HHZ		 1057 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
1058 err);
1059 continue;
1060 }
5dbe906f
PB		 1061
1062 mlx5e_tc_unoffload_from_slow_path(esw, flow, &slow_attr);
1063 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when slow path rule removed */
6d2a3ed0 1064 flow->rule[0] = rule;
232c0013
HHZ		 1065 }
1066}
1067
1068void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
1069 struct mlx5e_encap_entry *e)
1070{
3c37745e 1071 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f
PB		 1072 struct mlx5_esw_flow_attr slow_attr;
1073 struct mlx5_flow_handle *rule;
1074 struct mlx5_flow_spec *spec;
232c0013 1075 struct mlx5e_tc_flow *flow;
5dbe906f 1076 int err;
232c0013
HHZ		 1077
1078 list_for_each_entry(flow, &e->flows, encap) {
5dbe906f
PB		 1079 spec = &flow->esw_attr->parse_attr->spec;
1080
1081 /* update from encap rule to slow path rule */
1082 rule = mlx5e_tc_offload_to_slow_path(esw, flow, spec, &slow_attr);
1083
1084 if (IS_ERR(rule)) {
1085 err = PTR_ERR(rule);
1086 mlx5_core_warn(priv->mdev, "Failed to update slow path (encap) flow, %d\n",
1087 err);
1088 continue;
1089 }
1090
1091 mlx5e_tc_unoffload_fdb_rules(esw, flow, flow->esw_attr);
1092 flow->flags |= MLX5E_TC_FLOW_OFFLOADED; /* was unset when fast path rule removed */
1093 flow->rule[0] = rule;
232c0013
HHZ		 1094 }
1095
1096 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
1097 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
60786f09 1098 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013
HHZ		 1099 }
1100}
1101
b8aee822
MB		 1102static struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
1103{
1104 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1105 return flow->esw_attr->counter;
1106 else
1107 return flow->nic_attr->counter;
1108}
1109
f6dfb4c3
HHZ		 1110void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
1111{
1112 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
1113 u64 bytes, packets, lastuse = 0;
1114 struct mlx5e_tc_flow *flow;
1115 struct mlx5e_encap_entry *e;
1116 struct mlx5_fc *counter;
1117 struct neigh_table *tbl;
1118 bool neigh_used = false;
1119 struct neighbour *n;
1120
1121 if (m_neigh->family == AF_INET)
1122 tbl = &arp_tbl;
1123#if IS_ENABLED(CONFIG_IPV6)
1124 else if (m_neigh->family == AF_INET6)
423c9db2 1125 tbl = &nd_tbl;
f6dfb4c3
HHZ		 1126#endif
1127 else
1128 return;
1129
1130 list_for_each_entry(e, &nhe->encap_list, encap_list) {
1131 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
1132 continue;
1133 list_for_each_entry(flow, &e->flows, encap) {
1134 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
b8aee822 1135 counter = mlx5e_tc_get_counter(flow);
f6dfb4c3
HHZ		 1136 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
1137 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
1138 neigh_used = true;
1139 break;
1140 }
1141 }
1142 }
e36d4810
RD		 1143 if (neigh_used)
1144 break;
f6dfb4c3
HHZ		 1145 }
1146
1147 if (neigh_used) {
1148 nhe->reported_lastuse = jiffies;
1149
1150 /* find the relevant neigh according to the cached device and
1151 * dst ip pair
1152 */
1153 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
c7f7ba8d 1154 if (!n)
f6dfb4c3 1155 return;
f6dfb4c3
HHZ		 1156
1157 neigh_event_send(n, NULL);
1158 neigh_release(n);
1159 }
1160}
1161
d85cdccb
OG		 1162static void mlx5e_detach_encap(struct mlx5e_priv *priv,
1163 struct mlx5e_tc_flow *flow)
1164{
5067b602
RD		 1165 struct list_head *next = flow->encap.next;
1166
1167 list_del(&flow->encap);
1168 if (list_empty(next)) {
c1ae1152 1169 struct mlx5e_encap_entry *e;
5067b602 1170
c1ae1152 1171 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 1172 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
1173
1174 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
60786f09 1175 mlx5_packet_reformat_dealloc(priv->mdev, e->encap_id);
232c0013 1176
cdc5a7f3 1177 hash_del_rcu(&e->encap_hlist);
232c0013 1178 kfree(e->encap_header);
5067b602
RD		 1179 kfree(e);
1180 }
1181}
1182
e8f887ac 1183static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 1184 struct mlx5e_tc_flow *flow)
e8f887ac 1185{
d85cdccb
OG		 1186 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1187 mlx5e_tc_del_fdb_flow(priv, flow);
1188 else
1189 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 1190}
1191
bbd00f7e
HHZ		 1192static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
1193 struct tc_cls_flower_offload *f)
1194{
1195 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1196 outer_headers);
1197 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1198 outer_headers);
1199 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1200 misc_parameters);
1201 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1202 misc_parameters);
1203
1204 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
1205 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
1206
1207 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
1208 struct flow_dissector_key_keyid *key =
1209 skb_flow_dissector_target(f->dissector,
1210 FLOW_DISSECTOR_KEY_ENC_KEYID,
1211 f->key);
1212 struct flow_dissector_key_keyid *mask =
1213 skb_flow_dissector_target(f->dissector,
1214 FLOW_DISSECTOR_KEY_ENC_KEYID,
1215 f->mask);
1216 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
1217 be32_to_cpu(mask->keyid));
1218 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
1219 be32_to_cpu(key->keyid));
1220 }
1221}
1222
1223static int parse_tunnel_attr(struct mlx5e_priv *priv,
1224 struct mlx5_flow_spec *spec,
1225 struct tc_cls_flower_offload *f)
1226{
e98bedf5 1227 struct netlink_ext_ack *extack = f->common.extack;
bbd00f7e
HHZ		 1228 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1229 outer_headers);
1230 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1231 outer_headers);
1232
2e72eb43
OG		 1233 struct flow_dissector_key_control *enc_control =
1234 skb_flow_dissector_target(f->dissector,
1235 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1236 f->key);
1237
bbd00f7e
HHZ		 1238 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
1239 struct flow_dissector_key_ports *key =
1240 skb_flow_dissector_target(f->dissector,
1241 FLOW_DISSECTOR_KEY_ENC_PORTS,
1242 f->key);
1243 struct flow_dissector_key_ports *mask =
1244 skb_flow_dissector_target(f->dissector,
1245 FLOW_DISSECTOR_KEY_ENC_PORTS,
1246 f->mask);
1247
1248 /* Full udp dst port must be given */
1249 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 1250 goto vxlan_match_offload_err;
bbd00f7e 1251
a3e67366 1252 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 1253 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
1254 parse_vxlan_attr(spec, f);
2fcd82e9 1255 else {
e98bedf5
EB		 1256 NL_SET_ERR_MSG_MOD(extack,
1257 "port isn't an offloaded vxlan udp dport");
2fcd82e9
OG		 1258 netdev_warn(priv->netdev,
1259 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 1260 return -EOPNOTSUPP;
2fcd82e9 1261 }
bbd00f7e
HHZ		 1262
1263 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1264 udp_dport, ntohs(mask->dst));
1265 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1266 udp_dport, ntohs(key->dst));
1267
cd377663
OG		 1268 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1269 udp_sport, ntohs(mask->src));
1270 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1271 udp_sport, ntohs(key->src));
bbd00f7e 1272 } else { /* udp dst port must be given */
2fcd82e9 1273vxlan_match_offload_err:
e98bedf5
EB		 1274 NL_SET_ERR_MSG_MOD(extack,
1275 "IP tunnel decap offload supported only for vxlan, must set UDP dport");
2fcd82e9
OG		 1276 netdev_warn(priv->netdev,
1277 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
1278 return -EOPNOTSUPP;
bbd00f7e
HHZ		 1279 }
1280
2e72eb43 1281 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 1282 struct flow_dissector_key_ipv4_addrs *key =
1283 skb_flow_dissector_target(f->dissector,
1284 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1285 f->key);
1286 struct flow_dissector_key_ipv4_addrs *mask =
1287 skb_flow_dissector_target(f->dissector,
1288 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
1289 f->mask);
1290 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1291 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1292 ntohl(mask->src));
1293 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1294 src_ipv4_src_ipv6.ipv4_layout.ipv4,
1295 ntohl(key->src));
1296
1297 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1298 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1299 ntohl(mask->dst));
1300 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1301 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
1302 ntohl(key->dst));
bbd00f7e 1303
2e72eb43
OG		 1304 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1305 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 1306 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1307 struct flow_dissector_key_ipv6_addrs *key =
1308 skb_flow_dissector_target(f->dissector,
1309 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1310 f->key);
1311 struct flow_dissector_key_ipv6_addrs *mask =
1312 skb_flow_dissector_target(f->dissector,
1313 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
1314 f->mask);
1315
1316 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1317 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1318 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1319 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1320 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1321 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1322
1323 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1324 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1325 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1326 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1327 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1328 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
1329
1330 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
1331 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 1332 }
bbd00f7e 1333
bcef735c
OG		 1334 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_IP)) {
1335 struct flow_dissector_key_ip *key =
1336 skb_flow_dissector_target(f->dissector,
1337 FLOW_DISSECTOR_KEY_ENC_IP,
1338 f->key);
1339 struct flow_dissector_key_ip *mask =
1340 skb_flow_dissector_target(f->dissector,
1341 FLOW_DISSECTOR_KEY_ENC_IP,
1342 f->mask);
1343
1344 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1345 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1346
1347 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1348 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1349
1350 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1351 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
e98bedf5
EB		 1352
1353 if (mask->ttl &&
1354 !MLX5_CAP_ESW_FLOWTABLE_FDB
1355 (priv->mdev,
1356 ft_field_support.outer_ipv4_ttl)) {
1357 NL_SET_ERR_MSG_MOD(extack,
1358 "Matching on TTL is not supported");
1359 return -EOPNOTSUPP;
1360 }
1361
bcef735c
OG		 1362 }
1363
bbd00f7e
HHZ		 1364 /* Enforce DMAC when offloading incoming tunneled flows.
1365 * Flow counters require a match on the DMAC.
1366 */
1367 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
1368 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
1369 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1370 dmac_47_16), priv->netdev->dev_addr);
1371
1372 /* let software handle IP fragments */
1373 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1374 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
1375
1376 return 0;
1377}
1378
de0af0bf
RD		 1379static int __parse_cls_flower(struct mlx5e_priv *priv,
1380 struct mlx5_flow_spec *spec,
1381 struct tc_cls_flower_offload *f,
d708f902 1382 u8 *match_level)
e3a2b7ed 1383{
e98bedf5 1384 struct netlink_ext_ack *extack = f->common.extack;
c5bb1730
MG		 1385 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1386 outer_headers);
1387 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1388 outer_headers);
699e96dd
JL		 1389 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1390 misc_parameters);
1391 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1392 misc_parameters);
e3a2b7ed
AV		 1393 u16 addr_type = 0;
1394 u8 ip_proto = 0;
1395
d708f902 1396 *match_level = MLX5_MATCH_NONE;
de0af0bf 1397
e3a2b7ed
AV		 1398 if (f->dissector->used_keys &
1399 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
1400 BIT(FLOW_DISSECTOR_KEY_BASIC) |
1401 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 1402 BIT(FLOW_DISSECTOR_KEY_VLAN) |
699e96dd 1403 BIT(FLOW_DISSECTOR_KEY_CVLAN) |
e3a2b7ed
AV		 1404 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
1405 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 1406 BIT(FLOW_DISSECTOR_KEY_PORTS) |
1407 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
1408 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
1409 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
1410 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 1411 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b 1412 BIT(FLOW_DISSECTOR_KEY_TCP) |
bcef735c
OG		 1413 BIT(FLOW_DISSECTOR_KEY_IP) |
1414 BIT(FLOW_DISSECTOR_KEY_ENC_IP))) {
e98bedf5 1415 NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
e3a2b7ed
AV		 1416 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
1417 f->dissector->used_keys);
1418 return -EOPNOTSUPP;
1419 }
1420
bbd00f7e
HHZ		 1421 if ((dissector_uses_key(f->dissector,
1422 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
1423 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
1424 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
1425 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
1426 struct flow_dissector_key_control *key =
1427 skb_flow_dissector_target(f->dissector,
1428 FLOW_DISSECTOR_KEY_ENC_CONTROL,
1429 f->key);
1430 switch (key->addr_type) {
1431 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 1432 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 1433 if (parse_tunnel_attr(priv, spec, f))
1434 return -EOPNOTSUPP;
1435 break;
1436 default:
1437 return -EOPNOTSUPP;
1438 }
1439
1440 /* In decap flow, header pointers should point to the inner
1441 * headers, outer header were already set by parse_tunnel_attr
1442 */
1443 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
1444 inner_headers);
1445 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
1446 inner_headers);
1447 }
1448
d3a80bb5
OG		 1449 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1450 struct flow_dissector_key_basic *key =
e3a2b7ed 1451 skb_flow_dissector_target(f->dissector,
d3a80bb5 1452 FLOW_DISSECTOR_KEY_BASIC,
e3a2b7ed 1453 f->key);
d3a80bb5 1454 struct flow_dissector_key_basic *mask =
e3a2b7ed 1455 skb_flow_dissector_target(f->dissector,
d3a80bb5 1456 FLOW_DISSECTOR_KEY_BASIC,
e3a2b7ed 1457 f->mask);
d3a80bb5
OG		 1458 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
1459 ntohs(mask->n_proto));
1460 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
1461 ntohs(key->n_proto));
e3a2b7ed 1462
d3a80bb5 1463 if (mask->n_proto)
d708f902 1464 *match_level = MLX5_MATCH_L2;
e3a2b7ed
AV		 1465 }
1466
095b6cfd
OG		 1467 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
1468 struct flow_dissector_key_vlan *key =
1469 skb_flow_dissector_target(f->dissector,
1470 FLOW_DISSECTOR_KEY_VLAN,
1471 f->key);
1472 struct flow_dissector_key_vlan *mask =
1473 skb_flow_dissector_target(f->dissector,
1474 FLOW_DISSECTOR_KEY_VLAN,
1475 f->mask);
699e96dd
JL		 1476 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1477 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1478 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1479 svlan_tag, 1);
1480 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1481 svlan_tag, 1);
1482 } else {
1483 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1484 cvlan_tag, 1);
1485 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1486 cvlan_tag, 1);
1487 }
095b6cfd
OG		 1488
1489 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
1490 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 1491
1492 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
1493 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
54782900 1494
d708f902 1495 *match_level = MLX5_MATCH_L2;
54782900 1496 }
d3a80bb5 1497 } else if (*match_level != MLX5_MATCH_NONE) {
cee26487
JL		 1498 MLX5_SET(fte_match_set_lyr_2_4, headers_c, svlan_tag, 1);
1499 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
d3a80bb5 1500 *match_level = MLX5_MATCH_L2;
54782900
OG		 1501 }
1502
699e96dd
JL		 1503 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CVLAN)) {
1504 struct flow_dissector_key_vlan *key =
1505 skb_flow_dissector_target(f->dissector,
1506 FLOW_DISSECTOR_KEY_CVLAN,
1507 f->key);
1508 struct flow_dissector_key_vlan *mask =
1509 skb_flow_dissector_target(f->dissector,
1510 FLOW_DISSECTOR_KEY_CVLAN,
1511 f->mask);
1512 if (mask->vlan_id || mask->vlan_priority || mask->vlan_tpid) {
1513 if (key->vlan_tpid == htons(ETH_P_8021AD)) {
1514 MLX5_SET(fte_match_set_misc, misc_c,
1515 outer_second_svlan_tag, 1);
1516 MLX5_SET(fte_match_set_misc, misc_v,
1517 outer_second_svlan_tag, 1);
1518 } else {
1519 MLX5_SET(fte_match_set_misc, misc_c,
1520 outer_second_cvlan_tag, 1);
1521 MLX5_SET(fte_match_set_misc, misc_v,
1522 outer_second_cvlan_tag, 1);
1523 }
1524
1525 MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
1526 mask->vlan_id);
1527 MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
1528 key->vlan_id);
1529 MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
1530 mask->vlan_priority);
1531 MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
1532 key->vlan_priority);
1533
1534 *match_level = MLX5_MATCH_L2;
1535 }
1536 }
1537
d3a80bb5
OG		 1538 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
1539 struct flow_dissector_key_eth_addrs *key =
54782900 1540 skb_flow_dissector_target(f->dissector,
d3a80bb5 1541 FLOW_DISSECTOR_KEY_ETH_ADDRS,
54782900 1542 f->key);
d3a80bb5 1543 struct flow_dissector_key_eth_addrs *mask =
54782900 1544 skb_flow_dissector_target(f->dissector,
d3a80bb5 1545 FLOW_DISSECTOR_KEY_ETH_ADDRS,
54782900 1546 f->mask);
54782900 1547
d3a80bb5
OG		 1548 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1549 dmac_47_16),
1550 mask->dst);
1551 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1552 dmac_47_16),
1553 key->dst);
1554
1555 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1556 smac_47_16),
1557 mask->src);
1558 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1559 smac_47_16),
1560 key->src);
1561
1562 if (!is_zero_ether_addr(mask->src) || !is_zero_ether_addr(mask->dst))
d708f902 1563 *match_level = MLX5_MATCH_L2;
54782900
OG		 1564 }
1565
1566 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
1567 struct flow_dissector_key_control *key =
1568 skb_flow_dissector_target(f->dissector,
1569 FLOW_DISSECTOR_KEY_CONTROL,
1570 f->key);
1571
1572 struct flow_dissector_key_control *mask =
1573 skb_flow_dissector_target(f->dissector,
1574 FLOW_DISSECTOR_KEY_CONTROL,
1575 f->mask);
1576 addr_type = key->addr_type;
1577
1578 /* the HW doesn't support frag first/later */
1579 if (mask->flags & FLOW_DIS_FIRST_FRAG)
1580 return -EOPNOTSUPP;
1581
1582 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
1583 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
1584 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
1585 key->flags & FLOW_DIS_IS_FRAGMENT);
1586
1587 /* the HW doesn't need L3 inline to match on frag=no */
1588 if (!(key->flags & FLOW_DIS_IS_FRAGMENT))
83621b7d 1589 *match_level = MLX5_MATCH_L2;
54782900
OG		 1590 /* *** L2 attributes parsing up to here *** */
1591 else
83621b7d 1592 *match_level = MLX5_MATCH_L3;
095b6cfd
OG		 1593 }
1594 }
1595
54782900
OG		 1596 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
1597 struct flow_dissector_key_basic *key =
1598 skb_flow_dissector_target(f->dissector,
1599 FLOW_DISSECTOR_KEY_BASIC,
1600 f->key);
1601 struct flow_dissector_key_basic *mask =
1602 skb_flow_dissector_target(f->dissector,
1603 FLOW_DISSECTOR_KEY_BASIC,
1604 f->mask);
1605 ip_proto = key->ip_proto;
1606
1607 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1608 mask->ip_proto);
1609 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1610 key->ip_proto);
1611
1612 if (mask->ip_proto)
d708f902 1613 *match_level = MLX5_MATCH_L3;
54782900
OG		 1614 }
1615
e3a2b7ed
AV		 1616 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
1617 struct flow_dissector_key_ipv4_addrs *key =
1618 skb_flow_dissector_target(f->dissector,
1619 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1620 f->key);
1621 struct flow_dissector_key_ipv4_addrs *mask =
1622 skb_flow_dissector_target(f->dissector,
1623 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
1624 f->mask);
1625
1626 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1627 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1628 &mask->src, sizeof(mask->src));
1629 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1630 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1631 &key->src, sizeof(key->src));
1632 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1633 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1634 &mask->dst, sizeof(mask->dst));
1635 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1636 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1637 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1638
1639 if (mask->src || mask->dst)
d708f902 1640 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1641 }
1642
1643 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
1644 struct flow_dissector_key_ipv6_addrs *key =
1645 skb_flow_dissector_target(f->dissector,
1646 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1647 f->key);
1648 struct flow_dissector_key_ipv6_addrs *mask =
1649 skb_flow_dissector_target(f->dissector,
1650 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
1651 f->mask);
1652
1653 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1654 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1655 &mask->src, sizeof(mask->src));
1656 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1657 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1658 &key->src, sizeof(key->src));
1659
1660 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1661 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1662 &mask->dst, sizeof(mask->dst));
1663 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1664 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1665 &key->dst, sizeof(key->dst));
de0af0bf
RD		 1666
1667 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
1668 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
d708f902 1669 *match_level = MLX5_MATCH_L3;
e3a2b7ed
AV		 1670 }
1671
1f97a526
OG		 1672 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
1673 struct flow_dissector_key_ip *key =
1674 skb_flow_dissector_target(f->dissector,
1675 FLOW_DISSECTOR_KEY_IP,
1676 f->key);
1677 struct flow_dissector_key_ip *mask =
1678 skb_flow_dissector_target(f->dissector,
1679 FLOW_DISSECTOR_KEY_IP,
1680 f->mask);
1681
1682 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
1683 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
1684
1685 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
1686 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
1687
a8ade55f
OG		 1688 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
1689 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 1690
a8ade55f
OG		 1691 if (mask->ttl &&
1692 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
e98bedf5
EB		 1693 ft_field_support.outer_ipv4_ttl)) {
1694 NL_SET_ERR_MSG_MOD(extack,
1695 "Matching on TTL is not supported");
1f97a526 1696 return -EOPNOTSUPP;
e98bedf5 1697 }
a8ade55f
OG		 1698
1699 if (mask->tos || mask->ttl)
d708f902 1700 *match_level = MLX5_MATCH_L3;
1f97a526
OG		 1701 }
1702
54782900
OG		 1703 /* *** L3 attributes parsing up to here *** */
1704
e3a2b7ed
AV		 1705 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
1706 struct flow_dissector_key_ports *key =
1707 skb_flow_dissector_target(f->dissector,
1708 FLOW_DISSECTOR_KEY_PORTS,
1709 f->key);
1710 struct flow_dissector_key_ports *mask =
1711 skb_flow_dissector_target(f->dissector,
1712 FLOW_DISSECTOR_KEY_PORTS,
1713 f->mask);
1714 switch (ip_proto) {
1715 case IPPROTO_TCP:
1716 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1717 tcp_sport, ntohs(mask->src));
1718 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1719 tcp_sport, ntohs(key->src));
1720
1721 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1722 tcp_dport, ntohs(mask->dst));
1723 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1724 tcp_dport, ntohs(key->dst));
1725 break;
1726
1727 case IPPROTO_UDP:
1728 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1729 udp_sport, ntohs(mask->src));
1730 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1731 udp_sport, ntohs(key->src));
1732
1733 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1734 udp_dport, ntohs(mask->dst));
1735 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1736 udp_dport, ntohs(key->dst));
1737 break;
1738 default:
e98bedf5
EB		 1739 NL_SET_ERR_MSG_MOD(extack,
1740 "Only UDP and TCP transports are supported for L4 matching");
e3a2b7ed
AV		 1741 netdev_err(priv->netdev,
1742 "Only UDP and TCP transport are supported\n");
1743 return -EINVAL;
1744 }
de0af0bf
RD		 1745
1746 if (mask->src || mask->dst)
d708f902 1747 *match_level = MLX5_MATCH_L4;
e3a2b7ed
AV		 1748 }
1749
e77834ec
OG		 1750 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
1751 struct flow_dissector_key_tcp *key =
1752 skb_flow_dissector_target(f->dissector,
1753 FLOW_DISSECTOR_KEY_TCP,
1754 f->key);
1755 struct flow_dissector_key_tcp *mask =
1756 skb_flow_dissector_target(f->dissector,
1757 FLOW_DISSECTOR_KEY_TCP,
1758 f->mask);
1759
1760 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
1761 ntohs(mask->flags));
1762 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
1763 ntohs(key->flags));
1764
1765 if (mask->flags)
d708f902 1766 *match_level = MLX5_MATCH_L4;
e77834ec
OG		 1767 }
1768
e3a2b7ed
AV		 1769 return 0;
1770}
1771
de0af0bf 1772static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 1773 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 1774 struct mlx5_flow_spec *spec,
1775 struct tc_cls_flower_offload *f)
1776{
e98bedf5 1777 struct netlink_ext_ack *extack = f->common.extack;
de0af0bf
RD		 1778 struct mlx5_core_dev *dev = priv->mdev;
1779 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 1780 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1781 struct mlx5_eswitch_rep *rep;
d708f902 1782 u8 match_level;
de0af0bf
RD		 1783 int err;
1784
d708f902 1785 err = __parse_cls_flower(priv, spec, f, &match_level);
de0af0bf 1786
1d447a39
SM		 1787 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
1788 rep = rpriv->rep;
1789 if (rep->vport != FDB_UPLINK_VPORT &&
1790 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
d708f902 1791 esw->offloads.inline_mode < match_level)) {
e98bedf5
EB		 1792 NL_SET_ERR_MSG_MOD(extack,
1793 "Flow is not offloaded due to min inline setting");
de0af0bf
RD		 1794 netdev_warn(priv->netdev,
1795 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
d708f902 1796 match_level, esw->offloads.inline_mode);
de0af0bf
RD		 1797 return -EOPNOTSUPP;
1798 }
1799 }
1800
38aa51c1
OG		 1801 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
1802 flow->esw_attr->match_level = match_level;
1803 else
1804 flow->nic_attr->match_level = match_level;
1805
de0af0bf
RD		 1806 return err;
1807}
1808
d79b6df6
OG		 1809struct pedit_headers {
1810 struct ethhdr eth;
1811 struct iphdr ip4;
1812 struct ipv6hdr ip6;
1813 struct tcphdr tcp;
1814 struct udphdr udp;
1815};
1816
1817static int pedit_header_offsets[] = {
1818 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1819 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1820 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1821 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1822 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1823};
1824
1825#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1826
1827static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1828 struct pedit_headers *masks,
1829 struct pedit_headers *vals)
1830{
1831 u32 *curr_pmask, *curr_pval;
1832
1833 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1834 goto out_err;
1835
1836 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1837 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1838
1839 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1840 goto out_err;
1841
1842 *curr_pmask |= mask;
1843 *curr_pval |= (val & mask);
1844
1845 return 0;
1846
1847out_err:
1848 return -EOPNOTSUPP;
1849}
1850
1851struct mlx5_fields {
1852 u8 field;
1853 u8 size;
1854 u32 offset;
1855};
1856
a8e4f0c4
OG		 1857#define OFFLOAD(fw_field, size, field, off) \
1858 {MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, size, offsetof(struct pedit_headers, field) + (off)}
1859
d79b6df6 1860static struct mlx5_fields fields[] = {
a8e4f0c4
OG		 1861 OFFLOAD(DMAC_47_16, 4, eth.h_dest[0], 0),
1862 OFFLOAD(DMAC_15_0, 2, eth.h_dest[4], 0),
1863 OFFLOAD(SMAC_47_16, 4, eth.h_source[0], 0),
1864 OFFLOAD(SMAC_15_0, 2, eth.h_source[4], 0),
1865 OFFLOAD(ETHERTYPE, 2, eth.h_proto, 0),
1866
1867 OFFLOAD(IP_TTL, 1, ip4.ttl, 0),
1868 OFFLOAD(SIPV4, 4, ip4.saddr, 0),
1869 OFFLOAD(DIPV4, 4, ip4.daddr, 0),
1870
1871 OFFLOAD(SIPV6_127_96, 4, ip6.saddr.s6_addr32[0], 0),
1872 OFFLOAD(SIPV6_95_64, 4, ip6.saddr.s6_addr32[1], 0),
1873 OFFLOAD(SIPV6_63_32, 4, ip6.saddr.s6_addr32[2], 0),
1874 OFFLOAD(SIPV6_31_0, 4, ip6.saddr.s6_addr32[3], 0),
1875 OFFLOAD(DIPV6_127_96, 4, ip6.daddr.s6_addr32[0], 0),
1876 OFFLOAD(DIPV6_95_64, 4, ip6.daddr.s6_addr32[1], 0),
1877 OFFLOAD(DIPV6_63_32, 4, ip6.daddr.s6_addr32[2], 0),
1878 OFFLOAD(DIPV6_31_0, 4, ip6.daddr.s6_addr32[3], 0),
0c0316f5 1879 OFFLOAD(IPV6_HOPLIMIT, 1, ip6.hop_limit, 0),
a8e4f0c4
OG		 1880
1881 OFFLOAD(TCP_SPORT, 2, tcp.source, 0),
1882 OFFLOAD(TCP_DPORT, 2, tcp.dest, 0),
1883 OFFLOAD(TCP_FLAGS, 1, tcp.ack_seq, 5),
1884
1885 OFFLOAD(UDP_SPORT, 2, udp.source, 0),
1886 OFFLOAD(UDP_DPORT, 2, udp.dest, 0),
d79b6df6
OG		 1887};
1888
1889/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1890 * max from the SW pedit action. On success, it says how many HW actions were
1891 * actually parsed.
1892 */
1893static int offload_pedit_fields(struct pedit_headers *masks,
1894 struct pedit_headers *vals,
e98bedf5
EB		 1895 struct mlx5e_tc_flow_parse_attr *parse_attr,
1896 struct netlink_ext_ack *extack)
d79b6df6
OG		 1897{
1898 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1899 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1900 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1901 struct mlx5_fields *f;
1902 u8 cmd, field_bsize;
e3ca4e05 1903 u32 s_mask, a_mask;
d79b6df6 1904 unsigned long mask;
2b64beba
OG		 1905 __be32 mask_be32;
1906 __be16 mask_be16;
d79b6df6
OG		 1907 void *action;
1908
1909 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1910 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1911 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1912 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1913
1914 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1915 action = parse_attr->mod_hdr_actions;
1916 max_actions = parse_attr->num_mod_hdr_actions;
1917 nactions = 0;
1918
1919 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1920 f = &fields[i];
1921 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1922 s_mask = 0;
1923 a_mask = 0;
d79b6df6
OG		 1924
1925 s_masks_p = (void *)set_masks + f->offset;
1926 a_masks_p = (void *)add_masks + f->offset;
1927
1928 memcpy(&s_mask, s_masks_p, f->size);
1929 memcpy(&a_mask, a_masks_p, f->size);
1930
1931 if (!s_mask && !a_mask) /* nothing to offload here */
1932 continue;
1933
1934 if (s_mask && a_mask) {
e98bedf5
EB		 1935 NL_SET_ERR_MSG_MOD(extack,
1936 "can't set and add to the same HW field");
d79b6df6
OG		 1937 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1938 return -EOPNOTSUPP;
1939 }
1940
1941 if (nactions == max_actions) {
e98bedf5
EB		 1942 NL_SET_ERR_MSG_MOD(extack,
1943 "too many pedit actions, can't offload");
d79b6df6
OG		 1944 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1945 return -EOPNOTSUPP;
1946 }
1947
1948 if (s_mask) {
1949 cmd = MLX5_ACTION_TYPE_SET;
1950 mask = s_mask;
1951 vals_p = (void *)set_vals + f->offset;
1952 /* clear to denote we consumed this field */
1953 memset(s_masks_p, 0, f->size);
1954 } else {
1955 cmd = MLX5_ACTION_TYPE_ADD;
1956 mask = a_mask;
1957 vals_p = (void *)add_vals + f->offset;
1958 /* clear to denote we consumed this field */
1959 memset(a_masks_p, 0, f->size);
1960 }
1961
d79b6df6 1962 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1963
2b64beba
OG		 1964 if (field_bsize == 32) {
1965 mask_be32 = *(__be32 *)&mask;
1966 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1967 } else if (field_bsize == 16) {
1968 mask_be16 = *(__be16 *)&mask;
1969 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1970 }
1971
d79b6df6 1972 first = find_first_bit(&mask, field_bsize);
2b64beba 1973 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1974 last = find_last_bit(&mask, field_bsize);
2b64beba 1975 if (first < next_z && next_z < last) {
e98bedf5
EB		 1976 NL_SET_ERR_MSG_MOD(extack,
1977 "rewrite of few sub-fields isn't supported");
2b64beba 1978 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1979 mask);
1980 return -EOPNOTSUPP;
1981 }
1982
1983 MLX5_SET(set_action_in, action, action_type, cmd);
1984 MLX5_SET(set_action_in, action, field, f->field);
1985
1986 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1987 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1988 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1989 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1990 }
1991
1992 if (field_bsize == 32)
2b64beba 1993 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1994 else if (field_bsize == 16)
2b64beba 1995 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1996 else if (field_bsize == 8)
2b64beba 1997 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1998
1999 action += action_size;
2000 nactions++;
2001 }
2002
2003 parse_attr->num_mod_hdr_actions = nactions;
2004 return 0;
2005}
2006
2007static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
2008 const struct tc_action *a, int namespace,
2009 struct mlx5e_tc_flow_parse_attr *parse_attr)
2010{
2011 int nkeys, action_size, max_actions;
2012
2013 nkeys = tcf_pedit_nkeys(a);
2014 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
2015
2016 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
2017 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
2018 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
2019 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
2020
2021 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
2022 max_actions = min(max_actions, nkeys * 16);
2023
2024 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
2025 if (!parse_attr->mod_hdr_actions)
2026 return -ENOMEM;
2027
2028 parse_attr->num_mod_hdr_actions = max_actions;
2029 return 0;
2030}
2031
2032static const struct pedit_headers zero_masks = {};
2033
2034static int parse_tc_pedit_action(struct mlx5e_priv *priv,
2035 const struct tc_action *a, int namespace,
e98bedf5
EB		 2036 struct mlx5e_tc_flow_parse_attr *parse_attr,
2037 struct netlink_ext_ack *extack)
d79b6df6
OG		 2038{
2039 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
2040 int nkeys, i, err = -EOPNOTSUPP;
2041 u32 mask, val, offset;
2042 u8 cmd, htype;
2043
2044 nkeys = tcf_pedit_nkeys(a);
2045
2046 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2047 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
2048
2049 for (i = 0; i < nkeys; i++) {
2050 htype = tcf_pedit_htype(a, i);
2051 cmd = tcf_pedit_cmd(a, i);
2052 err = -EOPNOTSUPP; /* can't be all optimistic */
2053
2054 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
e98bedf5
EB		 2055 NL_SET_ERR_MSG_MOD(extack,
2056 "legacy pedit isn't offloaded");
d79b6df6
OG		 2057 goto out_err;
2058 }
2059
2060 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
e98bedf5 2061 NL_SET_ERR_MSG_MOD(extack, "pedit cmd isn't offloaded");
d79b6df6
OG		 2062 goto out_err;
2063 }
2064
2065 mask = tcf_pedit_mask(a, i);
2066 val = tcf_pedit_val(a, i);
2067 offset = tcf_pedit_offset(a, i);
2068
2069 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
2070 if (err)
2071 goto out_err;
2072 }
2073
2074 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
2075 if (err)
2076 goto out_err;
2077
e98bedf5 2078 err = offload_pedit_fields(masks, vals, parse_attr, extack);
d79b6df6
OG		 2079 if (err < 0)
2080 goto out_dealloc_parsed_actions;
2081
2082 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
2083 cmd_masks = &masks[cmd];
2084 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
e98bedf5
EB		 2085 NL_SET_ERR_MSG_MOD(extack,
2086 "attempt to offload an unsupported field");
b3a433de 2087 netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
d79b6df6
OG		 2088 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
2089 16, 1, cmd_masks, sizeof(zero_masks), true);
2090 err = -EOPNOTSUPP;
2091 goto out_dealloc_parsed_actions;
2092 }
2093 }
2094
2095 return 0;
2096
2097out_dealloc_parsed_actions:
2098 kfree(parse_attr->mod_hdr_actions);
2099out_err:
2100 return err;
2101}
2102
e98bedf5
EB		 2103static bool csum_offload_supported(struct mlx5e_priv *priv,
2104 u32 action,
2105 u32 update_flags,
2106 struct netlink_ext_ack *extack)
26c02749
OG		 2107{
2108 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
2109 TCA_CSUM_UPDATE_FLAG_UDP;
2110
2111 /* The HW recalcs checksums only if re-writing headers */
2112 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
e98bedf5
EB		 2113 NL_SET_ERR_MSG_MOD(extack,
2114 "TC csum action is only offloaded with pedit");
26c02749
OG		 2115 netdev_warn(priv->netdev,
2116 "TC csum action is only offloaded with pedit\n");
2117 return false;
2118 }
2119
2120 if (update_flags & ~prot_flags) {
e98bedf5
EB		 2121 NL_SET_ERR_MSG_MOD(extack,
2122 "can't offload TC csum action for some header/s");
26c02749
OG		 2123 netdev_warn(priv->netdev,
2124 "can't offload TC csum action for some header/s - flags %#x\n",
2125 update_flags);
2126 return false;
2127 }
2128
2129 return true;
2130}
2131
bdd66ac0 2132static bool modify_header_match_supported(struct mlx5_flow_spec *spec,
e98bedf5
EB		 2133 struct tcf_exts *exts,
2134 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2135{
2136 const struct tc_action *a;
2137 bool modify_ip_header;
2138 LIST_HEAD(actions);
2139 u8 htype, ip_proto;
2140 void *headers_v;
2141 u16 ethertype;
2142 int nkeys, i;
2143
2144 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2145 ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2146
2147 /* for non-IP we only re-write MACs, so we're okay */
2148 if (ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
2149 goto out_ok;
2150
2151 modify_ip_header = false;
244cd96a
CW		 2152 tcf_exts_for_each_action(i, a, exts) {
2153 int k;
2154
bdd66ac0
OG		 2155 if (!is_tcf_pedit(a))
2156 continue;
2157
2158 nkeys = tcf_pedit_nkeys(a);
244cd96a
CW		 2159 for (k = 0; k < nkeys; k++) {
2160 htype = tcf_pedit_htype(a, k);
bdd66ac0
OG		 2161 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP4 ||
2162 htype == TCA_PEDIT_KEY_EX_HDR_TYPE_IP6) {
2163 modify_ip_header = true;
2164 break;
2165 }
2166 }
2167 }
2168
2169 ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
1ccef350
JL		 2170 if (modify_ip_header && ip_proto != IPPROTO_TCP &&
2171 ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
e98bedf5
EB		 2172 NL_SET_ERR_MSG_MOD(extack,
2173 "can't offload re-write of non TCP/UDP");
bdd66ac0
OG		 2174 pr_info("can't offload re-write of ip proto %d\n", ip_proto);
2175 return false;
2176 }
2177
2178out_ok:
2179 return true;
2180}
2181
2182static bool actions_match_supported(struct mlx5e_priv *priv,
2183 struct tcf_exts *exts,
2184 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2185 struct mlx5e_tc_flow *flow,
2186 struct netlink_ext_ack *extack)
bdd66ac0
OG		 2187{
2188 u32 actions;
2189
2190 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
2191 actions = flow->esw_attr->action;
2192 else
2193 actions = flow->nic_attr->action;
2194
7e29392e
RD		 2195 if (flow->flags & MLX5E_TC_FLOW_EGRESS &&
2196 !(actions & MLX5_FLOW_CONTEXT_ACTION_DECAP))
2197 return false;
2198
bdd66ac0 2199 if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
e98bedf5
EB		 2200 return modify_header_match_supported(&parse_attr->spec, exts,
2201 extack);
bdd66ac0
OG		 2202
2203 return true;
2204}
2205
5c65c564
OG		 2206static bool same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
2207{
2208 struct mlx5_core_dev *fmdev, *pmdev;
816f6706 2209 u64 fsystem_guid, psystem_guid;
5c65c564
OG		 2210
2211 fmdev = priv->mdev;
2212 pmdev = peer_priv->mdev;
2213
59c9d35e
AH		 2214 fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
2215 psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
5c65c564 2216
816f6706 2217 return (fsystem_guid == psystem_guid);
5c65c564
OG		 2218}
2219
5c40348c 2220static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae 2221 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2222 struct mlx5e_tc_flow *flow,
2223 struct netlink_ext_ack *extack)
e3a2b7ed 2224{
aa0cbbae 2225 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 2226 const struct tc_action *a;
22dc13c8 2227 LIST_HEAD(actions);
1cab1cd7 2228 u32 action = 0;
244cd96a 2229 int err, i;
e3a2b7ed 2230
3bcc0cec 2231 if (!tcf_exts_has_actions(exts))
e3a2b7ed
AV		 2232 return -EINVAL;
2233
3bc4b7bf 2234 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
e3a2b7ed 2235
244cd96a 2236 tcf_exts_for_each_action(i, a, exts) {
e3a2b7ed 2237 if (is_tcf_gact_shot(a)) {
1cab1cd7 2238 action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 2239 if (MLX5_CAP_FLOWTABLE(priv->mdev,
2240 flow_table_properties_nic_receive.flow_counter))
1cab1cd7 2241 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 2242 continue;
2243 }
2244
2f4fe4ca
OG		 2245 if (is_tcf_pedit(a)) {
2246 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
e98bedf5 2247 parse_attr, extack);
2f4fe4ca
OG		 2248 if (err)
2249 return err;
2250
1cab1cd7
OG		 2251 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
2252 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2f4fe4ca
OG		 2253 continue;
2254 }
2255
26c02749 2256 if (is_tcf_csum(a)) {
1cab1cd7 2257 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2258 tcf_csum_update_flags(a),
2259 extack))
26c02749
OG		 2260 continue;
2261
2262 return -EOPNOTSUPP;
2263 }
2264
5c65c564
OG		 2265 if (is_tcf_mirred_egress_redirect(a)) {
2266 struct net_device *peer_dev = tcf_mirred_dev(a);
2267
2268 if (priv->netdev->netdev_ops == peer_dev->netdev_ops &&
2269 same_hw_devs(priv, netdev_priv(peer_dev))) {
2270 parse_attr->mirred_ifindex = peer_dev->ifindex;
2271 flow->flags |= MLX5E_TC_FLOW_HAIRPIN;
1cab1cd7
OG		 2272 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2273 MLX5_FLOW_CONTEXT_ACTION_COUNT;
5c65c564 2274 } else {
e98bedf5
EB		 2275 NL_SET_ERR_MSG_MOD(extack,
2276 "device is not on same HW, can't offload");
5c65c564
OG		 2277 netdev_warn(priv->netdev, "device %s not on same HW, can't offload\n",
2278 peer_dev->name);
2279 return -EINVAL;
2280 }
2281 continue;
2282 }
2283
e3a2b7ed
AV		 2284 if (is_tcf_skbedit_mark(a)) {
2285 u32 mark = tcf_skbedit_mark(a);
2286
2287 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
e98bedf5
EB		 2288 NL_SET_ERR_MSG_MOD(extack,
2289 "Bad flow mark - only 16 bit is supported");
e3a2b7ed
AV		 2290 return -EINVAL;
2291 }
2292
3bc4b7bf 2293 attr->flow_tag = mark;
1cab1cd7 2294 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 2295 continue;
2296 }
2297
2298 return -EINVAL;
2299 }
2300
1cab1cd7 2301 attr->action = action;
e98bedf5 2302 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2303 return -EOPNOTSUPP;
2304
e3a2b7ed
AV		 2305 return 0;
2306}
2307
76f7444d
OG		 2308static inline int cmp_encap_info(struct ip_tunnel_key *a,
2309 struct ip_tunnel_key *b)
a54e20b4
HHZ		 2310{
2311 return memcmp(a, b, sizeof(*a));
2312}
2313
76f7444d 2314static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 2315{
76f7444d 2316 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 2317}
2318
2319static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
2320 struct net_device *mirred_dev,
2321 struct net_device **out_dev,
2322 struct flowi4 *fl4,
2323 struct neighbour **out_n,
6360cd62 2324 u8 *out_ttl)
a54e20b4 2325{
3e621b19 2326 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5ed99fb4 2327 struct mlx5e_rep_priv *uplink_rpriv;
a54e20b4
HHZ		 2328 struct rtable *rt;
2329 struct neighbour *n = NULL;
a54e20b4
HHZ		 2330
2331#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 2332 int ret;
2333
a54e20b4 2334 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 2335 ret = PTR_ERR_OR_ZERO(rt);
2336 if (ret)
2337 return ret;
a54e20b4
HHZ		 2338#else
2339 return -EOPNOTSUPP;
2340#endif
a4b97ab4 2341 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3e621b19
HHZ		 2342 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2343 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
5ed99fb4 2344 *out_dev = uplink_rpriv->netdev;
3e621b19
HHZ		 2345 else
2346 *out_dev = rt->dst.dev;
a54e20b4 2347
6360cd62
OG		 2348 if (!(*out_ttl))
2349 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 2350 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
2351 ip_rt_put(rt);
2352 if (!n)
2353 return -ENOMEM;
2354
2355 *out_n = n;
a54e20b4
HHZ		 2356 return 0;
2357}
2358
b1d90e6b
RL		 2359static bool is_merged_eswitch_dev(struct mlx5e_priv *priv,
2360 struct net_device *peer_netdev)
2361{
2362 struct mlx5e_priv *peer_priv;
2363
2364 peer_priv = netdev_priv(peer_netdev);
2365
2366 return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
2367 (priv->netdev->netdev_ops == peer_netdev->netdev_ops) &&
2368 same_hw_devs(priv, peer_priv) &&
2369 MLX5_VPORT_MANAGER(peer_priv->mdev) &&
2370 (peer_priv->mdev->priv.eswitch->mode == SRIOV_OFFLOADS));
2371}
2372
ce99f6b9
OG		 2373static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
2374 struct net_device *mirred_dev,
2375 struct net_device **out_dev,
2376 struct flowi6 *fl6,
2377 struct neighbour **out_n,
6360cd62 2378 u8 *out_ttl)
ce99f6b9
OG		 2379{
2380 struct neighbour *n = NULL;
2381 struct dst_entry *dst;
2382
2383#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
74bd5d56 2384 struct mlx5e_rep_priv *uplink_rpriv;
ce99f6b9
OG		 2385 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2386 int ret;
2387
08820528
PB		 2388 ret = ipv6_stub->ipv6_dst_lookup(dev_net(mirred_dev), NULL, &dst,
2389 fl6);
2390 if (ret < 0)
ce99f6b9 2391 return ret;
ce99f6b9 2392
6360cd62
OG		 2393 if (!(*out_ttl))
2394 *out_ttl = ip6_dst_hoplimit(dst);
ce99f6b9 2395
a4b97ab4 2396 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
ce99f6b9
OG		 2397 /* if the egress device isn't on the same HW e-switch, we use the uplink */
2398 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
5ed99fb4 2399 *out_dev = uplink_rpriv->netdev;
ce99f6b9
OG		 2400 else
2401 *out_dev = dst->dev;
2402#else
2403 return -EOPNOTSUPP;
2404#endif
2405
2406 n = dst_neigh_lookup(dst, &fl6->daddr);
2407 dst_release(dst);
2408 if (!n)
2409 return -ENOMEM;
2410
2411 *out_n = n;
2412 return 0;
2413}
2414
32f3671f
OG		 2415static void gen_vxlan_header_ipv4(struct net_device *out_dev,
2416 char buf[], int encap_size,
2417 unsigned char h_dest[ETH_ALEN],
f35f800d 2418 u8 tos, u8 ttl,
32f3671f
OG		 2419 __be32 daddr,
2420 __be32 saddr,
2421 __be16 udp_dst_port,
2422 __be32 vx_vni)
a54e20b4 2423{
a54e20b4
HHZ		 2424 struct ethhdr *eth = (struct ethhdr *)buf;
2425 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
2426 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
2427 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2428
2429 memset(buf, 0, encap_size);
2430
2431 ether_addr_copy(eth->h_dest, h_dest);
2432 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2433 eth->h_proto = htons(ETH_P_IP);
2434
2435 ip->daddr = daddr;
2436 ip->saddr = saddr;
2437
f35f800d 2438 ip->tos = tos;
a54e20b4
HHZ		 2439 ip->ttl = ttl;
2440 ip->protocol = IPPROTO_UDP;
2441 ip->version = 0x4;
2442 ip->ihl = 0x5;
2443
2444 udp->dest = udp_dst_port;
2445 vxh->vx_flags = VXLAN_HF_VNI;
2446 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 2447}
2448
225aabaf
OG		 2449static void gen_vxlan_header_ipv6(struct net_device *out_dev,
2450 char buf[], int encap_size,
2451 unsigned char h_dest[ETH_ALEN],
f35f800d 2452 u8 tos, u8 ttl,
225aabaf
OG		 2453 struct in6_addr *daddr,
2454 struct in6_addr *saddr,
2455 __be16 udp_dst_port,
2456 __be32 vx_vni)
ce99f6b9 2457{
ce99f6b9
OG		 2458 struct ethhdr *eth = (struct ethhdr *)buf;
2459 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
2460 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
2461 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
2462
2463 memset(buf, 0, encap_size);
2464
2465 ether_addr_copy(eth->h_dest, h_dest);
2466 ether_addr_copy(eth->h_source, out_dev->dev_addr);
2467 eth->h_proto = htons(ETH_P_IPV6);
2468
f35f800d 2469 ip6_flow_hdr(ip6h, tos, 0);
ce99f6b9
OG		 2470 /* the HW fills up ipv6 payload len */
2471 ip6h->nexthdr = IPPROTO_UDP;
2472 ip6h->hop_limit = ttl;
2473 ip6h->daddr = *daddr;
2474 ip6h->saddr = *saddr;
2475
2476 udp->dest = udp_dst_port;
2477 vxh->vx_flags = VXLAN_HF_VNI;
2478 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 2479}
2480
a54e20b4
HHZ		 2481static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
2482 struct net_device *mirred_dev,
1a8552bd 2483 struct mlx5e_encap_entry *e)
a54e20b4
HHZ		 2484{
2485 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 2486 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 2487 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2488 struct net_device *out_dev;
a42485eb 2489 struct neighbour *n = NULL;
a54e20b4 2490 struct flowi4 fl4 = {};
f35f800d 2491 u8 nud_state, tos, ttl;
a54e20b4 2492 char *encap_header;
6360cd62 2493 int err;
32f3671f
OG		 2494
2495 if (max_encap_size < ipv4_encap_size) {
2496 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2497 ipv4_encap_size, max_encap_size);
2498 return -EOPNOTSUPP;
2499 }
a54e20b4 2500
32f3671f 2501 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 2502 if (!encap_header)
2503 return -ENOMEM;
2504
2505 switch (e->tunnel_type) {
60786f09 2506 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
a54e20b4 2507 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 2508 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 2509 break;
2510 default:
2511 err = -EOPNOTSUPP;
ace74321 2512 goto free_encap;
a54e20b4 2513 }
6360cd62 2514
f35f800d
OG		 2515 tos = tun_key->tos;
2516 ttl = tun_key->ttl;
6360cd62 2517
9a941117 2518 fl4.flowi4_tos = tun_key->tos;
76f7444d 2519 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 2520 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 2521
1a8552bd 2522 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 2523 &fl4, &n, &ttl);
a54e20b4 2524 if (err)
ace74321 2525 goto free_encap;
a54e20b4 2526
232c0013
HHZ		 2527 /* used by mlx5e_detach_encap to lookup a neigh hash table
2528 * entry in the neigh hash table when a user deletes a rule
2529 */
2530 e->m_neigh.dev = n->dev;
f6dfb4c3 2531 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2532 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2533 e->out_dev = out_dev;
2534
2535 /* It's importent to add the neigh to the hash table before checking
2536 * the neigh validity state. So if we'll get a notification, in case the
2537 * neigh changes it's validity state, we would find the relevant neigh
2538 * in the hash.
2539 */
2540 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2541 if (err)
ace74321 2542 goto free_encap;
232c0013 2543
033354d5
HHZ		 2544 read_lock_bh(&n->lock);
2545 nud_state = n->nud_state;
2546 ether_addr_copy(e->h_dest, n->ha);
2547 read_unlock_bh(&n->lock);
2548
a54e20b4 2549 switch (e->tunnel_type) {
60786f09 2550 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
1a8552bd 2551 gen_vxlan_header_ipv4(out_dev, encap_header,
f35f800d 2552 ipv4_encap_size, e->h_dest, tos, ttl,
32f3671f
OG		 2553 fl4.daddr,
2554 fl4.saddr, tun_key->tp_dst,
2555 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 2556 break;
2557 default:
2558 err = -EOPNOTSUPP;
232c0013
HHZ		 2559 goto destroy_neigh_entry;
2560 }
2561 e->encap_size = ipv4_encap_size;
2562 e->encap_header = encap_header;
2563
2564 if (!(nud_state & NUD_VALID)) {
2565 neigh_event_send(n, NULL);
27902f08
WY		 2566 err = -EAGAIN;
2567 goto out;
a54e20b4
HHZ		 2568 }
2569
60786f09
MB		 2570 err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
2571 ipv4_encap_size, encap_header,
31ca3648 2572 MLX5_FLOW_NAMESPACE_FDB,
60786f09 2573 &e->encap_id);
232c0013
HHZ		 2574 if (err)
2575 goto destroy_neigh_entry;
2576
2577 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2578 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2579 neigh_release(n);
2580 return err;
2581
2582destroy_neigh_entry:
2583 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2584free_encap:
a54e20b4 2585 kfree(encap_header);
ace74321 2586out:
232c0013
HHZ		 2587 if (n)
2588 neigh_release(n);
a54e20b4
HHZ		 2589 return err;
2590}
2591
ce99f6b9
OG		 2592static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
2593 struct net_device *mirred_dev,
1a8552bd 2594 struct mlx5e_encap_entry *e)
ce99f6b9
OG		 2595{
2596 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 2597 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 2598 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 2599 struct net_device *out_dev;
ce99f6b9
OG		 2600 struct neighbour *n = NULL;
2601 struct flowi6 fl6 = {};
f35f800d 2602 u8 nud_state, tos, ttl;
ce99f6b9 2603 char *encap_header;
6360cd62 2604 int err;
ce99f6b9 2605
225aabaf
OG		 2606 if (max_encap_size < ipv6_encap_size) {
2607 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
2608 ipv6_encap_size, max_encap_size);
2609 return -EOPNOTSUPP;
2610 }
ce99f6b9 2611
225aabaf 2612 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 2613 if (!encap_header)
2614 return -ENOMEM;
2615
2616 switch (e->tunnel_type) {
60786f09 2617 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
ce99f6b9
OG		 2618 fl6.flowi6_proto = IPPROTO_UDP;
2619 fl6.fl6_dport = tun_key->tp_dst;
2620 break;
2621 default:
2622 err = -EOPNOTSUPP;
ace74321 2623 goto free_encap;
ce99f6b9
OG		 2624 }
2625
f35f800d
OG		 2626 tos = tun_key->tos;
2627 ttl = tun_key->ttl;
6360cd62 2628
ce99f6b9
OG		 2629 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
2630 fl6.daddr = tun_key->u.ipv6.dst;
2631 fl6.saddr = tun_key->u.ipv6.src;
2632
1a8552bd 2633 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG		 2634 &fl6, &n, &ttl);
2635 if (err)
ace74321 2636 goto free_encap;
ce99f6b9 2637
232c0013
HHZ		 2638 /* used by mlx5e_detach_encap to lookup a neigh hash table
2639 * entry in the neigh hash table when a user deletes a rule
2640 */
2641 e->m_neigh.dev = n->dev;
f6dfb4c3 2642 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 2643 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
2644 e->out_dev = out_dev;
2645
2646 /* It's importent to add the neigh to the hash table before checking
2647 * the neigh validity state. So if we'll get a notification, in case the
2648 * neigh changes it's validity state, we would find the relevant neigh
2649 * in the hash.
2650 */
2651 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
2652 if (err)
ace74321 2653 goto free_encap;
232c0013 2654
033354d5
HHZ		 2655 read_lock_bh(&n->lock);
2656 nud_state = n->nud_state;
2657 ether_addr_copy(e->h_dest, n->ha);
2658 read_unlock_bh(&n->lock);
2659
ce99f6b9 2660 switch (e->tunnel_type) {
60786f09 2661 case MLX5_REFORMAT_TYPE_L2_TO_VXLAN:
1a8552bd 2662 gen_vxlan_header_ipv6(out_dev, encap_header,
f35f800d 2663 ipv6_encap_size, e->h_dest, tos, ttl,
225aabaf
OG		 2664 &fl6.daddr,
2665 &fl6.saddr, tun_key->tp_dst,
2666 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 2667 break;
2668 default:
2669 err = -EOPNOTSUPP;
232c0013
HHZ		 2670 goto destroy_neigh_entry;
2671 }
2672
2673 e->encap_size = ipv6_encap_size;
2674 e->encap_header = encap_header;
2675
2676 if (!(nud_state & NUD_VALID)) {
2677 neigh_event_send(n, NULL);
27902f08
WY		 2678 err = -EAGAIN;
2679 goto out;
ce99f6b9
OG		 2680 }
2681
60786f09
MB		 2682 err = mlx5_packet_reformat_alloc(priv->mdev, e->tunnel_type,
2683 ipv6_encap_size, encap_header,
31ca3648 2684 MLX5_FLOW_NAMESPACE_FDB,
60786f09 2685 &e->encap_id);
232c0013
HHZ		 2686 if (err)
2687 goto destroy_neigh_entry;
2688
2689 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 2690 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 2691 neigh_release(n);
2692 return err;
2693
2694destroy_neigh_entry:
2695 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ace74321 2696free_encap:
ce99f6b9 2697 kfree(encap_header);
ace74321 2698out:
232c0013
HHZ		 2699 if (n)
2700 neigh_release(n);
ce99f6b9
OG		 2701 return err;
2702}
2703
a54e20b4
HHZ		 2704static int mlx5e_attach_encap(struct mlx5e_priv *priv,
2705 struct ip_tunnel_info *tun_info,
2706 struct net_device *mirred_dev,
45247bf2 2707 struct net_device **encap_dev,
e98bedf5
EB		 2708 struct mlx5e_tc_flow *flow,
2709 struct netlink_ext_ack *extack)
a54e20b4
HHZ		 2710{
2711 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2712 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2 2713 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 2714 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 2715 struct mlx5e_encap_entry *e;
45247bf2 2716 int tunnel_type, err = 0;
a54e20b4
HHZ		 2717 uintptr_t hash_key;
2718 bool found = false;
a54e20b4 2719
2fcd82e9 2720 /* udp dst port must be set */
a54e20b4 2721 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 2722 goto vxlan_encap_offload_err;
a54e20b4 2723
cd377663 2724 /* setting udp src port isn't supported */
2fcd82e9
OG		 2725 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
2726vxlan_encap_offload_err:
e98bedf5
EB		 2727 NL_SET_ERR_MSG_MOD(extack,
2728 "must set udp dst port and not set udp src port");
2fcd82e9
OG		 2729 netdev_warn(priv->netdev,
2730 "must set udp dst port and not set udp src port\n");
cd377663 2731 return -EOPNOTSUPP;
2fcd82e9 2732 }
cd377663 2733
a3e67366 2734 if (mlx5_vxlan_lookup_port(priv->mdev->vxlan, be16_to_cpu(key->tp_dst)) &&
a54e20b4 2735 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
60786f09 2736 tunnel_type = MLX5_REFORMAT_TYPE_L2_TO_VXLAN;
a54e20b4 2737 } else {
e98bedf5
EB		 2738 NL_SET_ERR_MSG_MOD(extack,
2739 "port isn't an offloaded vxlan udp dport");
2fcd82e9
OG		 2740 netdev_warn(priv->netdev,
2741 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 2742 return -EOPNOTSUPP;
2743 }
2744
76f7444d 2745 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 2746
2747 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
2748 encap_hlist, hash_key) {
76f7444d 2749 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 2750 found = true;
2751 break;
2752 }
2753 }
2754
b2812089 2755 /* must verify if encap is valid or not */
45247bf2
OG		 2756 if (found)
2757 goto attach_flow;
a54e20b4
HHZ		 2758
2759 e = kzalloc(sizeof(*e), GFP_KERNEL);
2760 if (!e)
2761 return -ENOMEM;
2762
76f7444d 2763 e->tun_info = *tun_info;
a54e20b4
HHZ		 2764 e->tunnel_type = tunnel_type;
2765 INIT_LIST_HEAD(&e->flows);
2766
ce99f6b9 2767 if (family == AF_INET)
1a8552bd 2768 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 2769 else if (family == AF_INET6)
1a8552bd 2770 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 2771
232c0013 2772 if (err && err != -EAGAIN)
a54e20b4
HHZ		 2773 goto out_err;
2774
a54e20b4
HHZ		 2775 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
2776
45247bf2
OG		 2777attach_flow:
2778 list_add(&flow->encap, &e->flows);
2779 *encap_dev = e->out_dev;
232c0013
HHZ		 2780 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
2781 attr->encap_id = e->encap_id;
b2812089
VB		 2782 else
2783 err = -EAGAIN;
45247bf2 2784
232c0013 2785 return err;
a54e20b4
HHZ		 2786
2787out_err:
2788 kfree(e);
2789 return err;
2790}
2791
1482bd3d
JL		 2792static int parse_tc_vlan_action(struct mlx5e_priv *priv,
2793 const struct tc_action *a,
2794 struct mlx5_esw_flow_attr *attr,
2795 u32 *action)
2796{
cc495188
JL		 2797 u8 vlan_idx = attr->total_vlan;
2798
2799 if (vlan_idx >= MLX5_FS_VLAN_DEPTH)
2800 return -EOPNOTSUPP;
2801
1482bd3d 2802 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
cc495188
JL		 2803 if (vlan_idx) {
2804 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2805 MLX5_FS_VLAN_DEPTH))
2806 return -EOPNOTSUPP;
2807
2808 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2;
2809 } else {
2810 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
2811 }
1482bd3d 2812 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
cc495188
JL		 2813 attr->vlan_vid[vlan_idx] = tcf_vlan_push_vid(a);
2814 attr->vlan_prio[vlan_idx] = tcf_vlan_push_prio(a);
2815 attr->vlan_proto[vlan_idx] = tcf_vlan_push_proto(a);
2816 if (!attr->vlan_proto[vlan_idx])
2817 attr->vlan_proto[vlan_idx] = htons(ETH_P_8021Q);
2818
2819 if (vlan_idx) {
2820 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev,
2821 MLX5_FS_VLAN_DEPTH))
2822 return -EOPNOTSUPP;
2823
2824 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2;
2825 } else {
2826 if (!mlx5_eswitch_vlan_actions_supported(priv->mdev, 1) &&
2827 (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q) ||
2828 tcf_vlan_push_prio(a)))
2829 return -EOPNOTSUPP;
2830
2831 *action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1482bd3d
JL		 2832 }
2833 } else { /* action is TCA_VLAN_ACT_MODIFY */
2834 return -EOPNOTSUPP;
2835 }
2836
cc495188
JL		 2837 attr->total_vlan = vlan_idx + 1;
2838
1482bd3d
JL		 2839 return 0;
2840}
2841
03a9d11e 2842static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 2843 struct mlx5e_tc_flow_parse_attr *parse_attr,
e98bedf5
EB		 2844 struct mlx5e_tc_flow *flow,
2845 struct netlink_ext_ack *extack)
03a9d11e 2846{
bf07aa73 2847 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
ecf5bb79 2848 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 2849 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 2850 struct ip_tunnel_info *info = NULL;
03a9d11e 2851 const struct tc_action *a;
22dc13c8 2852 LIST_HEAD(actions);
a54e20b4 2853 bool encap = false;
1cab1cd7 2854 u32 action = 0;
244cd96a 2855 int err, i;
03a9d11e 2856
3bcc0cec 2857 if (!tcf_exts_has_actions(exts))
03a9d11e
OG		 2858 return -EINVAL;
2859
1d447a39 2860 attr->in_rep = rpriv->rep;
10ff5359 2861 attr->in_mdev = priv->mdev;
03a9d11e 2862
244cd96a 2863 tcf_exts_for_each_action(i, a, exts) {
03a9d11e 2864 if (is_tcf_gact_shot(a)) {
1cab1cd7
OG		 2865 action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
2866 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 2867 continue;
2868 }
2869
d7e75a32
OG		 2870 if (is_tcf_pedit(a)) {
2871 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
e98bedf5 2872 parse_attr, extack);
d7e75a32
OG		 2873 if (err)
2874 return err;
2875
1cab1cd7 2876 action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
592d3651 2877 attr->mirror_count = attr->out_count;
d7e75a32
OG		 2878 continue;
2879 }
2880
26c02749 2881 if (is_tcf_csum(a)) {
1cab1cd7 2882 if (csum_offload_supported(priv, action,
e98bedf5
EB		 2883 tcf_csum_update_flags(a),
2884 extack))
26c02749
OG		 2885 continue;
2886
2887 return -EOPNOTSUPP;
2888 }
2889
592d3651 2890 if (is_tcf_mirred_egress_redirect(a) || is_tcf_mirred_egress_mirror(a)) {
03a9d11e 2891 struct mlx5e_priv *out_priv;
592d3651 2892 struct net_device *out_dev;
03a9d11e 2893
9f8a739e 2894 out_dev = tcf_mirred_dev(a);
03a9d11e 2895
592d3651 2896 if (attr->out_count >= MLX5_MAX_FLOW_FWD_VPORTS) {
e98bedf5
EB		 2897 NL_SET_ERR_MSG_MOD(extack,
2898 "can't support more output ports, can't offload forwarding");
592d3651
CM		 2899 pr_err("can't support more than %d output ports, can't offload forwarding\n",
2900 attr->out_count);
2901 return -EOPNOTSUPP;
2902 }
2903
a54e20b4 2904 if (switchdev_port_same_parent_id(priv->netdev,
b1d90e6b
RL		 2905 out_dev) ||
2906 is_merged_eswitch_dev(priv, out_dev)) {
1cab1cd7
OG		 2907 action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2908 MLX5_FLOW_CONTEXT_ACTION_COUNT;
a54e20b4 2909 out_priv = netdev_priv(out_dev);
1d447a39 2910 rpriv = out_priv->ppriv;
592d3651
CM		 2911 attr->out_rep[attr->out_count] = rpriv->rep;
2912 attr->out_mdev[attr->out_count++] = out_priv->mdev;
a54e20b4 2913 } else if (encap) {
9f8a739e 2914 parse_attr->mirred_ifindex = out_dev->ifindex;
3c37745e
OG		 2915 parse_attr->tun_info = *info;
2916 attr->parse_attr = parse_attr;
60786f09 2917 action |= MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT |
1cab1cd7
OG		 2918 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
2919 MLX5_FLOW_CONTEXT_ACTION_COUNT;
3c37745e 2920 /* attr->out_rep is resolved when we handle encap */
a54e20b4 2921 } else {
e98bedf5
EB		 2922 NL_SET_ERR_MSG_MOD(extack,
2923 "devices are not on same switch HW, can't offload forwarding");
03a9d11e
OG		 2924 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
2925 priv->netdev->name, out_dev->name);
2926 return -EINVAL;
2927 }
a54e20b4
HHZ		 2928 continue;
2929 }
03a9d11e 2930
a54e20b4
HHZ		 2931 if (is_tcf_tunnel_set(a)) {
2932 info = tcf_tunnel_info(a);
2933 if (info)
2934 encap = true;
2935 else
2936 return -EOPNOTSUPP;
592d3651 2937 attr->mirror_count = attr->out_count;
03a9d11e
OG		 2938 continue;
2939 }
2940
8b32580d 2941 if (is_tcf_vlan(a)) {
1482bd3d
JL		 2942 err = parse_tc_vlan_action(priv, a, attr, &action);
2943
2944 if (err)
2945 return err;
2946
592d3651 2947 attr->mirror_count = attr->out_count;
8b32580d
OG		 2948 continue;
2949 }
2950
bbd00f7e 2951 if (is_tcf_tunnel_release(a)) {
1cab1cd7 2952 action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
bbd00f7e
HHZ		 2953 continue;
2954 }
2955
bf07aa73
PB		 2956 if (is_tcf_gact_goto_chain(a)) {
2957 u32 dest_chain = tcf_gact_goto_chain_index(a);
2958 u32 max_chain = mlx5_eswitch_get_chain_range(esw);
2959
2960 if (dest_chain <= attr->chain) {
2961 NL_SET_ERR_MSG(extack, "Goto earlier chain isn't supported");
2962 return -EOPNOTSUPP;
2963 }
2964 if (dest_chain > max_chain) {
2965 NL_SET_ERR_MSG(extack, "Requested destination chain is out of supported range");
2966 return -EOPNOTSUPP;
2967 }
e88afe75 2968 action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
bf07aa73
PB		 2969 attr->dest_chain = dest_chain;
2970
2971 continue;
2972 }
2973
03a9d11e
OG		 2974 return -EINVAL;
2975 }
bdd66ac0 2976
1cab1cd7 2977 attr->action = action;
e98bedf5 2978 if (!actions_match_supported(priv, exts, parse_attr, flow, extack))
bdd66ac0
OG		 2979 return -EOPNOTSUPP;
2980
e88afe75
OG		 2981 if (attr->dest_chain) {
2982 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
2983 NL_SET_ERR_MSG(extack, "Mirroring goto chain rules isn't supported");
2984 return -EOPNOTSUPP;
2985 }
2986 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
2987 }
2988
1392f44b 2989 if (attr->mirror_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
e98bedf5
EB		 2990 NL_SET_ERR_MSG_MOD(extack,
2991 "current firmware doesn't support split rule for port mirroring");
592d3651
CM		 2992 netdev_warn_once(priv->netdev, "current firmware doesn't support split rule for port mirroring\n");
2993 return -EOPNOTSUPP;
2994 }
2995
31c8eba5 2996 return 0;
03a9d11e
OG		 2997}
2998
5dbe906f 2999static void get_flags(int flags, u16 *flow_flags)
60bd4af8 3000{
5dbe906f 3001 u16 __flow_flags = 0;
60bd4af8
OG		 3002
3003 if (flags & MLX5E_TC_INGRESS)
3004 __flow_flags |= MLX5E_TC_FLOW_INGRESS;
3005 if (flags & MLX5E_TC_EGRESS)
3006 __flow_flags |= MLX5E_TC_FLOW_EGRESS;
3007
3008 *flow_flags = __flow_flags;
3009}
3010
05866c82
OG		 3011static const struct rhashtable_params tc_ht_params = {
3012 .head_offset = offsetof(struct mlx5e_tc_flow, node),
3013 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
3014 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
3015 .automatic_shrinking = true,
3016};
3017
3018static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv)
3019{
655dc3d2
OG		 3020 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
3021 struct mlx5e_rep_priv *uplink_rpriv;
3022
3023 if (MLX5_VPORT_MANAGER(priv->mdev) && esw->mode == SRIOV_OFFLOADS) {
3024 uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
3025 return &uplink_rpriv->tc_ht;
3026 } else
3027 return &priv->fs.tc.ht;
05866c82
OG		 3028}
3029
a88780a9
RD		 3030static int
3031mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
5dbe906f 3032 struct tc_cls_flower_offload *f, u16 flow_flags,
a88780a9
RD		 3033 struct mlx5e_tc_flow_parse_attr **__parse_attr,
3034 struct mlx5e_tc_flow **__flow)
e3a2b7ed 3035{
17091853 3036 struct mlx5e_tc_flow_parse_attr *parse_attr;
3bc4b7bf 3037 struct mlx5e_tc_flow *flow;
a88780a9 3038 int err;
e3a2b7ed 3039
65ba8fb7 3040 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 3041 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 3042 if (!parse_attr || !flow) {
e3a2b7ed
AV		 3043 err = -ENOMEM;
3044 goto err_free;
3045 }
3046
3047 flow->cookie = f->cookie;
65ba8fb7 3048 flow->flags = flow_flags;
655dc3d2 3049 flow->priv = priv;
e3a2b7ed 3050
17091853 3051 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
a88780a9 3052 if (err)
e3a2b7ed
AV		 3053 goto err_free;
3054
a88780a9
RD		 3055 *__flow = flow;
3056 *__parse_attr = parse_attr;
3057
3058 return 0;
3059
3060err_free:
3061 kfree(flow);
3062 kvfree(parse_attr);
3063 return err;
3064}
3065
3066static int
3067mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
3068 struct tc_cls_flower_offload *f,
5dbe906f 3069 u16 flow_flags,
a88780a9
RD		 3070 struct mlx5e_tc_flow **__flow)
3071{
3072 struct netlink_ext_ack *extack = f->common.extack;
3073 struct mlx5e_tc_flow_parse_attr *parse_attr;
3074 struct mlx5e_tc_flow *flow;
3075 int attr_size, err;
e3a2b7ed 3076
a88780a9
RD		 3077 flow_flags |= MLX5E_TC_FLOW_ESWITCH;
3078 attr_size = sizeof(struct mlx5_esw_flow_attr);
3079 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3080 &parse_attr, &flow);
3081 if (err)
3082 goto out;
3083
bf07aa73
PB		 3084 flow->esw_attr->chain = f->common.chain_index;
3085 flow->esw_attr->prio = TC_H_MAJ(f->common.prio) >> 16;
a88780a9
RD		 3086 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow, extack);
3087 if (err)
3088 goto err_free;
3089
3090 err = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow, extack);
5dbe906f 3091 if (err)
c83954ab 3092 goto err_free;
e3a2b7ed 3093
a88780a9 3094 if (!(flow->esw_attr->action &
60786f09 3095 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT))
af1607c3
JL		 3096 kvfree(parse_attr);
3097
a88780a9 3098 *__flow = flow;
5c40348c 3099
a88780a9
RD		 3100 return 0;
3101
3102err_free:
3103 kfree(flow);
3104 kvfree(parse_attr);
3105out:
232c0013 3106 return err;
a88780a9
RD		 3107}
3108
3109static int
3110mlx5e_add_nic_flow(struct mlx5e_priv *priv,
3111 struct tc_cls_flower_offload *f,
5dbe906f 3112 u16 flow_flags,
a88780a9
RD		 3113 struct mlx5e_tc_flow **__flow)
3114{
3115 struct netlink_ext_ack *extack = f->common.extack;
3116 struct mlx5e_tc_flow_parse_attr *parse_attr;
3117 struct mlx5e_tc_flow *flow;
3118 int attr_size, err;
3119
bf07aa73
PB		 3120 /* multi-chain not supported for NIC rules */
3121 if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
3122 return -EOPNOTSUPP;
3123
a88780a9
RD		 3124 flow_flags |= MLX5E_TC_FLOW_NIC;
3125 attr_size = sizeof(struct mlx5_nic_flow_attr);
3126 err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
3127 &parse_attr, &flow);
3128 if (err)
3129 goto out;
3130
3131 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow, extack);
3132 if (err)
3133 goto err_free;
3134
3135 err = mlx5e_tc_add_nic_flow(priv, parse_attr, flow, extack);
3136 if (err)
3137 goto err_free;
3138
3139 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
3140 kvfree(parse_attr);
3141 *__flow = flow;
3142
3143 return 0;
e3a2b7ed 3144
e3a2b7ed 3145err_free:
a88780a9 3146 kfree(flow);
17091853 3147 kvfree(parse_attr);
a88780a9
RD		 3148out:
3149 return err;
3150}
3151
3152static int
3153mlx5e_tc_add_flow(struct mlx5e_priv *priv,
3154 struct tc_cls_flower_offload *f,
3155 int flags,
3156 struct mlx5e_tc_flow **flow)
3157{
3158 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5dbe906f 3159 u16 flow_flags;
a88780a9
RD		 3160 int err;
3161
3162 get_flags(flags, &flow_flags);
3163
bf07aa73
PB		 3164 if (!tc_can_offload_extack(priv->netdev, f->common.extack))
3165 return -EOPNOTSUPP;
3166
a88780a9
RD		 3167 if (esw && esw->mode == SRIOV_OFFLOADS)
3168 err = mlx5e_add_fdb_flow(priv, f, flow_flags, flow);
3169 else
3170 err = mlx5e_add_nic_flow(priv, f, flow_flags, flow);
3171
3172 return err;
3173}
3174
3175int mlx5e_configure_flower(struct mlx5e_priv *priv,
3176 struct tc_cls_flower_offload *f, int flags)
3177{
3178 struct netlink_ext_ack *extack = f->common.extack;
3179 struct rhashtable *tc_ht = get_tc_ht(priv);
3180 struct mlx5e_tc_flow *flow;
3181 int err = 0;
3182
3183 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
3184 if (flow) {
3185 NL_SET_ERR_MSG_MOD(extack,
3186 "flow cookie already exists, ignoring");
3187 netdev_warn_once(priv->netdev,
3188 "flow cookie %lx already exists, ignoring\n",
3189 f->cookie);
3190 goto out;
3191 }
3192
3193 err = mlx5e_tc_add_flow(priv, f, flags, &flow);
3194 if (err)
3195 goto out;
3196
3197 err = rhashtable_insert_fast(tc_ht, &flow->node, tc_ht_params);
3198 if (err)
3199 goto err_free;
3200
3201 return 0;
3202
3203err_free:
3204 mlx5e_tc_del_flow(priv, flow);
232c0013 3205 kfree(flow);
a88780a9 3206out:
e3a2b7ed
AV		 3207 return err;
3208}
3209
8f8ae895
OG		 3210#define DIRECTION_MASK (MLX5E_TC_INGRESS | MLX5E_TC_EGRESS)
3211#define FLOW_DIRECTION_MASK (MLX5E_TC_FLOW_INGRESS | MLX5E_TC_FLOW_EGRESS)
3212
3213static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
3214{
3215 if ((flow->flags & FLOW_DIRECTION_MASK) == (flags & DIRECTION_MASK))
3216 return true;
3217
3218 return false;
3219}
3220
e3a2b7ed 3221int mlx5e_delete_flower(struct mlx5e_priv *priv,
60bd4af8 3222 struct tc_cls_flower_offload *f, int flags)
e3a2b7ed 3223{
05866c82 3224 struct rhashtable *tc_ht = get_tc_ht(priv);
e3a2b7ed 3225 struct mlx5e_tc_flow *flow;
e3a2b7ed 3226
05866c82 3227 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3228 if (!flow || !same_flow_direction(flow, flags))
e3a2b7ed
AV		 3229 return -EINVAL;
3230
05866c82 3231 rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
e3a2b7ed 3232
961e8979 3233 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 3234
3235 kfree(flow);
3236
3237 return 0;
3238}
3239
aad7e08d 3240int mlx5e_stats_flower(struct mlx5e_priv *priv,
60bd4af8 3241 struct tc_cls_flower_offload *f, int flags)
aad7e08d 3242{
05866c82 3243 struct rhashtable *tc_ht = get_tc_ht(priv);
aad7e08d 3244 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 3245 struct mlx5_fc *counter;
3246 u64 bytes;
3247 u64 packets;
3248 u64 lastuse;
3249
05866c82 3250 flow = rhashtable_lookup_fast(tc_ht, &f->cookie, tc_ht_params);
8f8ae895 3251 if (!flow || !same_flow_direction(flow, flags))
aad7e08d
AV		 3252 return -EINVAL;
3253
0b67a38f
HHZ		 3254 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
3255 return 0;
3256
b8aee822 3257 counter = mlx5e_tc_get_counter(flow);
aad7e08d
AV		 3258 if (!counter)
3259 return 0;
3260
3261 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
3262
d897a638 3263 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 3264
aad7e08d
AV		 3265 return 0;
3266}
3267
4d8fcf21
AH		 3268static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
3269 struct mlx5e_priv *peer_priv)
3270{
3271 struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
3272 struct mlx5e_hairpin_entry *hpe;
3273 u16 peer_vhca_id;
3274 int bkt;
3275
3276 if (!same_hw_devs(priv, peer_priv))
3277 return;
3278
3279 peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
3280
3281 hash_for_each(priv->fs.tc.hairpin_tbl, bkt, hpe, hairpin_hlist) {
3282 if (hpe->peer_vhca_id == peer_vhca_id)
3283 hpe->hp->pair->peer_gone = true;
3284 }
3285}
3286
3287static int mlx5e_tc_netdev_event(struct notifier_block *this,
3288 unsigned long event, void *ptr)
3289{
3290 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
3291 struct mlx5e_flow_steering *fs;
3292 struct mlx5e_priv *peer_priv;
3293 struct mlx5e_tc_table *tc;
3294 struct mlx5e_priv *priv;
3295
3296 if (ndev->netdev_ops != &mlx5e_netdev_ops ||
3297 event != NETDEV_UNREGISTER ||
3298 ndev->reg_state == NETREG_REGISTERED)
3299 return NOTIFY_DONE;
3300
3301 tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
3302 fs = container_of(tc, struct mlx5e_flow_steering, tc);
3303 priv = container_of(fs, struct mlx5e_priv, fs);
3304 peer_priv = netdev_priv(ndev);
3305 if (priv == peer_priv ||
3306 !(priv->netdev->features & NETIF_F_HW_TC))
3307 return NOTIFY_DONE;
3308
3309 mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
3310
3311 return NOTIFY_DONE;
3312}
3313
655dc3d2 3314int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
e8f887ac 3315{
acff797c 3316 struct mlx5e_tc_table *tc = &priv->fs.tc;
4d8fcf21 3317 int err;
e8f887ac 3318
11c9c548 3319 hash_init(tc->mod_hdr_tbl);
5c65c564 3320 hash_init(tc->hairpin_tbl);
11c9c548 3321
4d8fcf21
AH		 3322 err = rhashtable_init(&tc->ht, &tc_ht_params);
3323 if (err)
3324 return err;
3325
3326 tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
3327 if (register_netdevice_notifier(&tc->netdevice_nb)) {
3328 tc->netdevice_nb.notifier_call = NULL;
3329 mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
3330 }
3331
3332 return err;
e8f887ac
AV		 3333}
3334
3335static void _mlx5e_tc_del_flow(void *ptr, void *arg)
3336{
3337 struct mlx5e_tc_flow *flow = ptr;
655dc3d2 3338 struct mlx5e_priv *priv = flow->priv;
e8f887ac 3339
961e8979 3340 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 3341 kfree(flow);
3342}
3343
655dc3d2 3344void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
e8f887ac 3345{
acff797c 3346 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 3347
4d8fcf21
AH		 3348 if (tc->netdevice_nb.notifier_call)
3349 unregister_netdevice_notifier(&tc->netdevice_nb);
3350
655dc3d2 3351 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
e8f887ac 3352
acff797c
MG		 3353 if (!IS_ERR_OR_NULL(tc->t)) {
3354 mlx5_destroy_flow_table(tc->t);
3355 tc->t = NULL;
e8f887ac
AV		 3356 }
3357}
655dc3d2
OG		 3358
3359int mlx5e_tc_esw_init(struct rhashtable *tc_ht)
3360{
3361 return rhashtable_init(tc_ht, &tc_ht_params);
3362}
3363
3364void mlx5e_tc_esw_cleanup(struct rhashtable *tc_ht)
3365{
3366 rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
3367}
01252a27
OG		 3368
3369int mlx5e_tc_num_filters(struct mlx5e_priv *priv)
3370{
3371 struct rhashtable *tc_ht = get_tc_ht(priv);
3372
3373 return atomic_read(&tc_ht->nelems);
3374}
Linux 6.x block layer and io_uring tree(s)