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net: dsa: b53: Fix statistics readings
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
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225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
38438f7c 52static bool enable_qos = true;
51f5f0ee 53module_param(enable_qos, bool, 0444);
38438f7c 54MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)");
51f5f0ee 55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
17d5ceb6 59 u64 val; \
225c7b1f
RD		 60 switch (sizeof (dest)) { \
61 case 1: (dest) = *(u8 *) __p; break; \
62 case 2: (dest) = be16_to_cpup(__p); break; \
63 case 4: (dest) = be32_to_cpup(__p); break; \
17d5ceb6
DA		 64 case 8: val = get_unaligned((u64 *)__p); \
65 (dest) = be64_to_cpu(val); break; \
225c7b1f
RD		 66 default: __buggy_use_of_MLX4_GET(); \
67 } \
68 } while (0)
69
70#define MLX4_PUT(dest, source, offset) \
71 do { \
72 void *__d = ((char *) (dest) + (offset)); \
73 switch (sizeof(source)) { \
74 case 1: *(u8 *) __d = (source); break; \
75 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
76 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
77 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
78 default: __buggy_use_of_MLX4_PUT(); \
79 } \
80 } while (0)
81
52eafc68 82static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 83{
84 static const char *fname[] = {
85 [ 0] = "RC transport",
86 [ 1] = "UC transport",
87 [ 2] = "UD transport",
ea98054f 88 [ 3] = "XRC transport",
225c7b1f
RD		 89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
4d531aa8 93 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 94 [15] = "Big LSO headers",
225c7b1f
RD		 95 [16] = "MW support",
96 [17] = "APM support",
97 [18] = "Atomic ops support",
98 [19] = "Raw multicast support",
99 [20] = "Address vector port checking support",
100 [21] = "UD multicast support",
ccf86321
OG		 101 [30] = "IBoE support",
102 [32] = "Unicast loopback support",
f3a9d1f2 103 [34] = "FCS header control",
cb2147a9
OG		 104 [37] = "Wake On LAN (port1) support",
105 [38] = "Wake On LAN (port2) support",
ccf86321
OG		 106 [40] = "UDP RSS support",
107 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 108 [42] = "Multicast VEP steering support",
109 [48] = "Counters support",
802f42a8 110 [52] = "RSS IP fragments support",
540b3a39 111 [53] = "Port ETS Scheduler support",
4d531aa8 112 [55] = "Port link type sensing support",
00f5ce99 113 [59] = "Port management change event support",
08ff3235
OG		 114 [61] = "64 byte EQE support",
115 [62] = "64 byte CQE support",
225c7b1f
RD		 116 };
117 int i;
118
119 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 120 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 121 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 122 mlx4_dbg(dev, " %s\n", fname[i]);
123}
124
b3416f44
SP		 125static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
126{
127 static const char * const fname[] = {
128 [0] = "RSS support",
129 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 130 [2] = "RSS XOR Hash Function support",
56cb4567 131 [3] = "Device managed flow steering support",
d998735f 132 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 133 [5] = "Time stamping support",
134 [6] = "VST (control vlan insertion/stripping) support",
b01978ca 135 [7] = "FSM (MAC anti-spoofing) support",
7ffdf726 136 [8] = "Dynamic QP updates support",
56cb4567 137 [9] = "Device managed flow steering IPoIB support",
114840c3 138 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
77507aa2
IS		 139 [11] = "MAD DEMUX (Secure-Host) support",
140 [12] = "Large cache line (>64B) CQE stride support",
adbc7ac5 141 [13] = "Large cache line (>64B) EQE stride support",
a53e3e8c 142 [14] = "Ethernet protocol control support",
d475c95b 143 [15] = "Ethernet Backplane autoneg support",
7ae0e400 144 [16] = "CONFIG DEV support",
de966c59 145 [17] = "Asymmetric EQs support",
7d077cd3 146 [18] = "More than 80 VFs support",
be6a6b43 147 [19] = "Performance optimized for limited rule configuration flow steering support",
59e14e32 148 [20] = "Recoverable error events support",
d237baa1 149 [21] = "Port Remap support",
fc31e256 150 [22] = "QCN support",
0b131561 151 [23] = "QP rate limiting support",
d019fcb2
IS		 152 [24] = "Ethernet Flow control statistics support",
153 [25] = "Granular QoS per VF support",
3742cc65 154 [26] = "Port ETS Scheduler support",
51af33cf 155 [27] = "Port beacon support",
78500b8c 156 [28] = "RX-ALL support",
77fc29c4 157 [29] = "802.1ad offload support",
9a892835
MG		 158 [31] = "Modifying loopback source checks using UPDATE_QP support",
159 [32] = "Loopback source checks support",
0e451e88
MV		 160 [33] = "RoCEv2 support",
161 [34] = "DMFS Sniffer support (UC & MC)"
b3416f44
SP		 162 };
163 int i;
164
165 for (i = 0; i < ARRAY_SIZE(fname); ++i)
166 if (fname[i] && (flags & (1LL << i)))
167 mlx4_dbg(dev, " %s\n", fname[i]);
168}
169
2d928651
VS		 170int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
171{
172 struct mlx4_cmd_mailbox *mailbox;
173 u32 *inbox;
174 int err = 0;
175
176#define MOD_STAT_CFG_IN_SIZE 0x100
177
178#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
179#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
180
181 mailbox = mlx4_alloc_cmd_mailbox(dev);
182 if (IS_ERR(mailbox))
183 return PTR_ERR(mailbox);
184 inbox = mailbox->buf;
185
2d928651
VS		 186 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
187 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
188
189 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 190 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 191
192 mlx4_free_cmd_mailbox(dev, mailbox);
193 return err;
194}
195
e8c4265b
MB		 196int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave)
197{
198 struct mlx4_cmd_mailbox *mailbox;
199 u32 *outbox;
200 u8 in_modifier;
201 u8 field;
202 u16 field16;
203 int err;
204
205#define QUERY_FUNC_BUS_OFFSET 0x00
206#define QUERY_FUNC_DEVICE_OFFSET 0x01
207#define QUERY_FUNC_FUNCTION_OFFSET 0x01
208#define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
209#define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
210#define QUERY_FUNC_MAX_EQ_OFFSET 0x06
211#define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
212
213 mailbox = mlx4_alloc_cmd_mailbox(dev);
214 if (IS_ERR(mailbox))
215 return PTR_ERR(mailbox);
216 outbox = mailbox->buf;
217
218 in_modifier = slave;
e8c4265b
MB		 219
220 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0,
221 MLX4_CMD_QUERY_FUNC,
222 MLX4_CMD_TIME_CLASS_A,
223 MLX4_CMD_NATIVE);
224 if (err)
225 goto out;
226
227 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
228 func->bus = field & 0xf;
229 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
230 func->device = field & 0xf1;
231 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
232 func->function = field & 0x7;
233 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
234 func->physical_function = field & 0xf;
235 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
236 func->rsvd_eqs = field16 & 0xffff;
237 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
238 func->max_eq = field16 & 0xffff;
239 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
240 func->rsvd_uars = field & 0x0f;
241
242 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
243 func->bus, func->device, func->function, func->physical_function,
244 func->max_eq, func->rsvd_eqs, func->rsvd_uars);
245
246out:
247 mlx4_free_cmd_mailbox(dev, mailbox);
248 return err;
249}
250
5cc914f1
MA		 251int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
252 struct mlx4_vhcr *vhcr,
253 struct mlx4_cmd_mailbox *inbox,
254 struct mlx4_cmd_mailbox *outbox,
255 struct mlx4_cmd_info *cmd)
256{
5a0d0a61 257 struct mlx4_priv *priv = mlx4_priv(dev);
99ec41d0
JM		 258 u8 field, port;
259 u32 size, proxy_qp, qkey;
5cc914f1 260 int err = 0;
7ae0e400 261 struct mlx4_func func;
5cc914f1
MA		 262
263#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
264#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 265#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 266#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 267#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
268#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
269#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
270#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
271#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
272#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 273#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 274#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
f0ce0615 275#define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48
5cc914f1 276
eb456a68
JM		 277#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
278#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
279#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
280#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
281#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
282#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
283
ddae0349
EE		 284#define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c
285
105c320f
JM		 286#define QUERY_FUNC_CAP_FMR_FLAG 0x80
287#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
288#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 289#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
f0ce0615 290#define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08
ddae0349
EE		 291#define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04
292
293#define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31)
d57febe1 294#define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30)
105c320f
JM		 295
296/* when opcode modifier = 1 */
5cc914f1 297#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
99ec41d0 298#define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
73e74ab4
HHZ		 299#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
300#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 301
47605df9
JM		 302#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
303#define QUERY_FUNC_CAP_QP0_PROXY 0x14
304#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
305#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
8e1a28e8 306#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
47605df9 307
73e74ab4
HHZ		 308#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
309#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
eb17711b 310#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
99ec41d0 311#define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
105c320f 312
73e74ab4 313#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
7ae0e400 314#define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
77fc29c4 315#define QUERY_FUNC_CAP_PHV_BIT 0x40
105c320f 316
5cc914f1 317 if (vhcr->op_modifier == 1) {
449fc488
MB		 318 struct mlx4_active_ports actv_ports =
319 mlx4_get_active_ports(dev, slave);
320 int converted_port = mlx4_slave_convert_port(
321 dev, slave, vhcr->in_modifier);
322
323 if (converted_port < 0)
324 return -EINVAL;
325
326 vhcr->in_modifier = converted_port;
449fc488
MB		 327 /* phys-port = logical-port */
328 field = vhcr->in_modifier -
329 find_first_bit(actv_ports.ports, dev->caps.num_ports);
47605df9
JM		 330 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
331
99ec41d0
JM		 332 port = vhcr->in_modifier;
333 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
334
335 /* Set nic_info bit to mark new fields support */
336 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
337
338 if (mlx4_vf_smi_enabled(dev, slave, port) &&
339 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
340 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
341 MLX4_PUT(outbox->buf, qkey,
342 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
343 }
344 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
345
47605df9 346 /* size is now the QP number */
99ec41d0 347 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
47605df9
JM		 348 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
349
350 size += 2;
351 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
352
99ec41d0
JM		 353 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
354 proxy_qp += 2;
355 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
47605df9 356
8e1a28e8
HHZ		 357 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
358 QUERY_FUNC_CAP_PHYS_PORT_ID);
359
77fc29c4
HHZ		 360 if (dev->caps.phv_bit[port]) {
361 field = QUERY_FUNC_CAP_PHV_BIT;
362 MLX4_PUT(outbox->buf, field,
363 QUERY_FUNC_CAP_FLAGS0_OFFSET);
364 }
365
5cc914f1 366 } else if (vhcr->op_modifier == 0) {
449fc488
MB		 367 struct mlx4_active_ports actv_ports =
368 mlx4_get_active_ports(dev, slave);
f0ce0615
JM		 369 /* enable rdma and ethernet interfaces, new quota locations,
370 * and reserved lkey
371 */
eb456a68 372 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
f0ce0615
JM		 373 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX |
374 QUERY_FUNC_CAP_FLAG_RESD_LKEY);
5cc914f1
MA		 375 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
376
449fc488
MB		 377 field = min(
378 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
379 dev->caps.num_ports);
5cc914f1
MA		 380 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
381
08ff3235 382 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 383 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
384
105c320f
JM		 385 field = 0; /* protected FMR support not available as yet */
386 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
387
5a0d0a61 388 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 389 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 390 size = dev->caps.num_qps;
391 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 392
5a0d0a61 393 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 394 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 395 size = dev->caps.num_srqs;
396 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 397
5a0d0a61 398 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 399 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 400 size = dev->caps.num_cqs;
401 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1 402
7ae0e400
MB		 403 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
404 mlx4_QUERY_FUNC(dev, &func, slave)) {
405 size = vhcr->in_modifier &
406 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
407 dev->caps.num_eqs :
408 rounddown_pow_of_two(dev->caps.num_eqs);
409 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
410 size = dev->caps.reserved_eqs;
411 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
412 } else {
413 size = vhcr->in_modifier &
414 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
415 func.max_eq :
416 rounddown_pow_of_two(func.max_eq);
417 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
418 size = func.rsvd_eqs;
419 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
420 }
5cc914f1 421
5a0d0a61 422 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 423 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 424 size = dev->caps.num_mpts;
425 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 426
5a0d0a61 427 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 428 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 429 size = dev->caps.num_mtts;
430 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 431
432 size = dev->caps.num_mgms + dev->caps.num_amgms;
433 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 434 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1 435
d57febe1
MB		 436 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG |
437 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG;
ddae0349 438 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
f0ce0615
JM		 439
440 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00);
441 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
5cc914f1
MA		 442 } else
443 err = -EINVAL;
444
445 return err;
446}
447
225c6c8c 448int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
47605df9 449 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 450{
451 struct mlx4_cmd_mailbox *mailbox;
452 u32 *outbox;
47605df9 453 u8 field, op_modifier;
99ec41d0 454 u32 size, qkey;
eb456a68 455 int err = 0, quotas = 0;
7ae0e400 456 u32 in_modifier;
5cc914f1 457
47605df9 458 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
7ae0e400
MB		 459 in_modifier = op_modifier ? gen_or_port :
460 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS;
5cc914f1
MA		 461
462 mailbox = mlx4_alloc_cmd_mailbox(dev);
463 if (IS_ERR(mailbox))
464 return PTR_ERR(mailbox);
465
7ae0e400 466 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier,
47605df9 467 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 468 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
469 if (err)
470 goto out;
471
472 outbox = mailbox->buf;
473
47605df9
JM		 474 if (!op_modifier) {
475 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
476 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
477 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
478 err = -EPROTONOSUPPORT;
479 goto out;
480 }
481 func_cap->flags = field;
eb456a68 482 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 483
47605df9
JM		 484 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
485 func_cap->num_ports = field;
5cc914f1 486
47605df9
JM		 487 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
488 func_cap->pf_context_behaviour = size;
5cc914f1 489
eb456a68
JM		 490 if (quotas) {
491 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
492 func_cap->qp_quota = size & 0xFFFFFF;
493
494 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
495 func_cap->srq_quota = size & 0xFFFFFF;
496
497 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
498 func_cap->cq_quota = size & 0xFFFFFF;
499
500 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
501 func_cap->mpt_quota = size & 0xFFFFFF;
502
503 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
504 func_cap->mtt_quota = size & 0xFFFFFF;
505
506 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
507 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 508
eb456a68
JM		 509 } else {
510 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
511 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 512
eb456a68
JM		 513 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
514 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 515
eb456a68
JM		 516 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
517 func_cap->cq_quota = size & 0xFFFFFF;
518
519 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
520 func_cap->mpt_quota = size & 0xFFFFFF;
521
522 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
523 func_cap->mtt_quota = size & 0xFFFFFF;
524
525 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
526 func_cap->mcg_quota = size & 0xFFFFFF;
527 }
47605df9
JM		 528 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
529 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 530
47605df9
JM		 531 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
532 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 533
f0ce0615
JM		 534 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) {
535 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
536 func_cap->reserved_lkey = size;
537 } else {
538 func_cap->reserved_lkey = 0;
539 }
540
ddae0349
EE		 541 func_cap->extra_flags = 0;
542
543 /* Mailbox data from 0x6c and onward should only be treated if
544 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags
545 */
546 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) {
547 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
548 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG)
549 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP;
d57febe1
MB		 550 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG)
551 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP;
ddae0349
EE		 552 }
553
47605df9
JM		 554 goto out;
555 }
5cc914f1 556
47605df9
JM		 557 /* logical port query */
558 if (gen_or_port > dev->caps.num_ports) {
559 err = -EINVAL;
560 goto out;
561 }
5cc914f1 562
eb17711b 563 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
47605df9 564 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
bc82878b 565 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
47605df9
JM		 566 mlx4_err(dev, "VLAN is enforced on this port\n");
567 err = -EPROTONOSUPPORT;
5cc914f1 568 goto out;
47605df9 569 }
5cc914f1 570
eb17711b 571 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 572 mlx4_err(dev, "Force mac is enabled on this port\n");
573 err = -EPROTONOSUPPORT;
574 goto out;
5cc914f1 575 }
47605df9 576 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 577 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
578 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
1a91de28 579 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
47605df9
JM		 580 err = -EPROTONOSUPPORT;
581 goto out;
582 }
583 }
5cc914f1 584
47605df9
JM		 585 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
586 func_cap->physical_port = field;
587 if (func_cap->physical_port != gen_or_port) {
588 err = -ENOSYS;
589 goto out;
5cc914f1
MA		 590 }
591
99ec41d0
JM		 592 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
593 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
594 func_cap->qp0_qkey = qkey;
595 } else {
596 func_cap->qp0_qkey = 0;
597 }
598
47605df9
JM		 599 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
600 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
601
602 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
603 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
604
605 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
606 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
607
608 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
609 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
610
8e1a28e8
HHZ		 611 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
612 MLX4_GET(func_cap->phys_port_id, outbox,
613 QUERY_FUNC_CAP_PHYS_PORT_ID);
614
77fc29c4
HHZ		 615 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
616 func_cap->flags |= (field & QUERY_FUNC_CAP_PHV_BIT);
617
5cc914f1
MA		 618 /* All other resources are allocated by the master, but we still report
619 * 'num' and 'reserved' capabilities as follows:
620 * - num remains the maximum resource index
621 * - 'num - reserved' is the total available objects of a resource, but
622 * resource indices may be less than 'reserved'
623 * TODO: set per-resource quotas */
624
625out:
626 mlx4_free_cmd_mailbox(dev, mailbox);
627
628 return err;
629}
630
d8ae9141
MS		 631static void disable_unsupported_roce_caps(void *buf);
632
225c7b1f
RD		 633int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
634{
635 struct mlx4_cmd_mailbox *mailbox;
636 u32 *outbox;
637 u8 field;
ccf86321 638 u32 field32, flags, ext_flags;
225c7b1f
RD		 639 u16 size;
640 u16 stat_rate;
641 int err;
5ae2a7a8 642 int i;
225c7b1f
RD		 643
644#define QUERY_DEV_CAP_OUT_SIZE 0x100
645#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
646#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
647#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
648#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
649#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
650#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
651#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
652#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
653#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
654#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
655#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
656#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
657#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
658#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
659#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
660#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
661#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
662#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
7ae0e400 663#define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
225c7b1f
RD		 664#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
665#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
666#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 667#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 668#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 669#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
670#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
51af33cf 671#define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34
225c7b1f
RD		 672#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
673#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
674#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 675#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 676#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
677#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 678#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 679#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 680#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 681#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
682#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
683#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
684#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
685#define QUERY_DEV_CAP_BF_OFFSET 0x4c
686#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
687#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
688#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
689#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
690#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
691#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
692#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
693#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
694#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
695#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
696#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
697#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 698#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
699#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 700#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
0b131561 701#define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70
3f7fb021 702#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
4de65803 703#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
0ff1fb65
HHZ		 704#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
705#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
77507aa2 706#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
d237baa1 707#define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b
225c7b1f
RD		 708#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
709#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
710#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
711#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
712#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
713#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
714#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
715#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
716#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
717#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 718#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
d475c95b 719#define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
77fc29c4 720#define QUERY_DEV_CAP_PHV_EN_OFFSET 0x96
225c7b1f
RD		 721#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
722#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
a53e3e8c 723#define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
955154fa 724#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
7ffdf726 725#define QUERY_DEV_CAP_VXLAN 0x9e
114840c3 726#define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
7d077cd3
MB		 727#define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8
728#define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac
fc31e256
OG		 729#define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc
730#define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0
731#define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2
732
225c7b1f 733
b3416f44 734 dev_cap->flags2 = 0;
225c7b1f
RD		 735 mailbox = mlx4_alloc_cmd_mailbox(dev);
736 if (IS_ERR(mailbox))
737 return PTR_ERR(mailbox);
738 outbox = mailbox->buf;
739
740 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 741 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 742 if (err)
743 goto out;
744
d8ae9141
MS		 745 if (mlx4_is_mfunc(dev))
746 disable_unsupported_roce_caps(outbox);
225c7b1f
RD		 747 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
748 dev_cap->reserved_qps = 1 << (field & 0xf);
749 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
750 dev_cap->max_qps = 1 << (field & 0x1f);
751 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
752 dev_cap->reserved_srqs = 1 << (field >> 4);
753 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
754 dev_cap->max_srqs = 1 << (field & 0x1f);
755 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
756 dev_cap->max_cq_sz = 1 << field;
757 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
758 dev_cap->reserved_cqs = 1 << (field & 0xf);
759 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
760 dev_cap->max_cqs = 1 << (field & 0x1f);
761 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
762 dev_cap->max_mpts = 1 << (field & 0x3f);
763 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
7c68dd43 764 dev_cap->reserved_eqs = 1 << (field & 0xf);
225c7b1f 765 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 766 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 767 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
768 dev_cap->reserved_mtts = 1 << (field >> 4);
769 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
770 dev_cap->max_mrw_sz = 1 << field;
771 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
772 dev_cap->reserved_mrws = 1 << (field & 0xf);
773 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
774 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
7ae0e400
MB		 775 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
776 dev_cap->num_sys_eqs = size & 0xfff;
225c7b1f
RD		 777 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
778 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
779 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
780 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 781 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
782 field &= 0x1f;
783 if (!field)
784 dev_cap->max_gso_sz = 0;
785 else
786 dev_cap->max_gso_sz = 1 << field;
787
b3416f44
SP		 788 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
789 if (field & 0x20)
790 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
791 if (field & 0x10)
792 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
793 field &= 0xf;
794 if (field) {
795 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
796 dev_cap->max_rss_tbl_sz = 1 << field;
797 } else
798 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 799 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
800 dev_cap->max_rdma_global = 1 << (field & 0x3f);
801 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
802 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 803 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 804 dev_cap->num_ports = field & 0xf;
149983af 805 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
fab9adfb 806 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0b131561
MB		 807 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET);
808 if (field & 0x10)
809 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN;
0ff1fb65
HHZ		 810 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
811 if (field & 0x80)
812 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
813 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
0e451e88
MV		 814 if (field & 0x20)
815 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER;
51af33cf
IS		 816 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
817 if (field & 0x80)
818 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON;
4de65803
MB		 819 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
820 if (field & 0x80)
821 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
0ff1fb65
HHZ		 822 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
823 dev_cap->fs_max_num_qp_per_entry = field;
d237baa1
SM		 824 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
825 if (field & 0x1)
826 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN;
225c7b1f
RD		 827 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
828 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 829 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
830 if (field & 0x80)
831 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 832 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 833 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 834 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 835 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
836 dev_cap->reserved_uars = field >> 4;
837 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
838 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
839 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
840 dev_cap->min_page_sz = 1 << field;
841
842 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
843 if (field & 0x80) {
844 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
845 dev_cap->bf_reg_size = 1 << (field & 0x1f);
846 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 847 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 848 field = 3;
225c7b1f 849 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
225c7b1f
RD		 850 } else {
851 dev_cap->bf_reg_size = 0;
225c7b1f
RD		 852 }
853
854 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
855 dev_cap->max_sq_sg = field;
856 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
857 dev_cap->max_sq_desc_sz = size;
858
859 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
860 dev_cap->max_qp_per_mcg = 1 << field;
861 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
862 dev_cap->reserved_mgms = field & 0xf;
863 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
864 dev_cap->max_mcgs = 1 << field;
865 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
866 dev_cap->reserved_pds = field >> 4;
867 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
868 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 869 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
870 dev_cap->reserved_xrcds = field >> 4;
426dd00d 871 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 872 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 873
874 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
875 dev_cap->rdmarc_entry_sz = size;
876 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
877 dev_cap->qpc_entry_sz = size;
878 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
879 dev_cap->aux_entry_sz = size;
880 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
881 dev_cap->altc_entry_sz = size;
882 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
883 dev_cap->eqc_entry_sz = size;
884 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
885 dev_cap->cqc_entry_sz = size;
886 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
887 dev_cap->srq_entry_sz = size;
888 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
889 dev_cap->cmpt_entry_sz = size;
890 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
891 dev_cap->mtt_entry_sz = size;
892 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
893 dev_cap->dmpt_entry_sz = size;
894
895 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
896 dev_cap->max_srq_sz = 1 << field;
897 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
898 dev_cap->max_qp_sz = 1 << field;
899 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
900 dev_cap->resize_srq = field & 1;
901 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
902 dev_cap->max_rq_sg = field;
903 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
904 dev_cap->max_rq_desc_sz = size;
77507aa2 905 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
d019fcb2
IS		 906 if (field & (1 << 4))
907 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP;
adbc7ac5
SM		 908 if (field & (1 << 5))
909 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
77507aa2
IS		 910 if (field & (1 << 6))
911 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
912 if (field & (1 << 7))
913 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
225c7b1f
RD		 914 MLX4_GET(dev_cap->bmme_flags, outbox,
915 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
d8ae9141
MS		 916 if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2)
917 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2;
59e14e32
MS		 918 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP)
919 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;
d475c95b
MB		 920 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
921 if (field & 0x20)
922 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
78500b8c
MM		 923 if (field & (1 << 2))
924 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
77fc29c4
HHZ		 925 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET);
926 if (field & 0x80)
927 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN;
928 if (field & 0x40)
929 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN;
930
225c7b1f
RD		 931 MLX4_GET(dev_cap->reserved_lkey, outbox,
932 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
a53e3e8c
SM		 933 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
934 if (field32 & (1 << 0))
935 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
be6a6b43
JM		 936 if (field32 & (1 << 7))
937 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;
955154fa
MB		 938 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
939 if (field & 1<<6)
5930e8d0 940 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
7ffdf726
OG		 941 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
942 if (field & 1<<3)
943 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
3742cc65
IS		 944 if (field & (1 << 5))
945 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
225c7b1f
RD		 946 MLX4_GET(dev_cap->max_icm_sz, outbox,
947 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 948 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
949 MLX4_GET(dev_cap->max_counters, outbox,
950 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 951
114840c3
JM		 952 MLX4_GET(field32, outbox,
953 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
954 if (field32 & (1 << 0))
955 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
956
7d077cd3
MB		 957 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox,
958 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET);
959 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK;
960 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox,
961 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET);
962 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK;
963
fc31e256
OG		 964 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
965 dev_cap->rl_caps.num_rates = size;
966 if (dev_cap->rl_caps.num_rates) {
967 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT;
968 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET);
969 dev_cap->rl_caps.max_val = size & 0xfff;
970 dev_cap->rl_caps.max_unit = size >> 14;
971 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET);
972 dev_cap->rl_caps.min_val = size & 0xfff;
973 dev_cap->rl_caps.min_unit = size >> 14;
974 }
975
3f7fb021 976 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 977 if (field32 & (1 << 16))
978 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
9a892835
MG		 979 if (field32 & (1 << 18))
980 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB;
981 if (field32 & (1 << 19))
982 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK;
3f7fb021
RE		 983 if (field32 & (1 << 26))
984 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 985 if (field32 & (1 << 20))
986 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
de966c59
MB		 987 if (field32 & (1 << 21))
988 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
3f7fb021 989
431df8c7
MB		 990 for (i = 1; i <= dev_cap->num_ports; i++) {
991 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);
992 if (err)
993 goto out;
5ae2a7a8
RD		 994 }
995
225c7b1f
RD		 996 /*
997 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
998 * we can't use any EQs whose doorbell falls on that page,
999 * even if the EQ itself isn't reserved.
1000 */
7ae0e400
MB		 1001 if (dev_cap->num_sys_eqs == 0)
1002 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
1003 dev_cap->reserved_eqs);
1004 else
1005 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
225c7b1f 1006
c78e25ed
OG		 1007out:
1008 mlx4_free_cmd_mailbox(dev, mailbox);
1009 return err;
1010}
1011
1012void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
1013{
1014 if (dev_cap->bf_reg_size > 0)
1015 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
1016 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
1017 else
1018 mlx4_dbg(dev, "BlueFlame not available\n");
1019
1020 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
1021 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 1022 mlx4_dbg(dev, "Max ICM size %lld MB\n",
1023 (unsigned long long) dev_cap->max_icm_sz >> 20);
1024 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1025 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
1026 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1027 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
1028 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1029 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
7ae0e400
MB		 1030 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
1031 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
1032 dev_cap->eqc_entry_sz);
225c7b1f
RD		 1033 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
1034 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
1035 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1036 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
1037 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
1038 dev_cap->max_pds, dev_cap->reserved_mgms);
1039 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1040 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
1041 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
431df8c7
MB		 1042 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,
1043 dev_cap->port_cap[1].max_port_width);
225c7b1f
RD		 1044 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
1045 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
1046 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
1047 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 1048 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 1049 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 1050 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
7d077cd3
MB		 1051 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n",
1052 dev_cap->dmfs_high_rate_qpn_base);
1053 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n",
1054 dev_cap->dmfs_high_rate_qpn_range);
fc31e256
OG		 1055
1056 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) {
1057 struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps;
1058
1059 mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n",
1060 rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val,
1061 rl_caps->min_unit, rl_caps->min_val);
1062 }
1063
225c7b1f 1064 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 1065 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 1066}
1067
431df8c7
MB		 1068int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap)
1069{
1070 struct mlx4_cmd_mailbox *mailbox;
1071 u32 *outbox;
1072 u8 field;
1073 u32 field32;
1074 int err;
1075
1076 mailbox = mlx4_alloc_cmd_mailbox(dev);
1077 if (IS_ERR(mailbox))
1078 return PTR_ERR(mailbox);
1079 outbox = mailbox->buf;
1080
1081 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1082 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1083 MLX4_CMD_TIME_CLASS_A,
1084 MLX4_CMD_NATIVE);
1085
1086 if (err)
1087 goto out;
1088
1089 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
1090 port_cap->max_vl = field >> 4;
1091 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
1092 port_cap->ib_mtu = field >> 4;
1093 port_cap->max_port_width = field & 0xf;
1094 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
1095 port_cap->max_gids = 1 << (field & 0xf);
1096 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
1097 port_cap->max_pkeys = 1 << (field & 0xf);
1098 } else {
1099#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
1100#define QUERY_PORT_MTU_OFFSET 0x01
1101#define QUERY_PORT_ETH_MTU_OFFSET 0x02
1102#define QUERY_PORT_WIDTH_OFFSET 0x06
1103#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
1104#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
1105#define QUERY_PORT_MAX_VL_OFFSET 0x0b
1106#define QUERY_PORT_MAC_OFFSET 0x10
1107#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
1108#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
1109#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
1110
1111 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT,
1112 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1113 if (err)
1114 goto out;
1115
1116 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
e34305c8 1117 port_cap->link_state = (field & 0x80) >> 7;
431df8c7
MB		 1118 port_cap->supported_port_types = field & 3;
1119 port_cap->suggested_type = (field >> 3) & 1;
1120 port_cap->default_sense = (field >> 4) & 1;
7d077cd3 1121 port_cap->dmfs_optimized_state = (field >> 5) & 1;
431df8c7
MB		 1122 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
1123 port_cap->ib_mtu = field & 0xf;
1124 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
1125 port_cap->max_port_width = field & 0xf;
1126 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
1127 port_cap->max_gids = 1 << (field >> 4);
1128 port_cap->max_pkeys = 1 << (field & 0xf);
1129 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
1130 port_cap->max_vl = field & 0xf;
1131 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
1132 port_cap->log_max_macs = field & 0xf;
1133 port_cap->log_max_vlans = field >> 4;
1134 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);
1135 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);
1136 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
1137 port_cap->trans_type = field32 >> 24;
1138 port_cap->vendor_oui = field32 & 0xffffff;
1139 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);
1140 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);
1141 }
1142
1143out:
1144 mlx4_free_cmd_mailbox(dev, mailbox);
1145 return err;
1146}
1147
0b131561 1148#define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28)
383677da
OG		 1149#define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
1150#define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
1151#define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
1152
b91cb3eb
JM		 1153int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1154 struct mlx4_vhcr *vhcr,
1155 struct mlx4_cmd_mailbox *inbox,
1156 struct mlx4_cmd_mailbox *outbox,
1157 struct mlx4_cmd_info *cmd)
1158{
2a4fae14 1159 u64 flags;
b91cb3eb
JM		 1160 int err = 0;
1161 u8 field;
fc31e256 1162 u16 field16;
383677da 1163 u32 bmme_flags, field32;
449fc488
MB		 1164 int real_port;
1165 int slave_port;
1166 int first_port;
1167 struct mlx4_active_ports actv_ports;
b91cb3eb
JM		 1168
1169 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1170 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1171 if (err)
1172 return err;
1173
d8ae9141 1174 disable_unsupported_roce_caps(outbox->buf);
cc1ade94
SM		 1175 /* add port mng change event capability and disable mw type 1
1176 * unconditionally to slaves
1177 */
2a4fae14
JM		 1178 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1179 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 1180 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
449fc488
MB		 1181 actv_ports = mlx4_get_active_ports(dev, slave);
1182 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
1183 for (slave_port = 0, real_port = first_port;
1184 real_port < first_port +
1185 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
1186 ++real_port, ++slave_port) {
1187 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
1188 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
1189 else
1190 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1191 }
1192 for (; slave_port < dev->caps.num_ports; ++slave_port)
1193 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
802f42a8
IS		 1194
1195 /* Not exposing RSS IP fragments to guests */
1196 flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG;
2a4fae14
JM		 1197 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1198
449fc488
MB		 1199 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1200 field &= ~0x0F;
1201 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1202 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1203
30b40c31
AV		 1204 /* For guests, disable timestamp */
1205 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1206 field &= 0x7f;
1207 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1208
3742cc65 1209 /* For guests, disable vxlan tunneling and QoS support */
57352ef4 1210 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
3742cc65 1211 field &= 0xd7;
7ffdf726
OG		 1212 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1213
51af33cf
IS		 1214 /* For guests, disable port BEACON */
1215 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1216 field &= 0x7f;
1217 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1218
b91cb3eb
JM		 1219 /* For guests, report Blueflame disabled */
1220 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1221 field &= 0x7f;
1222 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1223
59e14e32 1224 /* For guests, disable mw type 2 and port remap*/
57352ef4 1225 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
cc1ade94 1226 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
59e14e32 1227 bmme_flags &= ~MLX4_FLAG_PORT_REMAP;
cc1ade94
SM		 1228 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1229
0081c8f3
JM		 1230 /* turn off device-managed steering capability if not enabled */
1231 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1232 MLX4_GET(field, outbox->buf,
1233 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1234 field &= 0x7f;
1235 MLX4_PUT(outbox->buf, field,
1236 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1237 }
4de65803
MB		 1238
1239 /* turn off ipoib managed steering for guests */
57352ef4 1240 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
4de65803
MB		 1241 field &= ~0x80;
1242 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1243
383677da
OG		 1244 /* turn off host side virt features (VST, FSM, etc) for guests */
1245 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1246 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS |
0b131561 1247 DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS);
383677da
OG		 1248 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1249
d237baa1
SM		 1250 /* turn off QCN for guests */
1251 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1252 field &= 0xfe;
1253 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1254
fc31e256
OG		 1255 /* turn off QP max-rate limiting for guests */
1256 field16 = 0;
1257 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
1258
d019fcb2
IS		 1259 /* turn off QoS per VF support for guests */
1260 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1261 field &= 0xef;
1262 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1263
78500b8c
MM		 1264 /* turn off ignore FCS feature for guests */
1265 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1266 field &= 0xfb;
1267 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1268
b91cb3eb
JM		 1269 return 0;
1270}
1271
d8ae9141
MS		 1272static void disable_unsupported_roce_caps(void *buf)
1273{
1274 u32 flags;
1275
1276 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1277 flags &= ~(1UL << 31);
1278 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1279 MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1280 flags &= ~(1UL << 24);
1281 MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1282 MLX4_GET(flags, buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1283 flags &= ~(MLX4_FLAG_ROCE_V1_V2);
1284 MLX4_PUT(buf, flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1285}
1286
5cc914f1
MA		 1287int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1288 struct mlx4_vhcr *vhcr,
1289 struct mlx4_cmd_mailbox *inbox,
1290 struct mlx4_cmd_mailbox *outbox,
1291 struct mlx4_cmd_info *cmd)
1292{
0eb62b93 1293 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 1294 u64 def_mac;
1295 u8 port_type;
6634961c 1296 u16 short_field;
5cc914f1 1297 int err;
948e306d 1298 int admin_link_state;
449fc488
MB		 1299 int port = mlx4_slave_convert_port(dev, slave,
1300 vhcr->in_modifier & 0xFF);
5cc914f1 1301
105c320f 1302#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 1303#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 1304#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1305#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 1306
449fc488
MB		 1307 if (port < 0)
1308 return -EINVAL;
1309
a7401b9c
JM		 1310 /* Protect against untrusted guests: enforce that this is the
1311 * QUERY_PORT general query.
1312 */
1313 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
1314 return -EINVAL;
1315
1316 vhcr->in_modifier = port;
449fc488 1317
5cc914f1
MA		 1318 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1319 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1320 MLX4_CMD_NATIVE);
1321
1322 if (!err && dev->caps.function != slave) {
0508ad64 1323 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 1324 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1325
1326 /* get port type - currently only eth is enabled */
1327 MLX4_GET(port_type, outbox->buf,
1328 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1329
105c320f
JM		 1330 /* No link sensing allowed */
1331 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1332 /* set port type to currently operating port type */
1333 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 1334
948e306d
RE		 1335 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1336 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1337 port_type |= MLX4_PORT_LINK_UP_MASK;
1338 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1339 port_type &= ~MLX4_PORT_LINK_UP_MASK;
e34305c8
OG		 1340 else if (IFLA_VF_LINK_STATE_AUTO == admin_link_state && mlx4_is_bonded(dev)) {
1341 int other_port = (port == 1) ? 2 : 1;
1342 struct mlx4_port_cap port_cap;
1343
1344 err = mlx4_QUERY_PORT(dev, other_port, &port_cap);
1345 if (err)
1346 goto out;
1347 port_type |= (port_cap.link_state << 7);
1348 }
948e306d 1349
5cc914f1
MA		 1350 MLX4_PUT(outbox->buf, port_type,
1351 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c 1352
b6ffaeff 1353 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
449fc488 1354 short_field = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 1355 else
1356 short_field = 1; /* slave max gids */
6634961c
JM		 1357 MLX4_PUT(outbox->buf, short_field,
1358 QUERY_PORT_CUR_MAX_GID_OFFSET);
1359
1360 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1361 MLX4_PUT(outbox->buf, short_field,
1362 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1 1363 }
e34305c8 1364out:
5cc914f1
MA		 1365 return err;
1366}
1367
6634961c
JM		 1368int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1369 int *gid_tbl_len, int *pkey_tbl_len)
1370{
1371 struct mlx4_cmd_mailbox *mailbox;
1372 u32 *outbox;
1373 u16 field;
1374 int err;
1375
1376 mailbox = mlx4_alloc_cmd_mailbox(dev);
1377 if (IS_ERR(mailbox))
1378 return PTR_ERR(mailbox);
1379
1380 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1381 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1382 MLX4_CMD_WRAPPED);
1383 if (err)
1384 goto out;
1385
1386 outbox = mailbox->buf;
1387
1388 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1389 *gid_tbl_len = field;
1390
1391 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1392 *pkey_tbl_len = field;
1393
1394out:
1395 mlx4_free_cmd_mailbox(dev, mailbox);
1396 return err;
1397}
1398EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1399
225c7b1f
RD		 1400int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1401{
1402 struct mlx4_cmd_mailbox *mailbox;
1403 struct mlx4_icm_iter iter;
1404 __be64 *pages;
1405 int lg;
1406 int nent = 0;
1407 int i;
1408 int err = 0;
1409 int ts = 0, tc = 0;
1410
1411 mailbox = mlx4_alloc_cmd_mailbox(dev);
1412 if (IS_ERR(mailbox))
1413 return PTR_ERR(mailbox);
225c7b1f
RD		 1414 pages = mailbox->buf;
1415
1416 for (mlx4_icm_first(icm, &iter);
1417 !mlx4_icm_last(&iter);
1418 mlx4_icm_next(&iter)) {
1419 /*
1420 * We have to pass pages that are aligned to their
1421 * size, so find the least significant 1 in the
1422 * address or size and use that as our log2 size.
1423 */
1424 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1425 if (lg < MLX4_ICM_PAGE_SHIFT) {
1a91de28
JP		 1426 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1427 MLX4_ICM_PAGE_SIZE,
1428 (unsigned long long) mlx4_icm_addr(&iter),
1429 mlx4_icm_size(&iter));
225c7b1f
RD		 1430 err = -EINVAL;
1431 goto out;
1432 }
1433
1434 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1435 if (virt != -1) {
1436 pages[nent * 2] = cpu_to_be64(virt);
1437 virt += 1 << lg;
1438 }
1439
1440 pages[nent * 2 + 1] =
1441 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1442 (lg - MLX4_ICM_PAGE_SHIFT));
1443 ts += 1 << (lg - 10);
1444 ++tc;
1445
1446 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1447 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 1448 MLX4_CMD_TIME_CLASS_B,
1449 MLX4_CMD_NATIVE);
225c7b1f
RD		 1450 if (err)
1451 goto out;
1452 nent = 0;
1453 }
1454 }
1455 }
1456
1457 if (nent)
f9baff50
JM		 1458 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1459 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1460 if (err)
1461 goto out;
1462
1463 switch (op) {
1464 case MLX4_CMD_MAP_FA:
1a91de28 1465 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
225c7b1f
RD		 1466 break;
1467 case MLX4_CMD_MAP_ICM_AUX:
1a91de28 1468 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
225c7b1f
RD		 1469 break;
1470 case MLX4_CMD_MAP_ICM:
1a91de28
JP		 1471 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1472 tc, ts, (unsigned long long) virt - (ts << 10));
225c7b1f
RD		 1473 break;
1474 }
1475
1476out:
1477 mlx4_free_cmd_mailbox(dev, mailbox);
1478 return err;
1479}
1480
1481int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1482{
1483 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1484}
1485
1486int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1487{
f9baff50
JM		 1488 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1489 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1490}
1491
1492
1493int mlx4_RUN_FW(struct mlx4_dev *dev)
1494{
f9baff50
JM		 1495 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1496 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1497}
1498
1499int mlx4_QUERY_FW(struct mlx4_dev *dev)
1500{
1501 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1502 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1503 struct mlx4_cmd_mailbox *mailbox;
1504 u32 *outbox;
1505 int err = 0;
1506 u64 fw_ver;
fe40900f 1507 u16 cmd_if_rev;
225c7b1f
RD		 1508 u8 lg;
1509
1510#define QUERY_FW_OUT_SIZE 0x100
1511#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1512#define QUERY_FW_PPF_ID 0x09
fe40900f 1513#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1514#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1515#define QUERY_FW_ERR_START_OFFSET 0x30
1516#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1517#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1518
1519#define QUERY_FW_SIZE_OFFSET 0x00
1520#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1521#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1522
5cc914f1
MA		 1523#define QUERY_FW_COMM_BASE_OFFSET 0x40
1524#define QUERY_FW_COMM_BAR_OFFSET 0x48
1525
ddd8a6c1
EE		 1526#define QUERY_FW_CLOCK_OFFSET 0x50
1527#define QUERY_FW_CLOCK_BAR 0x58
1528
225c7b1f
RD		 1529 mailbox = mlx4_alloc_cmd_mailbox(dev);
1530 if (IS_ERR(mailbox))
1531 return PTR_ERR(mailbox);
1532 outbox = mailbox->buf;
1533
1534 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1535 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1536 if (err)
1537 goto out;
1538
1539 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1540 /*
3e1db334 1541 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1542 * version, so swap here.
1543 */
1544 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1545 ((fw_ver & 0xffff0000ull) >> 16) |
1546 ((fw_ver & 0x0000ffffull) << 16);
1547
752a50ca
JM		 1548 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1549 dev->caps.function = lg;
1550
b91cb3eb
JM		 1551 if (mlx4_is_slave(dev))
1552 goto out;
1553
5cc914f1 1554
fe40900f 1555 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1556 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1557 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1a91de28 1558 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
fe40900f
RD		 1559 cmd_if_rev);
1560 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1561 (int) (dev->caps.fw_ver >> 32),
1562 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1563 (int) dev->caps.fw_ver & 0xffff);
1a91de28 1564 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
5ae2a7a8 1565 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1566 err = -ENODEV;
1567 goto out;
1568 }
1569
5ae2a7a8
RD		 1570 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1571 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1572
225c7b1f
RD		 1573 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1574 cmd->max_cmds = 1 << lg;
1575
fe40900f 1576 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1577 (int) (dev->caps.fw_ver >> 32),
1578 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1579 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1580 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1581
1582 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1583 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1584 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1585 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1586
1587 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1588 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1589
1590 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1591 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1592 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1593 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1594
5cc914f1
MA		 1595 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1596 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1597 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1598 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1599 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1600 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1601
ddd8a6c1
EE		 1602 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1603 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1604 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1605 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1606 fw->clock_bar, fw->clock_offset);
1607
225c7b1f
RD		 1608 /*
1609 * Round up number of system pages needed in case
1610 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1611 */
1612 fw->fw_pages =
1613 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1614 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1615
1616 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1617 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1618
1619out:
1620 mlx4_free_cmd_mailbox(dev, mailbox);
1621 return err;
1622}
1623
b91cb3eb
JM		 1624int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1625 struct mlx4_vhcr *vhcr,
1626 struct mlx4_cmd_mailbox *inbox,
1627 struct mlx4_cmd_mailbox *outbox,
1628 struct mlx4_cmd_info *cmd)
1629{
1630 u8 *outbuf;
1631 int err;
1632
1633 outbuf = outbox->buf;
1634 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1635 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1636 if (err)
1637 return err;
1638
752a50ca
JM		 1639 /* for slaves, set pci PPF ID to invalid and zero out everything
1640 * else except FW version */
b91cb3eb
JM		 1641 outbuf[0] = outbuf[1] = 0;
1642 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1643 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1644
b91cb3eb
JM		 1645 return 0;
1646}
1647
225c7b1f
RD		 1648static void get_board_id(void *vsd, char *board_id)
1649{
1650 int i;
1651
1652#define VSD_OFFSET_SIG1 0x00
1653#define VSD_OFFSET_SIG2 0xde
1654#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1655#define VSD_OFFSET_TS_BOARD_ID 0x20
1656
1657#define VSD_SIGNATURE_TOPSPIN 0x5ad
1658
1659 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1660
1661 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1662 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1663 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1664 } else {
1665 /*
1666 * The board ID is a string but the firmware byte
1667 * swaps each 4-byte word before passing it back to
1668 * us. Therefore we need to swab it before printing.
1669 */
17d5ceb6
DA		 1670 u32 *bid_u32 = (u32 *)board_id;
1671
1672 for (i = 0; i < 4; ++i) {
1673 u32 *addr;
1674 u32 val;
1675
1676 addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4);
1677 val = get_unaligned(addr);
1678 val = swab32(val);
1679 put_unaligned(val, &bid_u32[i]);
1680 }
225c7b1f
RD		 1681 }
1682}
1683
1684int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1685{
1686 struct mlx4_cmd_mailbox *mailbox;
1687 u32 *outbox;
1688 int err;
1689
1690#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1691#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1692#define QUERY_ADAPTER_VSD_OFFSET 0x20
1693
1694 mailbox = mlx4_alloc_cmd_mailbox(dev);
1695 if (IS_ERR(mailbox))
1696 return PTR_ERR(mailbox);
1697 outbox = mailbox->buf;
1698
1699 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1700 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1701 if (err)
1702 goto out;
1703
225c7b1f
RD		 1704 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1705
1706 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1707 adapter->board_id);
1708
1709out:
1710 mlx4_free_cmd_mailbox(dev, mailbox);
1711 return err;
1712}
1713
1714int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1715{
1716 struct mlx4_cmd_mailbox *mailbox;
1717 __be32 *inbox;
1718 int err;
7d077cd3
MB		 1719 static const u8 a0_dmfs_hw_steering[] = {
1720 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0,
1721 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1,
1722 [MLX4_STEERING_DMFS_A0_STATIC] = 2,
1723 [MLX4_STEERING_DMFS_A0_DISABLE] = 3
1724 };
225c7b1f
RD		 1725
1726#define INIT_HCA_IN_SIZE 0x200
1727#define INIT_HCA_VERSION_OFFSET 0x000
1728#define INIT_HCA_VERSION 2
7ffdf726 1729#define INIT_HCA_VXLAN_OFFSET 0x0c
c57e20dc 1730#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f 1731#define INIT_HCA_FLAGS_OFFSET 0x014
be6a6b43 1732#define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018
225c7b1f
RD		 1733#define INIT_HCA_QPC_OFFSET 0x020
1734#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1735#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1736#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1737#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1738#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1739#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1740#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
77507aa2 1741#define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
225c7b1f
RD		 1742#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1743#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1744#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1745#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
7ae0e400 1746#define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
225c7b1f
RD		 1747#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1748#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1749#define INIT_HCA_MCAST_OFFSET 0x0c0
1750#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1751#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1752#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1753#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1754#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1755#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1756#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1757#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1758#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
7d077cd3 1759#define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18)
0ff1fb65
HHZ		 1760#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1761#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1762#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1763#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1764#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1765#define INIT_HCA_TPT_OFFSET 0x0f0
1766#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1767#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1768#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1769#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1770#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1771#define INIT_HCA_UAR_OFFSET 0x120
1772#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1773#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1774
1775 mailbox = mlx4_alloc_cmd_mailbox(dev);
1776 if (IS_ERR(mailbox))
1777 return PTR_ERR(mailbox);
1778 inbox = mailbox->buf;
1779
225c7b1f
RD		 1780 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1781
c57e20dc
EC		 1782 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1783 (ilog2(cache_line_size()) - 4) << 5;
1784
225c7b1f
RD		 1785#if defined(__LITTLE_ENDIAN)
1786 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1787#elif defined(__BIG_ENDIAN)
1788 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1789#else
1790#error Host endianness not defined
1791#endif
1792 /* Check port for UD address vector: */
1793 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1794
8ff095ec
EC		 1795 /* Enable IPoIB checksumming if we can: */
1796 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1797 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1798
51f5f0ee 1799 /* Enable QoS support if module parameter set */
38438f7c 1800 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos)
51f5f0ee
JM		 1801 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1802
f2a3f6a3
OG		 1803 /* enable counters */
1804 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1805 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1806
802f42a8
IS		 1807 /* Enable RSS spread to fragmented IP packets when supported */
1808 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG)
1809 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13);
1810
08ff3235
OG		 1811 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1812 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1813 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1814 dev->caps.eqe_size = 64;
1815 dev->caps.eqe_factor = 1;
1816 } else {
1817 dev->caps.eqe_size = 32;
1818 dev->caps.eqe_factor = 0;
1819 }
1820
1821 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1822 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1823 dev->caps.cqe_size = 64;
77507aa2 1824 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1825 } else {
1826 dev->caps.cqe_size = 32;
1827 }
1828
77507aa2
IS		 1829 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1830 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1831 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1832 dev->caps.eqe_size = cache_line_size();
1833 dev->caps.cqe_size = cache_line_size();
1834 dev->caps.eqe_factor = 0;
1835 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1836 (ilog2(dev->caps.eqe_size) - 5)),
1837 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1838
1839 /* User still need to know to support CQE > 32B */
1840 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1841 }
1842
be6a6b43
JM		 1843 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
1844 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31);
1845
225c7b1f
RD		 1846 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1847
1848 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1849 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1850 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1851 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1852 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1853 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1854 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1855 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1856 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1857 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1858 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
225c7b1f
RD		 1859 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1860 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1861
0ff1fb65
HHZ		 1862 /* steering attributes */
1863 if (dev->caps.steering_mode ==
1864 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1865 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1866 cpu_to_be32(1 <<
1867 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1868
1869 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1870 MLX4_PUT(inbox, param->log_mc_entry_sz,
1871 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1872 MLX4_PUT(inbox, param->log_mc_table_sz,
1873 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1874 /* Enable Ethernet flow steering
1875 * with udp unicast and tcp unicast
1876 */
7d077cd3
MB		 1877 if (dev->caps.dmfs_high_steer_mode !=
1878 MLX4_STEERING_DMFS_A0_STATIC)
1879 MLX4_PUT(inbox,
1880 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1881 INIT_HCA_FS_ETH_BITS_OFFSET);
0ff1fb65
HHZ		 1882 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1883 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1884 /* Enable IPoIB flow steering
1885 * with udp unicast and tcp unicast
1886 */
23537b73 1887 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1888 INIT_HCA_FS_IB_BITS_OFFSET);
1889 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1890 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
7d077cd3
MB		 1891
1892 if (dev->caps.dmfs_high_steer_mode !=
1893 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1894 MLX4_PUT(inbox,
1895 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode]
1896 << 6)),
1897 INIT_HCA_FS_A0_OFFSET);
0ff1fb65
HHZ		 1898 } else {
1899 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1900 MLX4_PUT(inbox, param->log_mc_entry_sz,
1901 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1902 MLX4_PUT(inbox, param->log_mc_hash_sz,
1903 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1904 MLX4_PUT(inbox, param->log_mc_table_sz,
1905 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1906 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1907 MLX4_PUT(inbox, (u8) (1 << 3),
1908 INIT_HCA_UC_STEERING_OFFSET);
1909 }
225c7b1f
RD		 1910
1911 /* TPT attributes */
1912
1913 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1914 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1915 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1916 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1917 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1918
1919 /* UAR attributes */
1920
ab9c17a0 1921 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1922 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1923
7ffdf726
OG		 1924 /* set parser VXLAN attributes */
1925 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1926 u8 parser_params = 0;
1927 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1928 }
1929
5a031086
JM		 1930 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA,
1931 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
225c7b1f
RD		 1932
1933 if (err)
1934 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1935
1936 mlx4_free_cmd_mailbox(dev, mailbox);
1937 return err;
1938}
1939
ab9c17a0
JM		 1940int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1941 struct mlx4_init_hca_param *param)
1942{
1943 struct mlx4_cmd_mailbox *mailbox;
1944 __be32 *outbox;
7b8157be 1945 u32 dword_field;
ab9c17a0 1946 int err;
08ff3235 1947 u8 byte_field;
7d077cd3
MB		 1948 static const u8 a0_dmfs_query_hw_steering[] = {
1949 [0] = MLX4_STEERING_DMFS_A0_DEFAULT,
1950 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC,
1951 [2] = MLX4_STEERING_DMFS_A0_STATIC,
1952 [3] = MLX4_STEERING_DMFS_A0_DISABLE
1953 };
ab9c17a0
JM		 1954
1955#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1956#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1957
1958 mailbox = mlx4_alloc_cmd_mailbox(dev);
1959 if (IS_ERR(mailbox))
1960 return PTR_ERR(mailbox);
1961 outbox = mailbox->buf;
1962
1963 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1964 MLX4_CMD_QUERY_HCA,
1965 MLX4_CMD_TIME_CLASS_B,
1966 !mlx4_is_slave(dev));
1967 if (err)
1968 goto out;
1969
1970 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1971 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1972
1973 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1974
1975 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1976 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1977 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1978 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1979 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1980 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1981 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1982 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1983 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1984 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1985 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
ab9c17a0
JM		 1986 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1987 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1988
7b8157be
JM		 1989 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1990 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1991 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1992 } else {
1993 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1994 if (byte_field & 0x8)
1995 param->steering_mode = MLX4_STEERING_MODE_B0;
1996 else
1997 param->steering_mode = MLX4_STEERING_MODE_A0;
1998 }
802f42a8
IS		 1999
2000 if (dword_field & (1 << 13))
2001 param->rss_ip_frags = 1;
2002
0ff1fb65 2003 /* steering attributes */
7b8157be 2004 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 2005 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
2006 MLX4_GET(param->log_mc_entry_sz, outbox,
2007 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
2008 MLX4_GET(param->log_mc_table_sz, outbox,
2009 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
7d077cd3
MB		 2010 MLX4_GET(byte_field, outbox,
2011 INIT_HCA_FS_A0_OFFSET);
2012 param->dmfs_high_steer_mode =
2013 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3];
0ff1fb65
HHZ		 2014 } else {
2015 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
2016 MLX4_GET(param->log_mc_entry_sz, outbox,
2017 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
2018 MLX4_GET(param->log_mc_hash_sz, outbox,
2019 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
2020 MLX4_GET(param->log_mc_table_sz, outbox,
2021 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
2022 }
ab9c17a0 2023
08ff3235
OG		 2024 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
2025 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
2026 if (byte_field & 0x20) /* 64-bytes eqe enabled */
2027 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
2028 if (byte_field & 0x40) /* 64-bytes cqe enabled */
2029 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
2030
77507aa2
IS		 2031 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
2032 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
2033 if (byte_field) {
c3f2511f
IS		 2034 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED;
2035 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED;
77507aa2
IS		 2036 param->cqe_size = 1 << ((byte_field &
2037 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
2038 param->eqe_size = 1 << (((byte_field &
2039 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
2040 }
2041
ab9c17a0
JM		 2042 /* TPT attributes */
2043
2044 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 2045 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 2046 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
2047 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
2048 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
2049
2050 /* UAR attributes */
2051
2052 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
2053 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
2054
77fc29c4
HHZ		 2055 /* phv_check enable */
2056 MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET);
2057 if (byte_field & 0x2)
2058 param->phv_check_en = 1;
ab9c17a0
JM		 2059out:
2060 mlx4_free_cmd_mailbox(dev, mailbox);
2061
2062 return err;
2063}
2064
6d6e996c
MD		 2065static int mlx4_hca_core_clock_update(struct mlx4_dev *dev)
2066{
2067 struct mlx4_cmd_mailbox *mailbox;
2068 __be32 *outbox;
2069 int err;
2070
2071 mailbox = mlx4_alloc_cmd_mailbox(dev);
2072 if (IS_ERR(mailbox)) {
2073 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n");
2074 return PTR_ERR(mailbox);
2075 }
2076 outbox = mailbox->buf;
2077
2078 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2079 MLX4_CMD_QUERY_HCA,
2080 MLX4_CMD_TIME_CLASS_B,
2081 !mlx4_is_slave(dev));
2082 if (err) {
2083 mlx4_warn(dev, "hca_core_clock update failed\n");
2084 goto out;
2085 }
2086
2087 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
2088
2089out:
2090 mlx4_free_cmd_mailbox(dev, mailbox);
2091
2092 return err;
2093}
2094
980e9001
JM		 2095/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
2096 * and real QP0 are active, so that the paravirtualized QP0 is ready
2097 * to operate */
2098static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
2099{
2100 struct mlx4_priv *priv = mlx4_priv(dev);
2101 /* irrelevant if not infiniband */
2102 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
2103 priv->mfunc.master.qp0_state[port].qp0_active)
2104 return 1;
2105 return 0;
2106}
2107
5cc914f1
MA		 2108int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
2109 struct mlx4_vhcr *vhcr,
2110 struct mlx4_cmd_mailbox *inbox,
2111 struct mlx4_cmd_mailbox *outbox,
2112 struct mlx4_cmd_info *cmd)
2113{
2114 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 2115 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 2116 int err;
2117
449fc488
MB		 2118 if (port < 0)
2119 return -EINVAL;
2120
5cc914f1
MA		 2121 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
2122 return 0;
2123
980e9001
JM		 2124 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
2125 /* Enable port only if it was previously disabled */
2126 if (!priv->mfunc.master.init_port_ref[port]) {
2127 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2128 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2129 if (err)
2130 return err;
2131 }
2132 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2133 } else {
2134 if (slave == mlx4_master_func_num(dev)) {
2135 if (check_qp0_state(dev, slave, port) &&
2136 !priv->mfunc.master.qp0_state[port].port_active) {
2137 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
2138 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2139 if (err)
2140 return err;
2141 priv->mfunc.master.qp0_state[port].port_active = 1;
2142 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
2143 }
2144 } else
2145 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 2146 }
2147 ++priv->mfunc.master.init_port_ref[port];
2148 return 0;
2149}
2150
5ae2a7a8 2151int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 2152{
2153 struct mlx4_cmd_mailbox *mailbox;
2154 u32 *inbox;
2155 int err;
2156 u32 flags;
5ae2a7a8 2157 u16 field;
225c7b1f 2158
5ae2a7a8 2159 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 2160#define INIT_PORT_IN_SIZE 256
2161#define INIT_PORT_FLAGS_OFFSET 0x00
2162#define INIT_PORT_FLAG_SIG (1 << 18)
2163#define INIT_PORT_FLAG_NG (1 << 17)
2164#define INIT_PORT_FLAG_G0 (1 << 16)
2165#define INIT_PORT_VL_SHIFT 4
2166#define INIT_PORT_PORT_WIDTH_SHIFT 8
2167#define INIT_PORT_MTU_OFFSET 0x04
2168#define INIT_PORT_MAX_GID_OFFSET 0x06
2169#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
2170#define INIT_PORT_GUID0_OFFSET 0x10
2171#define INIT_PORT_NODE_GUID_OFFSET 0x18
2172#define INIT_PORT_SI_GUID_OFFSET 0x20
2173
5ae2a7a8
RD		 2174 mailbox = mlx4_alloc_cmd_mailbox(dev);
2175 if (IS_ERR(mailbox))
2176 return PTR_ERR(mailbox);
2177 inbox = mailbox->buf;
225c7b1f 2178
5ae2a7a8
RD		 2179 flags = 0;
2180 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
2181 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
2182 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 2183
b79acb49 2184 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 2185 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
2186 field = dev->caps.gid_table_len[port];
2187 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
2188 field = dev->caps.pkey_table_len[port];
2189 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 2190
5ae2a7a8 2191 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 2192 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 2193
5ae2a7a8
RD		 2194 mlx4_free_cmd_mailbox(dev, mailbox);
2195 } else
2196 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 2197 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f 2198
6d6e996c
MD		 2199 if (!err)
2200 mlx4_hca_core_clock_update(dev);
2201
225c7b1f
RD		 2202 return err;
2203}
2204EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
2205
5cc914f1
MA		 2206int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
2207 struct mlx4_vhcr *vhcr,
2208 struct mlx4_cmd_mailbox *inbox,
2209 struct mlx4_cmd_mailbox *outbox,
2210 struct mlx4_cmd_info *cmd)
2211{
2212 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 2213 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 2214 int err;
2215
449fc488
MB		 2216 if (port < 0)
2217 return -EINVAL;
2218
5cc914f1
MA		 2219 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
2220 (1 << port)))
2221 return 0;
2222
980e9001
JM		 2223 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
2224 if (priv->mfunc.master.init_port_ref[port] == 1) {
2225 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
5a031086 2226 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
980e9001
JM		 2227 if (err)
2228 return err;
2229 }
2230 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2231 } else {
2232 /* infiniband port */
2233 if (slave == mlx4_master_func_num(dev)) {
2234 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
2235 priv->mfunc.master.qp0_state[port].port_active) {
2236 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
5a031086 2237 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
980e9001
JM		 2238 if (err)
2239 return err;
2240 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2241 priv->mfunc.master.qp0_state[port].port_active = 0;
2242 }
2243 } else
2244 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 2245 }
5cc914f1
MA		 2246 --priv->mfunc.master.init_port_ref[port];
2247 return 0;
2248}
2249
225c7b1f
RD		 2250int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
2251{
5a031086
JM		 2252 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2253 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 2254}
2255EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
2256
2257int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
2258{
5a031086
JM		 2259 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA,
2260 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
225c7b1f
RD		 2261}
2262
d18f141a
OG		 2263struct mlx4_config_dev {
2264 __be32 update_flags;
d475c95b 2265 __be32 rsvd1[3];
d18f141a
OG		 2266 __be16 vxlan_udp_dport;
2267 __be16 rsvd2;
fca83006
MS		 2268 __be16 roce_v2_entropy;
2269 __be16 roce_v2_udp_dport;
59e14e32
MS		 2270 __be32 roce_flags;
2271 __be32 rsvd4[25];
2272 __be16 rsvd5;
2273 u8 rsvd6;
d475c95b 2274 u8 rx_checksum_val;
d18f141a
OG		 2275};
2276
2277#define MLX4_VXLAN_UDP_DPORT (1 << 0)
fca83006 2278#define MLX4_ROCE_V2_UDP_DPORT BIT(3)
59e14e32 2279#define MLX4_DISABLE_RX_PORT BIT(18)
d18f141a 2280
d475c95b 2281static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
d18f141a
OG		 2282{
2283 int err;
2284 struct mlx4_cmd_mailbox *mailbox;
2285
2286 mailbox = mlx4_alloc_cmd_mailbox(dev);
2287 if (IS_ERR(mailbox))
2288 return PTR_ERR(mailbox);
2289
2290 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
2291
2292 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
2293 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2294
2295 mlx4_free_cmd_mailbox(dev, mailbox);
2296 return err;
2297}
2298
d475c95b
MB		 2299static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2300{
2301 int err;
2302 struct mlx4_cmd_mailbox *mailbox;
2303
2304 mailbox = mlx4_alloc_cmd_mailbox(dev);
2305 if (IS_ERR(mailbox))
2306 return PTR_ERR(mailbox);
2307
2308 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV,
2309 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2310
2311 if (!err)
2312 memcpy(config_dev, mailbox->buf, sizeof(*config_dev));
2313
2314 mlx4_free_cmd_mailbox(dev, mailbox);
2315 return err;
2316}
2317
2318/* Conversion between the HW values and the actual functionality.
2319 * The value represented by the array index,
2320 * and the functionality determined by the flags.
2321 */
2322static const u8 config_dev_csum_flags[] = {
2323 [0] = 0,
2324 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP,
2325 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP |
2326 MLX4_RX_CSUM_MODE_L4,
2327 [3] = MLX4_RX_CSUM_MODE_L4 |
2328 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP |
2329 MLX4_RX_CSUM_MODE_MULTI_VLAN
2330};
2331
2332int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
2333 struct mlx4_config_dev_params *params)
2334{
6af0a52f 2335 struct mlx4_config_dev config_dev = {0};
d475c95b
MB		 2336 int err;
2337 u8 csum_mask;
2338
2339#define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2340#define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2341#define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2342
2343 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2344 return -ENOTSUPP;
2345
2346 err = mlx4_CONFIG_DEV_get(dev, &config_dev);
2347 if (err)
2348 return err;
2349
2350 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) &
2351 CONFIG_DEV_RX_CSUM_MODE_MASK;
2352
2353 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2354 return -EINVAL;
2355 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask];
2356
2357 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) &
2358 CONFIG_DEV_RX_CSUM_MODE_MASK;
2359
2360 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2361 return -EINVAL;
2362 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask];
2363
2364 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport);
2365
2366 return 0;
2367}
2368EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval);
2369
d18f141a
OG		 2370int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
2371{
2372 struct mlx4_config_dev config_dev;
2373
2374 memset(&config_dev, 0, sizeof(config_dev));
2375 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
2376 config_dev.vxlan_udp_dport = udp_port;
2377
d475c95b 2378 return mlx4_CONFIG_DEV_set(dev, &config_dev);
d18f141a
OG		 2379}
2380EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
2381
59e14e32
MS		 2382#define CONFIG_DISABLE_RX_PORT BIT(15)
2383int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis)
2384{
2385 struct mlx4_config_dev config_dev;
2386
2387 memset(&config_dev, 0, sizeof(config_dev));
2388 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT);
2389 if (dis)
2390 config_dev.roce_flags =
2391 cpu_to_be32(CONFIG_DISABLE_RX_PORT);
2392
2393 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2394}
2395
fca83006
MS		 2396int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port)
2397{
2398 struct mlx4_config_dev config_dev;
2399
2400 memset(&config_dev, 0, sizeof(config_dev));
2401 config_dev.update_flags = cpu_to_be32(MLX4_ROCE_V2_UDP_DPORT);
2402 config_dev.roce_v2_udp_dport = cpu_to_be16(udp_port);
2403
2404 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2405}
2406EXPORT_SYMBOL_GPL(mlx4_config_roce_v2_port);
2407
59e14e32
MS		 2408int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2)
2409{
2410 struct mlx4_cmd_mailbox *mailbox;
2411 struct {
2412 __be32 v_port1;
2413 __be32 v_port2;
2414 } *v2p;
2415 int err;
2416
2417 mailbox = mlx4_alloc_cmd_mailbox(dev);
2418 if (IS_ERR(mailbox))
2419 return -ENOMEM;
2420
2421 v2p = mailbox->buf;
2422 v2p->v_port1 = cpu_to_be32(port1);
2423 v2p->v_port2 = cpu_to_be32(port2);
2424
2425 err = mlx4_cmd(dev, mailbox->dma, 0,
2426 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP,
2427 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2428
2429 mlx4_free_cmd_mailbox(dev, mailbox);
2430 return err;
2431}
2432
d18f141a 2433
225c7b1f
RD		 2434int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
2435{
2436 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
2437 MLX4_CMD_SET_ICM_SIZE,
f9baff50 2438 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 2439 if (ret)
2440 return ret;
2441
2442 /*
2443 * Round up number of system pages needed in case
2444 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2445 */
2446 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
2447 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
2448
2449 return 0;
2450}
2451
2452int mlx4_NOP(struct mlx4_dev *dev)
2453{
2454 /* Input modifier of 0x1f means "finish as soon as possible." */
5a031086
JM		 2455 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A,
2456 MLX4_CMD_NATIVE);
225c7b1f 2457}
14c07b13 2458
8e1a28e8
HHZ		 2459int mlx4_get_phys_port_id(struct mlx4_dev *dev)
2460{
2461 u8 port;
2462 u32 *outbox;
2463 struct mlx4_cmd_mailbox *mailbox;
2464 u32 in_mod;
2465 u32 guid_hi, guid_lo;
2466 int err, ret = 0;
2467#define MOD_STAT_CFG_PORT_OFFSET 8
2468#define MOD_STAT_CFG_GUID_H 0X14
2469#define MOD_STAT_CFG_GUID_L 0X1c
2470
2471 mailbox = mlx4_alloc_cmd_mailbox(dev);
2472 if (IS_ERR(mailbox))
2473 return PTR_ERR(mailbox);
2474 outbox = mailbox->buf;
2475
2476 for (port = 1; port <= dev->caps.num_ports; port++) {
2477 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
2478 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
2479 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2480 MLX4_CMD_NATIVE);
2481 if (err) {
2482 mlx4_err(dev, "Fail to get port %d uplink guid\n",
2483 port);
2484 ret = err;
2485 } else {
2486 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2487 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2488 dev->caps.phys_port_id[port] = (u64)guid_lo |
2489 (u64)guid_hi << 32;
2490 }
2491 }
2492 mlx4_free_cmd_mailbox(dev, mailbox);
2493 return ret;
2494}
2495
14c07b13
YP		 2496#define MLX4_WOL_SETUP_MODE (5 << 28)
2497int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
2498{
2499 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2500
2501 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 2502 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2503 MLX4_CMD_NATIVE);
14c07b13
YP		 2504}
2505EXPORT_SYMBOL_GPL(mlx4_wol_read);
2506
2507int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
2508{
2509 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2510
2511 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 2512 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 2513}
2514EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 2515
2516enum {
2517 ADD_TO_MCG = 0x26,
2518};
2519
2520
2521void mlx4_opreq_action(struct work_struct *work)
2522{
2523 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
2524 opreq_task);
2525 struct mlx4_dev *dev = &priv->dev;
2526 int num_tasks = atomic_read(&priv->opreq_count);
2527 struct mlx4_cmd_mailbox *mailbox;
2528 struct mlx4_mgm *mgm;
2529 u32 *outbox;
2530 u32 modifier;
2531 u16 token;
fe6f700d
YP		 2532 u16 type;
2533 int err;
2534 u32 num_qps;
2535 struct mlx4_qp qp;
2536 int i;
2537 u8 rem_mcg;
2538 u8 prot;
2539
2540#define GET_OP_REQ_MODIFIER_OFFSET 0x08
2541#define GET_OP_REQ_TOKEN_OFFSET 0x14
2542#define GET_OP_REQ_TYPE_OFFSET 0x1a
2543#define GET_OP_REQ_DATA_OFFSET 0x20
2544
2545 mailbox = mlx4_alloc_cmd_mailbox(dev);
2546 if (IS_ERR(mailbox)) {
2547 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2548 return;
2549 }
2550 outbox = mailbox->buf;
2551
2552 while (num_tasks) {
2553 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2554 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2555 MLX4_CMD_NATIVE);
2556 if (err) {
6d3be300 2557 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 2558 err);
2559 return;
2560 }
2561 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2562 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2563 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 2564 type &= 0xfff;
2565
2566 switch (type) {
2567 case ADD_TO_MCG:
2568 if (dev->caps.steering_mode ==
2569 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2570 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2571 err = EPERM;
2572 break;
2573 }
2574 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2575 GET_OP_REQ_DATA_OFFSET);
2576 num_qps = be32_to_cpu(mgm->members_count) &
2577 MGM_QPN_MASK;
2578 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2579 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2580
2581 for (i = 0; i < num_qps; i++) {
2582 qp.qpn = be32_to_cpu(mgm->qp[i]);
2583 if (rem_mcg)
2584 err = mlx4_multicast_detach(dev, &qp,
2585 mgm->gid,
2586 prot, 0);
2587 else
2588 err = mlx4_multicast_attach(dev, &qp,
2589 mgm->gid,
2590 mgm->gid[5]
2591 , 0, prot,
2592 NULL);
2593 if (err)
2594 break;
2595 }
2596 break;
2597 default:
2598 mlx4_warn(dev, "Bad type for required operation\n");
2599 err = EINVAL;
2600 break;
2601 }
28d222bb
EP		 2602 err = mlx4_cmd(dev, 0, ((u32) err |
2603 (__force u32)cpu_to_be32(token) << 16),
fe6f700d
YP		 2604 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2605 MLX4_CMD_NATIVE);
2606 if (err) {
2607 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2608 err);
2609 goto out;
2610 }
2611 memset(outbox, 0, 0xffc);
2612 num_tasks = atomic_dec_return(&priv->opreq_count);
2613 }
2614
2615out:
2616 mlx4_free_cmd_mailbox(dev, mailbox);
2617}
114840c3
JM		 2618
2619static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2620 struct mlx4_cmd_mailbox *mailbox)
2621{
2622#define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2623#define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2624#define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2625#define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2626
2627 u32 set_attr_mask, getresp_attr_mask;
2628 u32 trap_attr_mask, traprepress_attr_mask;
2629
2630 MLX4_GET(set_attr_mask, mailbox->buf,
2631 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2632 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2633 set_attr_mask);
2634
2635 MLX4_GET(getresp_attr_mask, mailbox->buf,
2636 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2637 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2638 getresp_attr_mask);
2639
2640 MLX4_GET(trap_attr_mask, mailbox->buf,
2641 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2642 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2643 trap_attr_mask);
2644
2645 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2646 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2647 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2648 traprepress_attr_mask);
2649
2650 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2651 traprepress_attr_mask)
2652 return 1;
2653
2654 return 0;
2655}
2656
2657int mlx4_config_mad_demux(struct mlx4_dev *dev)
2658{
2659 struct mlx4_cmd_mailbox *mailbox;
2660 int secure_host_active;
2661 int err;
2662
2663 /* Check if mad_demux is supported */
2664 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2665 return 0;
2666
2667 mailbox = mlx4_alloc_cmd_mailbox(dev);
2668 if (IS_ERR(mailbox)) {
2669 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2670 return -ENOMEM;
2671 }
2672
2673 /* Query mad_demux to find out which MADs are handled by internal sma */
2674 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2675 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2676 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2677 if (err) {
2678 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2679 err);
2680 goto out;
2681 }
2682
2683 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2684
2685 /* Config mad_demux to handle all MADs returned by the query above */
2686 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2687 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2688 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2689 if (err) {
2690 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2691 goto out;
2692 }
2693
2694 if (secure_host_active)
2695 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2696out:
2697 mlx4_free_cmd_mailbox(dev, mailbox);
2698 return err;
2699}
adbc7ac5
SM		 2700
2701/* Access Reg commands */
2702enum mlx4_access_reg_masks {
2703 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2704 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2705 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2706};
2707
2708struct mlx4_access_reg {
2709 __be16 constant1;
2710 u8 status;
2711 u8 resrvd1;
2712 __be16 reg_id;
2713 u8 method;
2714 u8 constant2;
2715 __be32 resrvd2[2];
2716 __be16 len_const;
2717 __be16 resrvd3;
2718#define MLX4_ACCESS_REG_HEADER_SIZE (20)
2719 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2720} __attribute__((__packed__));
2721
2722/**
2723 * mlx4_ACCESS_REG - Generic access reg command.
2724 * @dev: mlx4_dev.
2725 * @reg_id: register ID to access.
2726 * @method: Access method Read/Write.
2727 * @reg_len: register length to Read/Write in bytes.
2728 * @reg_data: reg_data pointer to Read/Write From/To.
2729 *
2730 * Access ConnectX registers FW command.
2731 * Returns 0 on success and copies outbox mlx4_access_reg data
2732 * field into reg_data or a negative error code.
2733 */
2734static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2735 enum mlx4_access_reg_method method,
2736 u16 reg_len, void *reg_data)
2737{
2738 struct mlx4_cmd_mailbox *inbox, *outbox;
2739 struct mlx4_access_reg *inbuf, *outbuf;
2740 int err;
2741
2742 inbox = mlx4_alloc_cmd_mailbox(dev);
2743 if (IS_ERR(inbox))
2744 return PTR_ERR(inbox);
2745
2746 outbox = mlx4_alloc_cmd_mailbox(dev);
2747 if (IS_ERR(outbox)) {
2748 mlx4_free_cmd_mailbox(dev, inbox);
2749 return PTR_ERR(outbox);
2750 }
2751
2752 inbuf = inbox->buf;
2753 outbuf = outbox->buf;
2754
2755 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2756 inbuf->constant2 = 0x1;
2757 inbuf->reg_id = cpu_to_be16(reg_id);
2758 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2759
2760 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2761 inbuf->len_const =
2762 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2763 ((0x3) << 12));
2764
2765 memcpy(inbuf->reg_data, reg_data, reg_len);
2766 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2767 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
6e806699 2768 MLX4_CMD_WRAPPED);
adbc7ac5
SM		 2769 if (err)
2770 goto out;
2771
2772 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2773 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2774 mlx4_err(dev,
2775 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2776 reg_id, err);
2777 goto out;
2778 }
2779
2780 memcpy(reg_data, outbuf->reg_data, reg_len);
2781out:
2782 mlx4_free_cmd_mailbox(dev, inbox);
2783 mlx4_free_cmd_mailbox(dev, outbox);
2784 return err;
2785}
2786
2787/* ConnectX registers IDs */
2788enum mlx4_reg_id {
2789 MLX4_REG_ID_PTYS = 0x5004,
2790};
2791
2792/**
2793 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2794 * register
2795 * @dev: mlx4_dev.
2796 * @method: Access method Read/Write.
2797 * @ptys_reg: PTYS register data pointer.
2798 *
2799 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2800 * configuration
2801 * Returns 0 on success or a negative error code.
2802 */
2803int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2804 enum mlx4_access_reg_method method,
2805 struct mlx4_ptys_reg *ptys_reg)
2806{
2807 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2808 method, sizeof(*ptys_reg), ptys_reg);
2809}
2810EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
6e806699
SM		 2811
2812int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2813 struct mlx4_vhcr *vhcr,
2814 struct mlx4_cmd_mailbox *inbox,
2815 struct mlx4_cmd_mailbox *outbox,
2816 struct mlx4_cmd_info *cmd)
2817{
2818 struct mlx4_access_reg *inbuf = inbox->buf;
2819 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2820 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2821
2822 if (slave != mlx4_master_func_num(dev) &&
2823 method == MLX4_ACCESS_REG_WRITE)
2824 return -EPERM;
2825
2826 if (reg_id == MLX4_REG_ID_PTYS) {
2827 struct mlx4_ptys_reg *ptys_reg =
2828 (struct mlx4_ptys_reg *)inbuf->reg_data;
2829
2830 ptys_reg->local_port =
2831 mlx4_slave_convert_port(dev, slave,
2832 ptys_reg->local_port);
2833 }
2834
2835 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2836 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2837 MLX4_CMD_NATIVE);
2838}
77fc29c4
HHZ		 2839
2840static int mlx4_SET_PORT_phv_bit(struct mlx4_dev *dev, u8 port, u8 phv_bit)
2841{
2842#define SET_PORT_GEN_PHV_VALID 0x10
2843#define SET_PORT_GEN_PHV_EN 0x80
2844
2845 struct mlx4_cmd_mailbox *mailbox;
2846 struct mlx4_set_port_general_context *context;
2847 u32 in_mod;
2848 int err;
2849
2850 mailbox = mlx4_alloc_cmd_mailbox(dev);
2851 if (IS_ERR(mailbox))
2852 return PTR_ERR(mailbox);
2853 context = mailbox->buf;
2854
2855 context->v_ignore_fcs |= SET_PORT_GEN_PHV_VALID;
2856 if (phv_bit)
2857 context->phv_en |= SET_PORT_GEN_PHV_EN;
2858
2859 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
2860 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE,
2861 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
2862 MLX4_CMD_NATIVE);
2863
2864 mlx4_free_cmd_mailbox(dev, mailbox);
2865 return err;
2866}
2867
2868int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv)
2869{
2870 int err;
2871 struct mlx4_func_cap func_cap;
2872
2873 memset(&func_cap, 0, sizeof(func_cap));
35e455f4 2874 err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap);
77fc29c4
HHZ		 2875 if (!err)
2876 *phv = func_cap.flags & QUERY_FUNC_CAP_PHV_BIT;
2877 return err;
2878}
2879EXPORT_SYMBOL(get_phv_bit);
2880
2881int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val)
2882{
2883 int ret;
2884
2885 if (mlx4_is_slave(dev))
2886 return -EPERM;
2887
2888 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
2889 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {
2890 ret = mlx4_SET_PORT_phv_bit(dev, port, new_val);
2891 if (!ret)
2892 dev->caps.phv_bit[port] = new_val;
2893 return ret;
2894 }
2895
2896 return -EOPNOTSUPP;
2897}
2898EXPORT_SYMBOL(set_phv_bit);
2b3ddf27
JM		 2899
2900void mlx4_replace_zero_macs(struct mlx4_dev *dev)
2901{
2902 int i;
2903 u8 mac_addr[ETH_ALEN];
2904
2905 dev->port_random_macs = 0;
2906 for (i = 1; i <= dev->caps.num_ports; ++i)
2907 if (!dev->caps.def_mac[i] &&
2908 dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) {
2909 eth_random_addr(mac_addr);
2910 dev->port_random_macs |= 1 << i;
2911 dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr);
2912 }
2913}
2914EXPORT_SYMBOL_GPL(mlx4_replace_zero_macs);
Linux 6.x block layer and io_uring tree(s)