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net/mlx4_core: Rename QUERY_FUNC_CAP fields
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
4d531aa8 94 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
540b3a39 112 [53] = "Port ETS Scheduler support",
4d531aa8 113 [55] = "Port link type sensing support",
00f5ce99 114 [59] = "Port management change event support",
08ff3235
OG		 115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
225c7b1f
RD		 117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 122 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
b3416f44
SP		 126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 131 [2] = "RSS XOR Hash Function support",
955154fa 132 [3] = "Device manage flow steering support",
d998735f 133 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
b01978ca
JM		 136 [7] = "FSM (MAC anti-spoofing) support",
137 [8] = "Dynamic QP updates support"
b3416f44
SP		 138 };
139 int i;
140
141 for (i = 0; i < ARRAY_SIZE(fname); ++i)
142 if (fname[i] && (flags & (1LL << i)))
143 mlx4_dbg(dev, " %s\n", fname[i]);
144}
145
2d928651
VS		 146int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
147{
148 struct mlx4_cmd_mailbox *mailbox;
149 u32 *inbox;
150 int err = 0;
151
152#define MOD_STAT_CFG_IN_SIZE 0x100
153
154#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
155#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
156
157 mailbox = mlx4_alloc_cmd_mailbox(dev);
158 if (IS_ERR(mailbox))
159 return PTR_ERR(mailbox);
160 inbox = mailbox->buf;
161
2d928651
VS		 162 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
163 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
164
165 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 166 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 167
168 mlx4_free_cmd_mailbox(dev, mailbox);
169 return err;
170}
171
5cc914f1
MA		 172int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
173 struct mlx4_vhcr *vhcr,
174 struct mlx4_cmd_mailbox *inbox,
175 struct mlx4_cmd_mailbox *outbox,
176 struct mlx4_cmd_info *cmd)
177{
5a0d0a61 178 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 179 u8 field;
180 u32 size;
181 int err = 0;
182
183#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
184#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 185#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 186#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 187#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
188#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
189#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
190#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
191#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
192#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 193#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 194#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 195
eb456a68
JM		 196#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
197#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
198#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
199#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
200#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
201#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
202
105c320f
JM		 203#define QUERY_FUNC_CAP_FMR_FLAG 0x80
204#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
205#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 206#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
105c320f
JM		 207
208/* when opcode modifier = 1 */
5cc914f1 209#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
73e74ab4
HHZ		 210#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
211#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 212
47605df9
JM		 213#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
214#define QUERY_FUNC_CAP_QP0_PROXY 0x14
215#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
216#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
217
73e74ab4
HHZ		 218#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
219#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
105c320f 220
73e74ab4 221#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
105c320f 222
5cc914f1 223 if (vhcr->op_modifier == 1) {
47605df9
JM		 224 field = vhcr->in_modifier; /* phys-port = logical-port */
225 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
226
227 /* size is now the QP number */
228 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
229 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
230
231 size += 2;
232 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
233
234 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
235 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
236
237 size += 2;
238 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
239
5cc914f1 240 } else if (vhcr->op_modifier == 0) {
eb456a68
JM		 241 /* enable rdma and ethernet interfaces, and new quota locations */
242 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
243 QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1
MA		 244 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
245
5cc914f1
MA		 246 field = dev->caps.num_ports;
247 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
248
08ff3235 249 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 250 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
251
105c320f
JM		 252 field = 0; /* protected FMR support not available as yet */
253 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
254
5a0d0a61 255 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 256 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 257 size = dev->caps.num_qps;
258 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 259
5a0d0a61 260 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 261 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 262 size = dev->caps.num_srqs;
263 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 264
5a0d0a61 265 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 266 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 267 size = dev->caps.num_cqs;
268 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1
MA		 269
270 size = dev->caps.num_eqs;
271 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
272
273 size = dev->caps.reserved_eqs;
274 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
275
5a0d0a61 276 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 277 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 278 size = dev->caps.num_mpts;
279 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 280
5a0d0a61 281 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 282 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 283 size = dev->caps.num_mtts;
284 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 285
286 size = dev->caps.num_mgms + dev->caps.num_amgms;
287 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 288 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1
MA		 289
290 } else
291 err = -EINVAL;
292
293 return err;
294}
295
47605df9
JM		 296int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
297 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 298{
299 struct mlx4_cmd_mailbox *mailbox;
300 u32 *outbox;
47605df9 301 u8 field, op_modifier;
5cc914f1 302 u32 size;
eb456a68 303 int err = 0, quotas = 0;
5cc914f1 304
47605df9 305 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
5cc914f1
MA		 306
307 mailbox = mlx4_alloc_cmd_mailbox(dev);
308 if (IS_ERR(mailbox))
309 return PTR_ERR(mailbox);
310
47605df9
JM		 311 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
312 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 313 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
314 if (err)
315 goto out;
316
317 outbox = mailbox->buf;
318
47605df9
JM		 319 if (!op_modifier) {
320 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
321 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
322 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
323 err = -EPROTONOSUPPORT;
324 goto out;
325 }
326 func_cap->flags = field;
eb456a68 327 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 328
47605df9
JM		 329 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
330 func_cap->num_ports = field;
5cc914f1 331
47605df9
JM		 332 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
333 func_cap->pf_context_behaviour = size;
5cc914f1 334
eb456a68
JM		 335 if (quotas) {
336 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
337 func_cap->qp_quota = size & 0xFFFFFF;
338
339 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
340 func_cap->srq_quota = size & 0xFFFFFF;
341
342 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
343 func_cap->cq_quota = size & 0xFFFFFF;
344
345 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
346 func_cap->mpt_quota = size & 0xFFFFFF;
347
348 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
349 func_cap->mtt_quota = size & 0xFFFFFF;
350
351 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
352 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 353
eb456a68
JM		 354 } else {
355 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
356 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 357
eb456a68
JM		 358 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
359 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 360
eb456a68
JM		 361 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
362 func_cap->cq_quota = size & 0xFFFFFF;
363
364 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
365 func_cap->mpt_quota = size & 0xFFFFFF;
366
367 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
368 func_cap->mtt_quota = size & 0xFFFFFF;
369
370 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
371 func_cap->mcg_quota = size & 0xFFFFFF;
372 }
47605df9
JM		 373 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
374 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 375
47605df9
JM		 376 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
377 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 378
47605df9
JM		 379 goto out;
380 }
5cc914f1 381
47605df9
JM		 382 /* logical port query */
383 if (gen_or_port > dev->caps.num_ports) {
384 err = -EINVAL;
385 goto out;
386 }
5cc914f1 387
47605df9 388 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
73e74ab4
HHZ		 389 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
390 if (field & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
47605df9
JM		 391 mlx4_err(dev, "VLAN is enforced on this port\n");
392 err = -EPROTONOSUPPORT;
5cc914f1 393 goto out;
47605df9 394 }
5cc914f1 395
73e74ab4 396 if (field & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 397 mlx4_err(dev, "Force mac is enabled on this port\n");
398 err = -EPROTONOSUPPORT;
399 goto out;
5cc914f1 400 }
47605df9 401 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 402 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
403 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
47605df9
JM		 404 mlx4_err(dev, "phy_wqe_gid is "
405 "enforced on this ib port\n");
406 err = -EPROTONOSUPPORT;
407 goto out;
408 }
409 }
5cc914f1 410
47605df9
JM		 411 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
412 func_cap->physical_port = field;
413 if (func_cap->physical_port != gen_or_port) {
414 err = -ENOSYS;
415 goto out;
5cc914f1
MA		 416 }
417
47605df9
JM		 418 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
419 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
420
421 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
422 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
423
424 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
425 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
426
427 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
428 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
429
5cc914f1
MA		 430 /* All other resources are allocated by the master, but we still report
431 * 'num' and 'reserved' capabilities as follows:
432 * - num remains the maximum resource index
433 * - 'num - reserved' is the total available objects of a resource, but
434 * resource indices may be less than 'reserved'
435 * TODO: set per-resource quotas */
436
437out:
438 mlx4_free_cmd_mailbox(dev, mailbox);
439
440 return err;
441}
442
225c7b1f
RD		 443int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
444{
445 struct mlx4_cmd_mailbox *mailbox;
446 u32 *outbox;
447 u8 field;
ccf86321 448 u32 field32, flags, ext_flags;
225c7b1f
RD		 449 u16 size;
450 u16 stat_rate;
451 int err;
5ae2a7a8 452 int i;
225c7b1f
RD		 453
454#define QUERY_DEV_CAP_OUT_SIZE 0x100
455#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
456#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
457#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
458#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
459#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
460#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
461#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
462#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
463#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
464#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
465#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
466#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
467#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
468#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
469#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
470#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
471#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
472#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
473#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
474#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
475#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 476#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 477#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 478#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
479#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
480#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
481#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
482#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 483#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 484#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
485#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 486#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 487#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 488#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 489#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
490#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
491#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
492#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
493#define QUERY_DEV_CAP_BF_OFFSET 0x4c
494#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
495#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
496#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
497#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
498#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
499#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
500#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
501#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
502#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
503#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
504#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
505#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 506#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
507#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 508#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
3f7fb021 509#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
0ff1fb65
HHZ		 510#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
511#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
225c7b1f
RD		 512#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
513#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
514#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
515#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
516#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
517#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
518#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
519#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
520#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
521#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 522#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 523#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
524#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
955154fa 525#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
225c7b1f 526
b3416f44 527 dev_cap->flags2 = 0;
225c7b1f
RD		 528 mailbox = mlx4_alloc_cmd_mailbox(dev);
529 if (IS_ERR(mailbox))
530 return PTR_ERR(mailbox);
531 outbox = mailbox->buf;
532
533 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 534 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 535 if (err)
536 goto out;
537
538 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
539 dev_cap->reserved_qps = 1 << (field & 0xf);
540 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
541 dev_cap->max_qps = 1 << (field & 0x1f);
542 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
543 dev_cap->reserved_srqs = 1 << (field >> 4);
544 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
545 dev_cap->max_srqs = 1 << (field & 0x1f);
546 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
547 dev_cap->max_cq_sz = 1 << field;
548 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
549 dev_cap->reserved_cqs = 1 << (field & 0xf);
550 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
551 dev_cap->max_cqs = 1 << (field & 0x1f);
552 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
553 dev_cap->max_mpts = 1 << (field & 0x3f);
554 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 555 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 556 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 557 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 558 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
559 dev_cap->reserved_mtts = 1 << (field >> 4);
560 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
561 dev_cap->max_mrw_sz = 1 << field;
562 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
563 dev_cap->reserved_mrws = 1 << (field & 0xf);
564 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
565 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
566 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
567 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
568 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
569 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 570 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
571 field &= 0x1f;
572 if (!field)
573 dev_cap->max_gso_sz = 0;
574 else
575 dev_cap->max_gso_sz = 1 << field;
576
b3416f44
SP		 577 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
578 if (field & 0x20)
579 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
580 if (field & 0x10)
581 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
582 field &= 0xf;
583 if (field) {
584 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
585 dev_cap->max_rss_tbl_sz = 1 << field;
586 } else
587 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 588 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
589 dev_cap->max_rdma_global = 1 << (field & 0x3f);
590 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
591 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 592 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 593 dev_cap->num_ports = field & 0xf;
149983af
DB		 594 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
595 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 596 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
597 if (field & 0x80)
598 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
599 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
600 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
601 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 602 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
603 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 604 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
605 if (field & 0x80)
606 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 607 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 608 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 609 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 610 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
611 dev_cap->reserved_uars = field >> 4;
612 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
613 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
614 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
615 dev_cap->min_page_sz = 1 << field;
616
617 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
618 if (field & 0x80) {
619 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
620 dev_cap->bf_reg_size = 1 << (field & 0x1f);
621 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 622 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 623 field = 3;
225c7b1f
RD		 624 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
625 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
626 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
627 } else {
628 dev_cap->bf_reg_size = 0;
629 mlx4_dbg(dev, "BlueFlame not available\n");
630 }
631
632 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
633 dev_cap->max_sq_sg = field;
634 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
635 dev_cap->max_sq_desc_sz = size;
636
637 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
638 dev_cap->max_qp_per_mcg = 1 << field;
639 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
640 dev_cap->reserved_mgms = field & 0xf;
641 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
642 dev_cap->max_mcgs = 1 << field;
643 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
644 dev_cap->reserved_pds = field >> 4;
645 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
646 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 647 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
648 dev_cap->reserved_xrcds = field >> 4;
426dd00d 649 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 650 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 651
652 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
653 dev_cap->rdmarc_entry_sz = size;
654 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
655 dev_cap->qpc_entry_sz = size;
656 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
657 dev_cap->aux_entry_sz = size;
658 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
659 dev_cap->altc_entry_sz = size;
660 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
661 dev_cap->eqc_entry_sz = size;
662 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
663 dev_cap->cqc_entry_sz = size;
664 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
665 dev_cap->srq_entry_sz = size;
666 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
667 dev_cap->cmpt_entry_sz = size;
668 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
669 dev_cap->mtt_entry_sz = size;
670 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
671 dev_cap->dmpt_entry_sz = size;
672
673 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
674 dev_cap->max_srq_sz = 1 << field;
675 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
676 dev_cap->max_qp_sz = 1 << field;
677 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
678 dev_cap->resize_srq = field & 1;
679 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
680 dev_cap->max_rq_sg = field;
681 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
682 dev_cap->max_rq_desc_sz = size;
683
684 MLX4_GET(dev_cap->bmme_flags, outbox,
685 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
686 MLX4_GET(dev_cap->reserved_lkey, outbox,
687 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
955154fa
MB		 688 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
689 if (field & 1<<6)
5930e8d0 690 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
225c7b1f
RD		 691 MLX4_GET(dev_cap->max_icm_sz, outbox,
692 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 693 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
694 MLX4_GET(dev_cap->max_counters, outbox,
695 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 696
3f7fb021 697 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 698 if (field32 & (1 << 16))
699 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
3f7fb021
RE		 700 if (field32 & (1 << 26))
701 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 702 if (field32 & (1 << 20))
703 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
3f7fb021 704
5ae2a7a8
RD		 705 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
706 for (i = 1; i <= dev_cap->num_ports; ++i) {
707 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
708 dev_cap->max_vl[i] = field >> 4;
709 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 710 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 711 dev_cap->max_port_width[i] = field & 0xf;
712 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
713 dev_cap->max_gids[i] = 1 << (field & 0xf);
714 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
715 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
716 }
717 } else {
7ff93f8b 718#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 719#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 720#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 721#define QUERY_PORT_WIDTH_OFFSET 0x06
722#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 723#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 724#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 725#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 726#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
727#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
728#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 729
730 for (i = 1; i <= dev_cap->num_ports; ++i) {
731 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 732 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 733 if (err)
734 goto out;
735
7ff93f8b
YP		 736 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
737 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 738 dev_cap->suggested_type[i] = (field >> 3) & 1;
739 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 740 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 741 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 742 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
743 dev_cap->max_port_width[i] = field & 0xf;
744 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
745 dev_cap->max_gids[i] = 1 << (field >> 4);
746 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
747 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
748 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 749 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
750 dev_cap->log_max_macs[i] = field & 0xf;
751 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 752 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
753 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 754 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
755 dev_cap->trans_type[i] = field32 >> 24;
756 dev_cap->vendor_oui[i] = field32 & 0xffffff;
757 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
758 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 759 }
760 }
761
95d04f07
RD		 762 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
763 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 764
765 /*
766 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
767 * we can't use any EQs whose doorbell falls on that page,
768 * even if the EQ itself isn't reserved.
769 */
770 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
771 dev_cap->reserved_eqs);
772
773 mlx4_dbg(dev, "Max ICM size %lld MB\n",
774 (unsigned long long) dev_cap->max_icm_sz >> 20);
775 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
776 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
777 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
778 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
779 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
780 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
781 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
782 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
783 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
784 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
785 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
786 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
787 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
788 dev_cap->max_pds, dev_cap->reserved_mgms);
789 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
790 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
791 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 792 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 793 dev_cap->max_port_width[1]);
225c7b1f
RD		 794 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
795 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
796 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
797 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 798 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 799 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 800 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 801
802 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 803 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 804
805out:
806 mlx4_free_cmd_mailbox(dev, mailbox);
807 return err;
808}
809
b91cb3eb
JM		 810int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
811 struct mlx4_vhcr *vhcr,
812 struct mlx4_cmd_mailbox *inbox,
813 struct mlx4_cmd_mailbox *outbox,
814 struct mlx4_cmd_info *cmd)
815{
2a4fae14 816 u64 flags;
b91cb3eb
JM		 817 int err = 0;
818 u8 field;
cc1ade94 819 u32 bmme_flags;
b91cb3eb
JM		 820
821 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
822 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
823 if (err)
824 return err;
825
cc1ade94
SM		 826 /* add port mng change event capability and disable mw type 1
827 * unconditionally to slaves
828 */
2a4fae14
JM		 829 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
830 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 831 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
2a4fae14
JM		 832 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
833
30b40c31
AV		 834 /* For guests, disable timestamp */
835 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
836 field &= 0x7f;
837 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
838
b91cb3eb
JM		 839 /* For guests, report Blueflame disabled */
840 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
841 field &= 0x7f;
842 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
843
cc1ade94
SM		 844 /* For guests, disable mw type 2 */
845 MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
846 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
847 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
848
0081c8f3
JM		 849 /* turn off device-managed steering capability if not enabled */
850 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
851 MLX4_GET(field, outbox->buf,
852 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
853 field &= 0x7f;
854 MLX4_PUT(outbox->buf, field,
855 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
856 }
b91cb3eb
JM		 857 return 0;
858}
859
5cc914f1
MA		 860int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
861 struct mlx4_vhcr *vhcr,
862 struct mlx4_cmd_mailbox *inbox,
863 struct mlx4_cmd_mailbox *outbox,
864 struct mlx4_cmd_info *cmd)
865{
0eb62b93 866 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 867 u64 def_mac;
868 u8 port_type;
6634961c 869 u16 short_field;
5cc914f1 870 int err;
948e306d 871 int admin_link_state;
5cc914f1 872
105c320f 873#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 874#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 875#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
876#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 877
5cc914f1
MA		 878 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
879 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
880 MLX4_CMD_NATIVE);
881
882 if (!err && dev->caps.function != slave) {
0508ad64 883 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 884 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
885
886 /* get port type - currently only eth is enabled */
887 MLX4_GET(port_type, outbox->buf,
888 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
889
105c320f
JM		 890 /* No link sensing allowed */
891 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
892 /* set port type to currently operating port type */
893 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 894
948e306d
RE		 895 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
896 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
897 port_type |= MLX4_PORT_LINK_UP_MASK;
898 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
899 port_type &= ~MLX4_PORT_LINK_UP_MASK;
900
5cc914f1
MA		 901 MLX4_PUT(outbox->buf, port_type,
902 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c
JM		 903
904 short_field = 1; /* slave max gids */
905 MLX4_PUT(outbox->buf, short_field,
906 QUERY_PORT_CUR_MAX_GID_OFFSET);
907
908 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
909 MLX4_PUT(outbox->buf, short_field,
910 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 911 }
912
913 return err;
914}
915
6634961c
JM		 916int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
917 int *gid_tbl_len, int *pkey_tbl_len)
918{
919 struct mlx4_cmd_mailbox *mailbox;
920 u32 *outbox;
921 u16 field;
922 int err;
923
924 mailbox = mlx4_alloc_cmd_mailbox(dev);
925 if (IS_ERR(mailbox))
926 return PTR_ERR(mailbox);
927
928 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
929 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
930 MLX4_CMD_WRAPPED);
931 if (err)
932 goto out;
933
934 outbox = mailbox->buf;
935
936 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
937 *gid_tbl_len = field;
938
939 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
940 *pkey_tbl_len = field;
941
942out:
943 mlx4_free_cmd_mailbox(dev, mailbox);
944 return err;
945}
946EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
947
225c7b1f
RD		 948int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
949{
950 struct mlx4_cmd_mailbox *mailbox;
951 struct mlx4_icm_iter iter;
952 __be64 *pages;
953 int lg;
954 int nent = 0;
955 int i;
956 int err = 0;
957 int ts = 0, tc = 0;
958
959 mailbox = mlx4_alloc_cmd_mailbox(dev);
960 if (IS_ERR(mailbox))
961 return PTR_ERR(mailbox);
225c7b1f
RD		 962 pages = mailbox->buf;
963
964 for (mlx4_icm_first(icm, &iter);
965 !mlx4_icm_last(&iter);
966 mlx4_icm_next(&iter)) {
967 /*
968 * We have to pass pages that are aligned to their
969 * size, so find the least significant 1 in the
970 * address or size and use that as our log2 size.
971 */
972 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
973 if (lg < MLX4_ICM_PAGE_SHIFT) {
974 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
975 MLX4_ICM_PAGE_SIZE,
976 (unsigned long long) mlx4_icm_addr(&iter),
977 mlx4_icm_size(&iter));
978 err = -EINVAL;
979 goto out;
980 }
981
982 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
983 if (virt != -1) {
984 pages[nent * 2] = cpu_to_be64(virt);
985 virt += 1 << lg;
986 }
987
988 pages[nent * 2 + 1] =
989 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
990 (lg - MLX4_ICM_PAGE_SHIFT));
991 ts += 1 << (lg - 10);
992 ++tc;
993
994 if (++nent == MLX4_MAILBOX_SIZE / 16) {
995 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 996 MLX4_CMD_TIME_CLASS_B,
997 MLX4_CMD_NATIVE);
225c7b1f
RD		 998 if (err)
999 goto out;
1000 nent = 0;
1001 }
1002 }
1003 }
1004
1005 if (nent)
f9baff50
JM		 1006 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1007 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1008 if (err)
1009 goto out;
1010
1011 switch (op) {
1012 case MLX4_CMD_MAP_FA:
1013 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
1014 break;
1015 case MLX4_CMD_MAP_ICM_AUX:
1016 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
1017 break;
1018 case MLX4_CMD_MAP_ICM:
1019 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
1020 tc, ts, (unsigned long long) virt - (ts << 10));
1021 break;
1022 }
1023
1024out:
1025 mlx4_free_cmd_mailbox(dev, mailbox);
1026 return err;
1027}
1028
1029int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1030{
1031 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1032}
1033
1034int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1035{
f9baff50
JM		 1036 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1037 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1038}
1039
1040
1041int mlx4_RUN_FW(struct mlx4_dev *dev)
1042{
f9baff50
JM		 1043 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1044 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1045}
1046
1047int mlx4_QUERY_FW(struct mlx4_dev *dev)
1048{
1049 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1050 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1051 struct mlx4_cmd_mailbox *mailbox;
1052 u32 *outbox;
1053 int err = 0;
1054 u64 fw_ver;
fe40900f 1055 u16 cmd_if_rev;
225c7b1f
RD		 1056 u8 lg;
1057
1058#define QUERY_FW_OUT_SIZE 0x100
1059#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1060#define QUERY_FW_PPF_ID 0x09
fe40900f 1061#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1062#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1063#define QUERY_FW_ERR_START_OFFSET 0x30
1064#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1065#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1066
1067#define QUERY_FW_SIZE_OFFSET 0x00
1068#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1069#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1070
5cc914f1
MA		 1071#define QUERY_FW_COMM_BASE_OFFSET 0x40
1072#define QUERY_FW_COMM_BAR_OFFSET 0x48
1073
ddd8a6c1
EE		 1074#define QUERY_FW_CLOCK_OFFSET 0x50
1075#define QUERY_FW_CLOCK_BAR 0x58
1076
225c7b1f
RD		 1077 mailbox = mlx4_alloc_cmd_mailbox(dev);
1078 if (IS_ERR(mailbox))
1079 return PTR_ERR(mailbox);
1080 outbox = mailbox->buf;
1081
1082 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1083 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1084 if (err)
1085 goto out;
1086
1087 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1088 /*
3e1db334 1089 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1090 * version, so swap here.
1091 */
1092 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1093 ((fw_ver & 0xffff0000ull) >> 16) |
1094 ((fw_ver & 0x0000ffffull) << 16);
1095
752a50ca
JM		 1096 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1097 dev->caps.function = lg;
1098
b91cb3eb
JM		 1099 if (mlx4_is_slave(dev))
1100 goto out;
1101
5cc914f1 1102
fe40900f 1103 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1104 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1105 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 1106 mlx4_err(dev, "Installed FW has unsupported "
1107 "command interface revision %d.\n",
1108 cmd_if_rev);
1109 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1110 (int) (dev->caps.fw_ver >> 32),
1111 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1112 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 1113 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
1114 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1115 err = -ENODEV;
1116 goto out;
1117 }
1118
5ae2a7a8
RD		 1119 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1120 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1121
225c7b1f
RD		 1122 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1123 cmd->max_cmds = 1 << lg;
1124
fe40900f 1125 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1126 (int) (dev->caps.fw_ver >> 32),
1127 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1128 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1129 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1130
1131 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1132 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1133 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1134 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1135
1136 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1137 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1138
1139 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1140 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1141 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1142 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1143
5cc914f1
MA		 1144 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1145 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1146 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1147 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1148 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1149 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1150
ddd8a6c1
EE		 1151 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1152 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1153 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1154 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1155 fw->clock_bar, fw->clock_offset);
1156
225c7b1f
RD		 1157 /*
1158 * Round up number of system pages needed in case
1159 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1160 */
1161 fw->fw_pages =
1162 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1163 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1164
1165 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1166 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1167
1168out:
1169 mlx4_free_cmd_mailbox(dev, mailbox);
1170 return err;
1171}
1172
b91cb3eb
JM		 1173int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1174 struct mlx4_vhcr *vhcr,
1175 struct mlx4_cmd_mailbox *inbox,
1176 struct mlx4_cmd_mailbox *outbox,
1177 struct mlx4_cmd_info *cmd)
1178{
1179 u8 *outbuf;
1180 int err;
1181
1182 outbuf = outbox->buf;
1183 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1184 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1185 if (err)
1186 return err;
1187
752a50ca
JM		 1188 /* for slaves, set pci PPF ID to invalid and zero out everything
1189 * else except FW version */
b91cb3eb
JM		 1190 outbuf[0] = outbuf[1] = 0;
1191 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1192 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1193
b91cb3eb
JM		 1194 return 0;
1195}
1196
225c7b1f
RD		 1197static void get_board_id(void *vsd, char *board_id)
1198{
1199 int i;
1200
1201#define VSD_OFFSET_SIG1 0x00
1202#define VSD_OFFSET_SIG2 0xde
1203#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1204#define VSD_OFFSET_TS_BOARD_ID 0x20
1205
1206#define VSD_SIGNATURE_TOPSPIN 0x5ad
1207
1208 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1209
1210 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1211 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1212 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1213 } else {
1214 /*
1215 * The board ID is a string but the firmware byte
1216 * swaps each 4-byte word before passing it back to
1217 * us. Therefore we need to swab it before printing.
1218 */
1219 for (i = 0; i < 4; ++i)
1220 ((u32 *) board_id)[i] =
1221 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1222 }
1223}
1224
1225int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1226{
1227 struct mlx4_cmd_mailbox *mailbox;
1228 u32 *outbox;
1229 int err;
1230
1231#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1232#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1233#define QUERY_ADAPTER_VSD_OFFSET 0x20
1234
1235 mailbox = mlx4_alloc_cmd_mailbox(dev);
1236 if (IS_ERR(mailbox))
1237 return PTR_ERR(mailbox);
1238 outbox = mailbox->buf;
1239
1240 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1241 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1242 if (err)
1243 goto out;
1244
225c7b1f
RD		 1245 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1246
1247 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1248 adapter->board_id);
1249
1250out:
1251 mlx4_free_cmd_mailbox(dev, mailbox);
1252 return err;
1253}
1254
1255int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1256{
1257 struct mlx4_cmd_mailbox *mailbox;
1258 __be32 *inbox;
1259 int err;
1260
1261#define INIT_HCA_IN_SIZE 0x200
1262#define INIT_HCA_VERSION_OFFSET 0x000
1263#define INIT_HCA_VERSION 2
c57e20dc 1264#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1265#define INIT_HCA_FLAGS_OFFSET 0x014
1266#define INIT_HCA_QPC_OFFSET 0x020
1267#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1268#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1269#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1270#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1271#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1272#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1273#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
225c7b1f
RD		 1274#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1275#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1276#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1277#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1278#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1279#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1280#define INIT_HCA_MCAST_OFFSET 0x0c0
1281#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1282#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1283#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1284#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1285#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1286#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1287#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1288#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1289#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1290#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1291#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1292#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1293#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1294#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1295#define INIT_HCA_TPT_OFFSET 0x0f0
1296#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1297#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1298#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1299#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1300#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1301#define INIT_HCA_UAR_OFFSET 0x120
1302#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1303#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1304
1305 mailbox = mlx4_alloc_cmd_mailbox(dev);
1306 if (IS_ERR(mailbox))
1307 return PTR_ERR(mailbox);
1308 inbox = mailbox->buf;
1309
225c7b1f
RD		 1310 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1311
c57e20dc
EC		 1312 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1313 (ilog2(cache_line_size()) - 4) << 5;
1314
225c7b1f
RD		 1315#if defined(__LITTLE_ENDIAN)
1316 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1317#elif defined(__BIG_ENDIAN)
1318 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1319#else
1320#error Host endianness not defined
1321#endif
1322 /* Check port for UD address vector: */
1323 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1324
8ff095ec
EC		 1325 /* Enable IPoIB checksumming if we can: */
1326 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1327 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1328
51f5f0ee
JM		 1329 /* Enable QoS support if module parameter set */
1330 if (enable_qos)
1331 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1332
f2a3f6a3
OG		 1333 /* enable counters */
1334 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1335 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1336
08ff3235
OG		 1337 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1338 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1339 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1340 dev->caps.eqe_size = 64;
1341 dev->caps.eqe_factor = 1;
1342 } else {
1343 dev->caps.eqe_size = 32;
1344 dev->caps.eqe_factor = 0;
1345 }
1346
1347 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1348 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1349 dev->caps.cqe_size = 64;
1350 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1351 } else {
1352 dev->caps.cqe_size = 32;
1353 }
1354
225c7b1f
RD		 1355 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1356
1357 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1358 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1359 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1360 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1361 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1362 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1363 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1364 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1365 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1366 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1367 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1368 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1369
0ff1fb65
HHZ		 1370 /* steering attributes */
1371 if (dev->caps.steering_mode ==
1372 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1373 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1374 cpu_to_be32(1 <<
1375 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1376
1377 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1378 MLX4_PUT(inbox, param->log_mc_entry_sz,
1379 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1380 MLX4_PUT(inbox, param->log_mc_table_sz,
1381 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1382 /* Enable Ethernet flow steering
1383 * with udp unicast and tcp unicast
1384 */
23537b73 1385 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1386 INIT_HCA_FS_ETH_BITS_OFFSET);
1387 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1388 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1389 /* Enable IPoIB flow steering
1390 * with udp unicast and tcp unicast
1391 */
23537b73 1392 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1393 INIT_HCA_FS_IB_BITS_OFFSET);
1394 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1395 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1396 } else {
1397 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1398 MLX4_PUT(inbox, param->log_mc_entry_sz,
1399 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1400 MLX4_PUT(inbox, param->log_mc_hash_sz,
1401 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1402 MLX4_PUT(inbox, param->log_mc_table_sz,
1403 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1404 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1405 MLX4_PUT(inbox, (u8) (1 << 3),
1406 INIT_HCA_UC_STEERING_OFFSET);
1407 }
225c7b1f
RD		 1408
1409 /* TPT attributes */
1410
1411 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1412 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1413 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1414 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1415 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1416
1417 /* UAR attributes */
1418
ab9c17a0 1419 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1420 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1421
f9baff50
JM		 1422 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1423 MLX4_CMD_NATIVE);
225c7b1f
RD		 1424
1425 if (err)
1426 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1427
1428 mlx4_free_cmd_mailbox(dev, mailbox);
1429 return err;
1430}
1431
ab9c17a0
JM		 1432int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1433 struct mlx4_init_hca_param *param)
1434{
1435 struct mlx4_cmd_mailbox *mailbox;
1436 __be32 *outbox;
7b8157be 1437 u32 dword_field;
ab9c17a0 1438 int err;
08ff3235 1439 u8 byte_field;
ab9c17a0
JM		 1440
1441#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1442#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1443
1444 mailbox = mlx4_alloc_cmd_mailbox(dev);
1445 if (IS_ERR(mailbox))
1446 return PTR_ERR(mailbox);
1447 outbox = mailbox->buf;
1448
1449 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1450 MLX4_CMD_QUERY_HCA,
1451 MLX4_CMD_TIME_CLASS_B,
1452 !mlx4_is_slave(dev));
1453 if (err)
1454 goto out;
1455
1456 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1457 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1458
1459 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1460
1461 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1462 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1463 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1464 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1465 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1466 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1467 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1468 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1469 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1470 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1471 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1472 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1473
7b8157be
JM		 1474 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1475 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1476 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1477 } else {
1478 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1479 if (byte_field & 0x8)
1480 param->steering_mode = MLX4_STEERING_MODE_B0;
1481 else
1482 param->steering_mode = MLX4_STEERING_MODE_A0;
1483 }
0ff1fb65 1484 /* steering attributes */
7b8157be 1485 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1486 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1487 MLX4_GET(param->log_mc_entry_sz, outbox,
1488 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1489 MLX4_GET(param->log_mc_table_sz, outbox,
1490 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1491 } else {
1492 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1493 MLX4_GET(param->log_mc_entry_sz, outbox,
1494 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1495 MLX4_GET(param->log_mc_hash_sz, outbox,
1496 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1497 MLX4_GET(param->log_mc_table_sz, outbox,
1498 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1499 }
ab9c17a0 1500
08ff3235
OG		 1501 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1502 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1503 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1504 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1505 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1506 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1507
ab9c17a0
JM		 1508 /* TPT attributes */
1509
1510 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1511 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1512 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1513 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1514 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1515
1516 /* UAR attributes */
1517
1518 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1519 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1520
1521out:
1522 mlx4_free_cmd_mailbox(dev, mailbox);
1523
1524 return err;
1525}
1526
980e9001
JM		 1527/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1528 * and real QP0 are active, so that the paravirtualized QP0 is ready
1529 * to operate */
1530static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1531{
1532 struct mlx4_priv *priv = mlx4_priv(dev);
1533 /* irrelevant if not infiniband */
1534 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1535 priv->mfunc.master.qp0_state[port].qp0_active)
1536 return 1;
1537 return 0;
1538}
1539
5cc914f1
MA		 1540int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1541 struct mlx4_vhcr *vhcr,
1542 struct mlx4_cmd_mailbox *inbox,
1543 struct mlx4_cmd_mailbox *outbox,
1544 struct mlx4_cmd_info *cmd)
1545{
1546 struct mlx4_priv *priv = mlx4_priv(dev);
1547 int port = vhcr->in_modifier;
1548 int err;
1549
1550 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1551 return 0;
1552
980e9001
JM		 1553 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1554 /* Enable port only if it was previously disabled */
1555 if (!priv->mfunc.master.init_port_ref[port]) {
1556 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1557 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1558 if (err)
1559 return err;
1560 }
1561 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1562 } else {
1563 if (slave == mlx4_master_func_num(dev)) {
1564 if (check_qp0_state(dev, slave, port) &&
1565 !priv->mfunc.master.qp0_state[port].port_active) {
1566 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1567 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1568 if (err)
1569 return err;
1570 priv->mfunc.master.qp0_state[port].port_active = 1;
1571 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1572 }
1573 } else
1574 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1575 }
1576 ++priv->mfunc.master.init_port_ref[port];
1577 return 0;
1578}
1579
5ae2a7a8 1580int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1581{
1582 struct mlx4_cmd_mailbox *mailbox;
1583 u32 *inbox;
1584 int err;
1585 u32 flags;
5ae2a7a8 1586 u16 field;
225c7b1f 1587
5ae2a7a8 1588 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1589#define INIT_PORT_IN_SIZE 256
1590#define INIT_PORT_FLAGS_OFFSET 0x00
1591#define INIT_PORT_FLAG_SIG (1 << 18)
1592#define INIT_PORT_FLAG_NG (1 << 17)
1593#define INIT_PORT_FLAG_G0 (1 << 16)
1594#define INIT_PORT_VL_SHIFT 4
1595#define INIT_PORT_PORT_WIDTH_SHIFT 8
1596#define INIT_PORT_MTU_OFFSET 0x04
1597#define INIT_PORT_MAX_GID_OFFSET 0x06
1598#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1599#define INIT_PORT_GUID0_OFFSET 0x10
1600#define INIT_PORT_NODE_GUID_OFFSET 0x18
1601#define INIT_PORT_SI_GUID_OFFSET 0x20
1602
5ae2a7a8
RD		 1603 mailbox = mlx4_alloc_cmd_mailbox(dev);
1604 if (IS_ERR(mailbox))
1605 return PTR_ERR(mailbox);
1606 inbox = mailbox->buf;
225c7b1f 1607
5ae2a7a8
RD		 1608 flags = 0;
1609 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1610 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1611 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1612
b79acb49 1613 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1614 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1615 field = dev->caps.gid_table_len[port];
1616 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1617 field = dev->caps.pkey_table_len[port];
1618 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1619
5ae2a7a8 1620 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1621 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1622
5ae2a7a8
RD		 1623 mlx4_free_cmd_mailbox(dev, mailbox);
1624 } else
1625 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1626 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1627
1628 return err;
1629}
1630EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1631
5cc914f1
MA		 1632int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1633 struct mlx4_vhcr *vhcr,
1634 struct mlx4_cmd_mailbox *inbox,
1635 struct mlx4_cmd_mailbox *outbox,
1636 struct mlx4_cmd_info *cmd)
1637{
1638 struct mlx4_priv *priv = mlx4_priv(dev);
1639 int port = vhcr->in_modifier;
1640 int err;
1641
1642 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1643 (1 << port)))
1644 return 0;
1645
980e9001
JM		 1646 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1647 if (priv->mfunc.master.init_port_ref[port] == 1) {
1648 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1649 1000, MLX4_CMD_NATIVE);
1650 if (err)
1651 return err;
1652 }
1653 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1654 } else {
1655 /* infiniband port */
1656 if (slave == mlx4_master_func_num(dev)) {
1657 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1658 priv->mfunc.master.qp0_state[port].port_active) {
1659 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1660 1000, MLX4_CMD_NATIVE);
1661 if (err)
1662 return err;
1663 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1664 priv->mfunc.master.qp0_state[port].port_active = 0;
1665 }
1666 } else
1667 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1668 }
5cc914f1
MA		 1669 --priv->mfunc.master.init_port_ref[port];
1670 return 0;
1671}
1672
225c7b1f
RD		 1673int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1674{
f9baff50
JM		 1675 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1676 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1677}
1678EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1679
1680int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1681{
f9baff50
JM		 1682 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1683 MLX4_CMD_NATIVE);
225c7b1f
RD		 1684}
1685
1686int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1687{
1688 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1689 MLX4_CMD_SET_ICM_SIZE,
f9baff50 1690 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1691 if (ret)
1692 return ret;
1693
1694 /*
1695 * Round up number of system pages needed in case
1696 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1697 */
1698 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1699 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1700
1701 return 0;
1702}
1703
1704int mlx4_NOP(struct mlx4_dev *dev)
1705{
1706 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 1707 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 1708}
14c07b13
YP		 1709
1710#define MLX4_WOL_SETUP_MODE (5 << 28)
1711int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1712{
1713 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1714
1715 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 1716 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1717 MLX4_CMD_NATIVE);
14c07b13
YP		 1718}
1719EXPORT_SYMBOL_GPL(mlx4_wol_read);
1720
1721int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1722{
1723 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1724
1725 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 1726 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 1727}
1728EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 1729
1730enum {
1731 ADD_TO_MCG = 0x26,
1732};
1733
1734
1735void mlx4_opreq_action(struct work_struct *work)
1736{
1737 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
1738 opreq_task);
1739 struct mlx4_dev *dev = &priv->dev;
1740 int num_tasks = atomic_read(&priv->opreq_count);
1741 struct mlx4_cmd_mailbox *mailbox;
1742 struct mlx4_mgm *mgm;
1743 u32 *outbox;
1744 u32 modifier;
1745 u16 token;
fe6f700d
YP		 1746 u16 type;
1747 int err;
1748 u32 num_qps;
1749 struct mlx4_qp qp;
1750 int i;
1751 u8 rem_mcg;
1752 u8 prot;
1753
1754#define GET_OP_REQ_MODIFIER_OFFSET 0x08
1755#define GET_OP_REQ_TOKEN_OFFSET 0x14
1756#define GET_OP_REQ_TYPE_OFFSET 0x1a
1757#define GET_OP_REQ_DATA_OFFSET 0x20
1758
1759 mailbox = mlx4_alloc_cmd_mailbox(dev);
1760 if (IS_ERR(mailbox)) {
1761 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
1762 return;
1763 }
1764 outbox = mailbox->buf;
1765
1766 while (num_tasks) {
1767 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1768 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1769 MLX4_CMD_NATIVE);
1770 if (err) {
6d3be300 1771 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 1772 err);
1773 return;
1774 }
1775 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
1776 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
1777 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 1778 type &= 0xfff;
1779
1780 switch (type) {
1781 case ADD_TO_MCG:
1782 if (dev->caps.steering_mode ==
1783 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1784 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
1785 err = EPERM;
1786 break;
1787 }
1788 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
1789 GET_OP_REQ_DATA_OFFSET);
1790 num_qps = be32_to_cpu(mgm->members_count) &
1791 MGM_QPN_MASK;
1792 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
1793 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
1794
1795 for (i = 0; i < num_qps; i++) {
1796 qp.qpn = be32_to_cpu(mgm->qp[i]);
1797 if (rem_mcg)
1798 err = mlx4_multicast_detach(dev, &qp,
1799 mgm->gid,
1800 prot, 0);
1801 else
1802 err = mlx4_multicast_attach(dev, &qp,
1803 mgm->gid,
1804 mgm->gid[5]
1805 , 0, prot,
1806 NULL);
1807 if (err)
1808 break;
1809 }
1810 break;
1811 default:
1812 mlx4_warn(dev, "Bad type for required operation\n");
1813 err = EINVAL;
1814 break;
1815 }
1816 err = mlx4_cmd(dev, 0, ((u32) err | cpu_to_be32(token) << 16),
1817 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1818 MLX4_CMD_NATIVE);
1819 if (err) {
1820 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
1821 err);
1822 goto out;
1823 }
1824 memset(outbox, 0, 0xffc);
1825 num_tasks = atomic_dec_return(&priv->opreq_count);
1826 }
1827
1828out:
1829 mlx4_free_cmd_mailbox(dev, mailbox);
1830}
Linux 6.x block layer and io_uring tree(s)