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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Mellanox Technologies. All rights reserved. | |
4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
35 | #include <linux/mlx4/cmd.h> | |
36 | ||
37 | #include "fw.h" | |
38 | #include "icm.h" | |
39 | ||
fe40900f | 40 | enum { |
5ae2a7a8 RD |
41 | MLX4_COMMAND_INTERFACE_MIN_REV = 2, |
42 | MLX4_COMMAND_INTERFACE_MAX_REV = 3, | |
43 | MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, | |
fe40900f RD |
44 | }; |
45 | ||
225c7b1f RD |
46 | extern void __buggy_use_of_MLX4_GET(void); |
47 | extern void __buggy_use_of_MLX4_PUT(void); | |
48 | ||
49 | #define MLX4_GET(dest, source, offset) \ | |
50 | do { \ | |
51 | void *__p = (char *) (source) + (offset); \ | |
52 | switch (sizeof (dest)) { \ | |
53 | case 1: (dest) = *(u8 *) __p; break; \ | |
54 | case 2: (dest) = be16_to_cpup(__p); break; \ | |
55 | case 4: (dest) = be32_to_cpup(__p); break; \ | |
56 | case 8: (dest) = be64_to_cpup(__p); break; \ | |
57 | default: __buggy_use_of_MLX4_GET(); \ | |
58 | } \ | |
59 | } while (0) | |
60 | ||
61 | #define MLX4_PUT(dest, source, offset) \ | |
62 | do { \ | |
63 | void *__d = ((char *) (dest) + (offset)); \ | |
64 | switch (sizeof(source)) { \ | |
65 | case 1: *(u8 *) __d = (source); break; \ | |
66 | case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ | |
67 | case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ | |
68 | case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ | |
69 | default: __buggy_use_of_MLX4_PUT(); \ | |
70 | } \ | |
71 | } while (0) | |
72 | ||
73 | static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags) | |
74 | { | |
75 | static const char *fname[] = { | |
76 | [ 0] = "RC transport", | |
77 | [ 1] = "UC transport", | |
78 | [ 2] = "UD transport", | |
79 | [ 3] = "SRC transport", | |
80 | [ 4] = "reliable multicast", | |
81 | [ 5] = "FCoIB support", | |
82 | [ 6] = "SRQ support", | |
83 | [ 7] = "IPoIB checksum offload", | |
84 | [ 8] = "P_Key violation counter", | |
85 | [ 9] = "Q_Key violation counter", | |
86 | [10] = "VMM", | |
87 | [16] = "MW support", | |
88 | [17] = "APM support", | |
89 | [18] = "Atomic ops support", | |
90 | [19] = "Raw multicast support", | |
91 | [20] = "Address vector port checking support", | |
92 | [21] = "UD multicast support", | |
93 | [24] = "Demand paging support", | |
94 | [25] = "Router support" | |
95 | }; | |
96 | int i; | |
97 | ||
98 | mlx4_dbg(dev, "DEV_CAP flags:\n"); | |
23c15c21 | 99 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
225c7b1f RD |
100 | if (fname[i] && (flags & (1 << i))) |
101 | mlx4_dbg(dev, " %s\n", fname[i]); | |
102 | } | |
103 | ||
104 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) | |
105 | { | |
106 | struct mlx4_cmd_mailbox *mailbox; | |
107 | u32 *outbox; | |
108 | u8 field; | |
109 | u16 size; | |
110 | u16 stat_rate; | |
111 | int err; | |
5ae2a7a8 | 112 | int i; |
225c7b1f RD |
113 | |
114 | #define QUERY_DEV_CAP_OUT_SIZE 0x100 | |
115 | #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 | |
116 | #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 | |
117 | #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 | |
118 | #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 | |
119 | #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 | |
120 | #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 | |
121 | #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 | |
122 | #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 | |
123 | #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 | |
124 | #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a | |
125 | #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b | |
126 | #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d | |
127 | #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e | |
128 | #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f | |
129 | #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 | |
130 | #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 | |
131 | #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 | |
132 | #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 | |
133 | #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 | |
134 | #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 | |
135 | #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b | |
136 | #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f | |
137 | #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 | |
138 | #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 | |
139 | #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 | |
140 | #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 | |
149983af | 141 | #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 |
225c7b1f RD |
142 | #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b |
143 | #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c | |
144 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f | |
145 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 | |
146 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 | |
147 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 | |
148 | #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b | |
149 | #define QUERY_DEV_CAP_BF_OFFSET 0x4c | |
150 | #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d | |
151 | #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e | |
152 | #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f | |
153 | #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 | |
154 | #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 | |
155 | #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 | |
156 | #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 | |
157 | #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 | |
158 | #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 | |
159 | #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 | |
160 | #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 | |
161 | #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 | |
162 | #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 | |
163 | #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 | |
164 | #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 | |
165 | #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 | |
166 | #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 | |
167 | #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a | |
168 | #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c | |
169 | #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e | |
170 | #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 | |
171 | #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 | |
172 | #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x97 | |
173 | #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 | |
174 | #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 | |
175 | ||
176 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
177 | if (IS_ERR(mailbox)) | |
178 | return PTR_ERR(mailbox); | |
179 | outbox = mailbox->buf; | |
180 | ||
181 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, | |
182 | MLX4_CMD_TIME_CLASS_A); | |
225c7b1f RD |
183 | if (err) |
184 | goto out; | |
185 | ||
186 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); | |
187 | dev_cap->reserved_qps = 1 << (field & 0xf); | |
188 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); | |
189 | dev_cap->max_qps = 1 << (field & 0x1f); | |
190 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); | |
191 | dev_cap->reserved_srqs = 1 << (field >> 4); | |
192 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); | |
193 | dev_cap->max_srqs = 1 << (field & 0x1f); | |
194 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); | |
195 | dev_cap->max_cq_sz = 1 << field; | |
196 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); | |
197 | dev_cap->reserved_cqs = 1 << (field & 0xf); | |
198 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); | |
199 | dev_cap->max_cqs = 1 << (field & 0x1f); | |
200 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); | |
201 | dev_cap->max_mpts = 1 << (field & 0x3f); | |
202 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); | |
203 | dev_cap->reserved_eqs = 1 << (field & 0xf); | |
204 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); | |
205 | dev_cap->max_eqs = 1 << (field & 0x7); | |
206 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); | |
207 | dev_cap->reserved_mtts = 1 << (field >> 4); | |
208 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); | |
209 | dev_cap->max_mrw_sz = 1 << field; | |
210 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); | |
211 | dev_cap->reserved_mrws = 1 << (field & 0xf); | |
212 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); | |
213 | dev_cap->max_mtt_seg = 1 << (field & 0x3f); | |
214 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); | |
215 | dev_cap->max_requester_per_qp = 1 << (field & 0x3f); | |
216 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); | |
217 | dev_cap->max_responder_per_qp = 1 << (field & 0x3f); | |
218 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); | |
219 | dev_cap->max_rdma_global = 1 << (field & 0x3f); | |
220 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); | |
221 | dev_cap->local_ca_ack_delay = field & 0x1f; | |
225c7b1f | 222 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
225c7b1f | 223 | dev_cap->num_ports = field & 0xf; |
149983af DB |
224 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); |
225 | dev_cap->max_msg_sz = 1 << (field & 0x1f); | |
225c7b1f RD |
226 | MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); |
227 | dev_cap->stat_rate_support = stat_rate; | |
225c7b1f RD |
228 | MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); |
229 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); | |
230 | dev_cap->reserved_uars = field >> 4; | |
231 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); | |
232 | dev_cap->uar_size = 1 << ((field & 0x3f) + 20); | |
233 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); | |
234 | dev_cap->min_page_sz = 1 << field; | |
235 | ||
236 | MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); | |
237 | if (field & 0x80) { | |
238 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); | |
239 | dev_cap->bf_reg_size = 1 << (field & 0x1f); | |
240 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); | |
241 | dev_cap->bf_regs_per_page = 1 << (field & 0x3f); | |
242 | mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", | |
243 | dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); | |
244 | } else { | |
245 | dev_cap->bf_reg_size = 0; | |
246 | mlx4_dbg(dev, "BlueFlame not available\n"); | |
247 | } | |
248 | ||
249 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); | |
250 | dev_cap->max_sq_sg = field; | |
251 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); | |
252 | dev_cap->max_sq_desc_sz = size; | |
253 | ||
254 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); | |
255 | dev_cap->max_qp_per_mcg = 1 << field; | |
256 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); | |
257 | dev_cap->reserved_mgms = field & 0xf; | |
258 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); | |
259 | dev_cap->max_mcgs = 1 << field; | |
260 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); | |
261 | dev_cap->reserved_pds = field >> 4; | |
262 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); | |
263 | dev_cap->max_pds = 1 << (field & 0x3f); | |
264 | ||
265 | MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); | |
266 | dev_cap->rdmarc_entry_sz = size; | |
267 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); | |
268 | dev_cap->qpc_entry_sz = size; | |
269 | MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); | |
270 | dev_cap->aux_entry_sz = size; | |
271 | MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); | |
272 | dev_cap->altc_entry_sz = size; | |
273 | MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); | |
274 | dev_cap->eqc_entry_sz = size; | |
275 | MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); | |
276 | dev_cap->cqc_entry_sz = size; | |
277 | MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); | |
278 | dev_cap->srq_entry_sz = size; | |
279 | MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); | |
280 | dev_cap->cmpt_entry_sz = size; | |
281 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); | |
282 | dev_cap->mtt_entry_sz = size; | |
283 | MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); | |
284 | dev_cap->dmpt_entry_sz = size; | |
285 | ||
286 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); | |
287 | dev_cap->max_srq_sz = 1 << field; | |
288 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); | |
289 | dev_cap->max_qp_sz = 1 << field; | |
290 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); | |
291 | dev_cap->resize_srq = field & 1; | |
292 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); | |
293 | dev_cap->max_rq_sg = field; | |
294 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); | |
295 | dev_cap->max_rq_desc_sz = size; | |
296 | ||
297 | MLX4_GET(dev_cap->bmme_flags, outbox, | |
298 | QUERY_DEV_CAP_BMME_FLAGS_OFFSET); | |
299 | MLX4_GET(dev_cap->reserved_lkey, outbox, | |
300 | QUERY_DEV_CAP_RSVD_LKEY_OFFSET); | |
301 | MLX4_GET(dev_cap->max_icm_sz, outbox, | |
302 | QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); | |
303 | ||
5ae2a7a8 RD |
304 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
305 | for (i = 1; i <= dev_cap->num_ports; ++i) { | |
306 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); | |
307 | dev_cap->max_vl[i] = field >> 4; | |
308 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); | |
309 | dev_cap->max_mtu[i] = field >> 4; | |
310 | dev_cap->max_port_width[i] = field & 0xf; | |
311 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); | |
312 | dev_cap->max_gids[i] = 1 << (field & 0xf); | |
313 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); | |
314 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | |
315 | } | |
316 | } else { | |
317 | #define QUERY_PORT_MTU_OFFSET 0x01 | |
318 | #define QUERY_PORT_WIDTH_OFFSET 0x06 | |
319 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 | |
320 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b | |
321 | ||
322 | for (i = 1; i <= dev_cap->num_ports; ++i) { | |
323 | err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, | |
324 | MLX4_CMD_TIME_CLASS_B); | |
325 | if (err) | |
326 | goto out; | |
327 | ||
328 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); | |
329 | dev_cap->max_mtu[i] = field & 0xf; | |
330 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); | |
331 | dev_cap->max_port_width[i] = field & 0xf; | |
332 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); | |
333 | dev_cap->max_gids[i] = 1 << (field >> 4); | |
334 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | |
335 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); | |
336 | dev_cap->max_vl[i] = field & 0xf; | |
337 | } | |
338 | } | |
339 | ||
225c7b1f RD |
340 | if (dev_cap->bmme_flags & 1) |
341 | mlx4_dbg(dev, "Base MM extensions: yes " | |
342 | "(flags %d, rsvd L_Key %08x)\n", | |
343 | dev_cap->bmme_flags, dev_cap->reserved_lkey); | |
344 | else | |
345 | mlx4_dbg(dev, "Base MM extensions: no\n"); | |
346 | ||
347 | /* | |
348 | * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then | |
349 | * we can't use any EQs whose doorbell falls on that page, | |
350 | * even if the EQ itself isn't reserved. | |
351 | */ | |
352 | dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, | |
353 | dev_cap->reserved_eqs); | |
354 | ||
355 | mlx4_dbg(dev, "Max ICM size %lld MB\n", | |
356 | (unsigned long long) dev_cap->max_icm_sz >> 20); | |
357 | mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", | |
358 | dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); | |
359 | mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", | |
360 | dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); | |
361 | mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", | |
362 | dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); | |
363 | mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", | |
364 | dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); | |
365 | mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", | |
366 | dev_cap->reserved_mrws, dev_cap->reserved_mtts); | |
367 | mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", | |
368 | dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); | |
369 | mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", | |
370 | dev_cap->max_pds, dev_cap->reserved_mgms); | |
371 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", | |
372 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); | |
373 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", | |
5ae2a7a8 RD |
374 | dev_cap->local_ca_ack_delay, 128 << dev_cap->max_mtu[1], |
375 | dev_cap->max_port_width[1]); | |
225c7b1f RD |
376 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", |
377 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); | |
378 | mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", | |
379 | dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); | |
380 | ||
381 | dump_dev_cap_flags(dev, dev_cap->flags); | |
382 | ||
383 | out: | |
384 | mlx4_free_cmd_mailbox(dev, mailbox); | |
385 | return err; | |
386 | } | |
387 | ||
388 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) | |
389 | { | |
390 | struct mlx4_cmd_mailbox *mailbox; | |
391 | struct mlx4_icm_iter iter; | |
392 | __be64 *pages; | |
393 | int lg; | |
394 | int nent = 0; | |
395 | int i; | |
396 | int err = 0; | |
397 | int ts = 0, tc = 0; | |
398 | ||
399 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
400 | if (IS_ERR(mailbox)) | |
401 | return PTR_ERR(mailbox); | |
402 | memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); | |
403 | pages = mailbox->buf; | |
404 | ||
405 | for (mlx4_icm_first(icm, &iter); | |
406 | !mlx4_icm_last(&iter); | |
407 | mlx4_icm_next(&iter)) { | |
408 | /* | |
409 | * We have to pass pages that are aligned to their | |
410 | * size, so find the least significant 1 in the | |
411 | * address or size and use that as our log2 size. | |
412 | */ | |
413 | lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; | |
414 | if (lg < MLX4_ICM_PAGE_SHIFT) { | |
415 | mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", | |
416 | MLX4_ICM_PAGE_SIZE, | |
417 | (unsigned long long) mlx4_icm_addr(&iter), | |
418 | mlx4_icm_size(&iter)); | |
419 | err = -EINVAL; | |
420 | goto out; | |
421 | } | |
422 | ||
423 | for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { | |
424 | if (virt != -1) { | |
425 | pages[nent * 2] = cpu_to_be64(virt); | |
426 | virt += 1 << lg; | |
427 | } | |
428 | ||
429 | pages[nent * 2 + 1] = | |
430 | cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | | |
431 | (lg - MLX4_ICM_PAGE_SHIFT)); | |
432 | ts += 1 << (lg - 10); | |
433 | ++tc; | |
434 | ||
435 | if (++nent == MLX4_MAILBOX_SIZE / 16) { | |
436 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, | |
437 | MLX4_CMD_TIME_CLASS_B); | |
438 | if (err) | |
439 | goto out; | |
440 | nent = 0; | |
441 | } | |
442 | } | |
443 | } | |
444 | ||
445 | if (nent) | |
446 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B); | |
447 | if (err) | |
448 | goto out; | |
449 | ||
450 | switch (op) { | |
451 | case MLX4_CMD_MAP_FA: | |
452 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); | |
453 | break; | |
454 | case MLX4_CMD_MAP_ICM_AUX: | |
455 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); | |
456 | break; | |
457 | case MLX4_CMD_MAP_ICM: | |
458 | mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", | |
459 | tc, ts, (unsigned long long) virt - (ts << 10)); | |
460 | break; | |
461 | } | |
462 | ||
463 | out: | |
464 | mlx4_free_cmd_mailbox(dev, mailbox); | |
465 | return err; | |
466 | } | |
467 | ||
468 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) | |
469 | { | |
470 | return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); | |
471 | } | |
472 | ||
473 | int mlx4_UNMAP_FA(struct mlx4_dev *dev) | |
474 | { | |
475 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B); | |
476 | } | |
477 | ||
478 | ||
479 | int mlx4_RUN_FW(struct mlx4_dev *dev) | |
480 | { | |
481 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A); | |
482 | } | |
483 | ||
484 | int mlx4_QUERY_FW(struct mlx4_dev *dev) | |
485 | { | |
486 | struct mlx4_fw *fw = &mlx4_priv(dev)->fw; | |
487 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; | |
488 | struct mlx4_cmd_mailbox *mailbox; | |
489 | u32 *outbox; | |
490 | int err = 0; | |
491 | u64 fw_ver; | |
fe40900f | 492 | u16 cmd_if_rev; |
225c7b1f RD |
493 | u8 lg; |
494 | ||
495 | #define QUERY_FW_OUT_SIZE 0x100 | |
496 | #define QUERY_FW_VER_OFFSET 0x00 | |
fe40900f | 497 | #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a |
225c7b1f RD |
498 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f |
499 | #define QUERY_FW_ERR_START_OFFSET 0x30 | |
500 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 | |
501 | #define QUERY_FW_ERR_BAR_OFFSET 0x3c | |
502 | ||
503 | #define QUERY_FW_SIZE_OFFSET 0x00 | |
504 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 | |
505 | #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 | |
506 | ||
507 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
508 | if (IS_ERR(mailbox)) | |
509 | return PTR_ERR(mailbox); | |
510 | outbox = mailbox->buf; | |
511 | ||
512 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, | |
513 | MLX4_CMD_TIME_CLASS_A); | |
514 | if (err) | |
515 | goto out; | |
516 | ||
517 | MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); | |
518 | /* | |
3e1db334 | 519 | * FW subminor version is at more significant bits than minor |
225c7b1f RD |
520 | * version, so swap here. |
521 | */ | |
522 | dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | | |
523 | ((fw_ver & 0xffff0000ull) >> 16) | | |
524 | ((fw_ver & 0x0000ffffull) << 16); | |
525 | ||
fe40900f | 526 | MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); |
5ae2a7a8 RD |
527 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || |
528 | cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { | |
fe40900f RD |
529 | mlx4_err(dev, "Installed FW has unsupported " |
530 | "command interface revision %d.\n", | |
531 | cmd_if_rev); | |
532 | mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", | |
533 | (int) (dev->caps.fw_ver >> 32), | |
534 | (int) (dev->caps.fw_ver >> 16) & 0xffff, | |
535 | (int) dev->caps.fw_ver & 0xffff); | |
5ae2a7a8 RD |
536 | mlx4_err(dev, "This driver version supports only revisions %d to %d.\n", |
537 | MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); | |
fe40900f RD |
538 | err = -ENODEV; |
539 | goto out; | |
540 | } | |
541 | ||
5ae2a7a8 RD |
542 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) |
543 | dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; | |
544 | ||
225c7b1f RD |
545 | MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
546 | cmd->max_cmds = 1 << lg; | |
547 | ||
fe40900f | 548 | mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", |
225c7b1f RD |
549 | (int) (dev->caps.fw_ver >> 32), |
550 | (int) (dev->caps.fw_ver >> 16) & 0xffff, | |
551 | (int) dev->caps.fw_ver & 0xffff, | |
fe40900f | 552 | cmd_if_rev, cmd->max_cmds); |
225c7b1f RD |
553 | |
554 | MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); | |
555 | MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); | |
556 | MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); | |
557 | fw->catas_bar = (fw->catas_bar >> 6) * 2; | |
558 | ||
559 | mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", | |
560 | (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); | |
561 | ||
562 | MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); | |
563 | MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); | |
564 | MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); | |
565 | fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; | |
566 | ||
567 | mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); | |
568 | ||
569 | /* | |
570 | * Round up number of system pages needed in case | |
571 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. | |
572 | */ | |
573 | fw->fw_pages = | |
574 | ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> | |
575 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); | |
576 | ||
577 | mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", | |
578 | (unsigned long long) fw->clr_int_base, fw->clr_int_bar); | |
579 | ||
580 | out: | |
581 | mlx4_free_cmd_mailbox(dev, mailbox); | |
582 | return err; | |
583 | } | |
584 | ||
585 | static void get_board_id(void *vsd, char *board_id) | |
586 | { | |
587 | int i; | |
588 | ||
589 | #define VSD_OFFSET_SIG1 0x00 | |
590 | #define VSD_OFFSET_SIG2 0xde | |
591 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 | |
592 | #define VSD_OFFSET_TS_BOARD_ID 0x20 | |
593 | ||
594 | #define VSD_SIGNATURE_TOPSPIN 0x5ad | |
595 | ||
596 | memset(board_id, 0, MLX4_BOARD_ID_LEN); | |
597 | ||
598 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && | |
599 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { | |
600 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); | |
601 | } else { | |
602 | /* | |
603 | * The board ID is a string but the firmware byte | |
604 | * swaps each 4-byte word before passing it back to | |
605 | * us. Therefore we need to swab it before printing. | |
606 | */ | |
607 | for (i = 0; i < 4; ++i) | |
608 | ((u32 *) board_id)[i] = | |
609 | swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); | |
610 | } | |
611 | } | |
612 | ||
613 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) | |
614 | { | |
615 | struct mlx4_cmd_mailbox *mailbox; | |
616 | u32 *outbox; | |
617 | int err; | |
618 | ||
619 | #define QUERY_ADAPTER_OUT_SIZE 0x100 | |
620 | #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00 | |
621 | #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04 | |
622 | #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08 | |
623 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 | |
624 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 | |
625 | ||
626 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
627 | if (IS_ERR(mailbox)) | |
628 | return PTR_ERR(mailbox); | |
629 | outbox = mailbox->buf; | |
630 | ||
631 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, | |
632 | MLX4_CMD_TIME_CLASS_A); | |
633 | if (err) | |
634 | goto out; | |
635 | ||
636 | MLX4_GET(adapter->vendor_id, outbox, QUERY_ADAPTER_VENDOR_ID_OFFSET); | |
637 | MLX4_GET(adapter->device_id, outbox, QUERY_ADAPTER_DEVICE_ID_OFFSET); | |
638 | MLX4_GET(adapter->revision_id, outbox, QUERY_ADAPTER_REVISION_ID_OFFSET); | |
639 | MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); | |
640 | ||
641 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, | |
642 | adapter->board_id); | |
643 | ||
644 | out: | |
645 | mlx4_free_cmd_mailbox(dev, mailbox); | |
646 | return err; | |
647 | } | |
648 | ||
649 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) | |
650 | { | |
651 | struct mlx4_cmd_mailbox *mailbox; | |
652 | __be32 *inbox; | |
653 | int err; | |
654 | ||
655 | #define INIT_HCA_IN_SIZE 0x200 | |
656 | #define INIT_HCA_VERSION_OFFSET 0x000 | |
657 | #define INIT_HCA_VERSION 2 | |
658 | #define INIT_HCA_FLAGS_OFFSET 0x014 | |
659 | #define INIT_HCA_QPC_OFFSET 0x020 | |
660 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) | |
661 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) | |
662 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) | |
663 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) | |
664 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) | |
665 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) | |
666 | #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) | |
667 | #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) | |
668 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) | |
669 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) | |
670 | #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) | |
671 | #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) | |
672 | #define INIT_HCA_MCAST_OFFSET 0x0c0 | |
673 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) | |
674 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) | |
675 | #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) | |
676 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) | |
677 | #define INIT_HCA_TPT_OFFSET 0x0f0 | |
678 | #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) | |
679 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) | |
680 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) | |
681 | #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) | |
682 | #define INIT_HCA_UAR_OFFSET 0x120 | |
683 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) | |
684 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) | |
685 | ||
686 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
687 | if (IS_ERR(mailbox)) | |
688 | return PTR_ERR(mailbox); | |
689 | inbox = mailbox->buf; | |
690 | ||
691 | memset(inbox, 0, INIT_HCA_IN_SIZE); | |
692 | ||
693 | *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; | |
694 | ||
695 | #if defined(__LITTLE_ENDIAN) | |
696 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); | |
697 | #elif defined(__BIG_ENDIAN) | |
698 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); | |
699 | #else | |
700 | #error Host endianness not defined | |
701 | #endif | |
702 | /* Check port for UD address vector: */ | |
703 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); | |
704 | ||
705 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ | |
706 | ||
707 | MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); | |
708 | MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); | |
709 | MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); | |
710 | MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); | |
711 | MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); | |
712 | MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); | |
713 | MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); | |
714 | MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); | |
715 | MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); | |
716 | MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); | |
717 | MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); | |
718 | MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); | |
719 | ||
720 | /* multicast attributes */ | |
721 | ||
722 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); | |
723 | MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
724 | MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET); | |
725 | MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); | |
726 | ||
727 | /* TPT attributes */ | |
728 | ||
729 | MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); | |
730 | MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); | |
731 | MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); | |
732 | MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); | |
733 | ||
734 | /* UAR attributes */ | |
735 | ||
736 | MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET); | |
737 | MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); | |
738 | ||
739 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 1000); | |
740 | ||
741 | if (err) | |
742 | mlx4_err(dev, "INIT_HCA returns %d\n", err); | |
743 | ||
744 | mlx4_free_cmd_mailbox(dev, mailbox); | |
745 | return err; | |
746 | } | |
747 | ||
5ae2a7a8 | 748 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) |
225c7b1f RD |
749 | { |
750 | struct mlx4_cmd_mailbox *mailbox; | |
751 | u32 *inbox; | |
752 | int err; | |
753 | u32 flags; | |
5ae2a7a8 | 754 | u16 field; |
225c7b1f | 755 | |
5ae2a7a8 | 756 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
225c7b1f RD |
757 | #define INIT_PORT_IN_SIZE 256 |
758 | #define INIT_PORT_FLAGS_OFFSET 0x00 | |
759 | #define INIT_PORT_FLAG_SIG (1 << 18) | |
760 | #define INIT_PORT_FLAG_NG (1 << 17) | |
761 | #define INIT_PORT_FLAG_G0 (1 << 16) | |
762 | #define INIT_PORT_VL_SHIFT 4 | |
763 | #define INIT_PORT_PORT_WIDTH_SHIFT 8 | |
764 | #define INIT_PORT_MTU_OFFSET 0x04 | |
765 | #define INIT_PORT_MAX_GID_OFFSET 0x06 | |
766 | #define INIT_PORT_MAX_PKEY_OFFSET 0x0a | |
767 | #define INIT_PORT_GUID0_OFFSET 0x10 | |
768 | #define INIT_PORT_NODE_GUID_OFFSET 0x18 | |
769 | #define INIT_PORT_SI_GUID_OFFSET 0x20 | |
770 | ||
5ae2a7a8 RD |
771 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
772 | if (IS_ERR(mailbox)) | |
773 | return PTR_ERR(mailbox); | |
774 | inbox = mailbox->buf; | |
225c7b1f | 775 | |
5ae2a7a8 | 776 | memset(inbox, 0, INIT_PORT_IN_SIZE); |
225c7b1f | 777 | |
5ae2a7a8 RD |
778 | flags = 0; |
779 | flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; | |
780 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; | |
781 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); | |
225c7b1f | 782 | |
5ae2a7a8 RD |
783 | field = 128 << dev->caps.mtu_cap[port]; |
784 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); | |
785 | field = dev->caps.gid_table_len[port]; | |
786 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); | |
787 | field = dev->caps.pkey_table_len[port]; | |
788 | MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); | |
225c7b1f | 789 | |
5ae2a7a8 RD |
790 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, |
791 | MLX4_CMD_TIME_CLASS_A); | |
225c7b1f | 792 | |
5ae2a7a8 RD |
793 | mlx4_free_cmd_mailbox(dev, mailbox); |
794 | } else | |
795 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
796 | MLX4_CMD_TIME_CLASS_A); | |
225c7b1f RD |
797 | |
798 | return err; | |
799 | } | |
800 | EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); | |
801 | ||
802 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) | |
803 | { | |
804 | return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000); | |
805 | } | |
806 | EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); | |
807 | ||
808 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) | |
809 | { | |
810 | return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000); | |
811 | } | |
812 | ||
813 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) | |
814 | { | |
815 | int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, | |
816 | MLX4_CMD_SET_ICM_SIZE, | |
817 | MLX4_CMD_TIME_CLASS_A); | |
818 | if (ret) | |
819 | return ret; | |
820 | ||
821 | /* | |
822 | * Round up number of system pages needed in case | |
823 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. | |
824 | */ | |
825 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> | |
826 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); | |
827 | ||
828 | return 0; | |
829 | } | |
830 | ||
831 | int mlx4_NOP(struct mlx4_dev *dev) | |
832 | { | |
833 | /* Input modifier of 0x1f means "finish as soon as possible." */ | |
834 | return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100); | |
835 | } |