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net/mlx4_core: Introduce ACCESS_REG CMD and eth_prot_ctrl dev cap
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
4d531aa8 94 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
540b3a39 112 [53] = "Port ETS Scheduler support",
4d531aa8 113 [55] = "Port link type sensing support",
00f5ce99 114 [59] = "Port management change event support",
08ff3235
OG		 115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
225c7b1f
RD		 117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 122 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
b3416f44
SP		 126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 131 [2] = "RSS XOR Hash Function support",
56cb4567 132 [3] = "Device managed flow steering support",
d998735f 133 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
b01978ca 136 [7] = "FSM (MAC anti-spoofing) support",
7ffdf726 137 [8] = "Dynamic QP updates support",
56cb4567 138 [9] = "Device managed flow steering IPoIB support",
114840c3 139 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
77507aa2
IS		 140 [11] = "MAD DEMUX (Secure-Host) support",
141 [12] = "Large cache line (>64B) CQE stride support",
adbc7ac5
SM		 142 [13] = "Large cache line (>64B) EQE stride support",
143 [14] = "Ethernet protocol control support"
b3416f44
SP		 144 };
145 int i;
146
147 for (i = 0; i < ARRAY_SIZE(fname); ++i)
148 if (fname[i] && (flags & (1LL << i)))
149 mlx4_dbg(dev, " %s\n", fname[i]);
150}
151
2d928651
VS		 152int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
153{
154 struct mlx4_cmd_mailbox *mailbox;
155 u32 *inbox;
156 int err = 0;
157
158#define MOD_STAT_CFG_IN_SIZE 0x100
159
160#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
161#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
162
163 mailbox = mlx4_alloc_cmd_mailbox(dev);
164 if (IS_ERR(mailbox))
165 return PTR_ERR(mailbox);
166 inbox = mailbox->buf;
167
2d928651
VS		 168 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
169 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
170
171 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 172 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 173
174 mlx4_free_cmd_mailbox(dev, mailbox);
175 return err;
176}
177
5cc914f1
MA		 178int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
179 struct mlx4_vhcr *vhcr,
180 struct mlx4_cmd_mailbox *inbox,
181 struct mlx4_cmd_mailbox *outbox,
182 struct mlx4_cmd_info *cmd)
183{
5a0d0a61 184 struct mlx4_priv *priv = mlx4_priv(dev);
99ec41d0
JM		 185 u8 field, port;
186 u32 size, proxy_qp, qkey;
5cc914f1
MA		 187 int err = 0;
188
189#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
190#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 191#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 192#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 193#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
194#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
195#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
196#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
197#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
198#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 199#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 200#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 201
eb456a68
JM		 202#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
203#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
204#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
205#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
206#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
207#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
208
105c320f
JM		 209#define QUERY_FUNC_CAP_FMR_FLAG 0x80
210#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
211#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 212#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
105c320f
JM		 213
214/* when opcode modifier = 1 */
5cc914f1 215#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
99ec41d0 216#define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
73e74ab4
HHZ		 217#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
218#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 219
47605df9
JM		 220#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
221#define QUERY_FUNC_CAP_QP0_PROXY 0x14
222#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
223#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
8e1a28e8 224#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
47605df9 225
73e74ab4
HHZ		 226#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
227#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
eb17711b 228#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
99ec41d0 229#define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
105c320f 230
73e74ab4 231#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
105c320f 232
5cc914f1 233 if (vhcr->op_modifier == 1) {
449fc488
MB		 234 struct mlx4_active_ports actv_ports =
235 mlx4_get_active_ports(dev, slave);
236 int converted_port = mlx4_slave_convert_port(
237 dev, slave, vhcr->in_modifier);
238
239 if (converted_port < 0)
240 return -EINVAL;
241
242 vhcr->in_modifier = converted_port;
449fc488
MB		 243 /* phys-port = logical-port */
244 field = vhcr->in_modifier -
245 find_first_bit(actv_ports.ports, dev->caps.num_ports);
47605df9
JM		 246 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
247
99ec41d0
JM		 248 port = vhcr->in_modifier;
249 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
250
251 /* Set nic_info bit to mark new fields support */
252 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
253
254 if (mlx4_vf_smi_enabled(dev, slave, port) &&
255 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
256 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
257 MLX4_PUT(outbox->buf, qkey,
258 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
259 }
260 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
261
47605df9 262 /* size is now the QP number */
99ec41d0 263 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
47605df9
JM		 264 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
265
266 size += 2;
267 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
268
99ec41d0
JM		 269 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
270 proxy_qp += 2;
271 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
47605df9 272
8e1a28e8
HHZ		 273 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
274 QUERY_FUNC_CAP_PHYS_PORT_ID);
275
5cc914f1 276 } else if (vhcr->op_modifier == 0) {
449fc488
MB		 277 struct mlx4_active_ports actv_ports =
278 mlx4_get_active_ports(dev, slave);
eb456a68
JM		 279 /* enable rdma and ethernet interfaces, and new quota locations */
280 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
281 QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1
MA		 282 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
283
449fc488
MB		 284 field = min(
285 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
286 dev->caps.num_ports);
5cc914f1
MA		 287 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
288
08ff3235 289 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 290 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
291
105c320f
JM		 292 field = 0; /* protected FMR support not available as yet */
293 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
294
5a0d0a61 295 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 296 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 297 size = dev->caps.num_qps;
298 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 299
5a0d0a61 300 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 301 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 302 size = dev->caps.num_srqs;
303 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 304
5a0d0a61 305 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 306 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 307 size = dev->caps.num_cqs;
308 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1
MA		 309
310 size = dev->caps.num_eqs;
311 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
312
313 size = dev->caps.reserved_eqs;
314 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
315
5a0d0a61 316 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 317 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 318 size = dev->caps.num_mpts;
319 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 320
5a0d0a61 321 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 322 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 323 size = dev->caps.num_mtts;
324 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 325
326 size = dev->caps.num_mgms + dev->caps.num_amgms;
327 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 328 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1
MA		 329
330 } else
331 err = -EINVAL;
332
333 return err;
334}
335
47605df9
JM		 336int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
337 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 338{
339 struct mlx4_cmd_mailbox *mailbox;
340 u32 *outbox;
47605df9 341 u8 field, op_modifier;
99ec41d0 342 u32 size, qkey;
eb456a68 343 int err = 0, quotas = 0;
5cc914f1 344
47605df9 345 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
5cc914f1
MA		 346
347 mailbox = mlx4_alloc_cmd_mailbox(dev);
348 if (IS_ERR(mailbox))
349 return PTR_ERR(mailbox);
350
47605df9
JM		 351 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
352 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 353 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
354 if (err)
355 goto out;
356
357 outbox = mailbox->buf;
358
47605df9
JM		 359 if (!op_modifier) {
360 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
361 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
362 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
363 err = -EPROTONOSUPPORT;
364 goto out;
365 }
366 func_cap->flags = field;
eb456a68 367 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 368
47605df9
JM		 369 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
370 func_cap->num_ports = field;
5cc914f1 371
47605df9
JM		 372 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
373 func_cap->pf_context_behaviour = size;
5cc914f1 374
eb456a68
JM		 375 if (quotas) {
376 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
377 func_cap->qp_quota = size & 0xFFFFFF;
378
379 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
380 func_cap->srq_quota = size & 0xFFFFFF;
381
382 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
383 func_cap->cq_quota = size & 0xFFFFFF;
384
385 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
386 func_cap->mpt_quota = size & 0xFFFFFF;
387
388 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
389 func_cap->mtt_quota = size & 0xFFFFFF;
390
391 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
392 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 393
eb456a68
JM		 394 } else {
395 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
396 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 397
eb456a68
JM		 398 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
399 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 400
eb456a68
JM		 401 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
402 func_cap->cq_quota = size & 0xFFFFFF;
403
404 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
405 func_cap->mpt_quota = size & 0xFFFFFF;
406
407 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
408 func_cap->mtt_quota = size & 0xFFFFFF;
409
410 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
411 func_cap->mcg_quota = size & 0xFFFFFF;
412 }
47605df9
JM		 413 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
414 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 415
47605df9
JM		 416 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
417 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 418
47605df9
JM		 419 goto out;
420 }
5cc914f1 421
47605df9
JM		 422 /* logical port query */
423 if (gen_or_port > dev->caps.num_ports) {
424 err = -EINVAL;
425 goto out;
426 }
5cc914f1 427
eb17711b 428 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
47605df9 429 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
bc82878b 430 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
47605df9
JM		 431 mlx4_err(dev, "VLAN is enforced on this port\n");
432 err = -EPROTONOSUPPORT;
5cc914f1 433 goto out;
47605df9 434 }
5cc914f1 435
eb17711b 436 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 437 mlx4_err(dev, "Force mac is enabled on this port\n");
438 err = -EPROTONOSUPPORT;
439 goto out;
5cc914f1 440 }
47605df9 441 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 442 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
443 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
1a91de28 444 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
47605df9
JM		 445 err = -EPROTONOSUPPORT;
446 goto out;
447 }
448 }
5cc914f1 449
47605df9
JM		 450 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
451 func_cap->physical_port = field;
452 if (func_cap->physical_port != gen_or_port) {
453 err = -ENOSYS;
454 goto out;
5cc914f1
MA		 455 }
456
99ec41d0
JM		 457 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
458 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
459 func_cap->qp0_qkey = qkey;
460 } else {
461 func_cap->qp0_qkey = 0;
462 }
463
47605df9
JM		 464 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
465 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
466
467 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
468 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
469
470 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
471 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
472
473 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
474 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
475
8e1a28e8
HHZ		 476 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
477 MLX4_GET(func_cap->phys_port_id, outbox,
478 QUERY_FUNC_CAP_PHYS_PORT_ID);
479
5cc914f1
MA		 480 /* All other resources are allocated by the master, but we still report
481 * 'num' and 'reserved' capabilities as follows:
482 * - num remains the maximum resource index
483 * - 'num - reserved' is the total available objects of a resource, but
484 * resource indices may be less than 'reserved'
485 * TODO: set per-resource quotas */
486
487out:
488 mlx4_free_cmd_mailbox(dev, mailbox);
489
490 return err;
491}
492
225c7b1f
RD		 493int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
494{
495 struct mlx4_cmd_mailbox *mailbox;
496 u32 *outbox;
497 u8 field;
ccf86321 498 u32 field32, flags, ext_flags;
225c7b1f
RD		 499 u16 size;
500 u16 stat_rate;
501 int err;
5ae2a7a8 502 int i;
225c7b1f
RD		 503
504#define QUERY_DEV_CAP_OUT_SIZE 0x100
505#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
506#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
507#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
508#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
509#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
510#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
511#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
512#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
513#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
514#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
515#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
516#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
517#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
518#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
519#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
520#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
521#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
522#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
523#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
524#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
525#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 526#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 527#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 528#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
529#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
530#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
531#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
532#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 533#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 534#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
535#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 536#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 537#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 538#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 539#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
540#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
541#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
542#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
543#define QUERY_DEV_CAP_BF_OFFSET 0x4c
544#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
545#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
546#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
547#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
548#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
549#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
550#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
551#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
552#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
553#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
554#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
555#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 556#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
557#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 558#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
3f7fb021 559#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
4de65803 560#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
0ff1fb65
HHZ		 561#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
562#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
77507aa2 563#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
adbc7ac5 564#define QUERY_DEV_CAP_ETH_PROT_CTRL_OFFSET 0x7a
225c7b1f
RD		 565#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
566#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
567#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
568#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
569#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
570#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
571#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
572#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
573#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
574#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 575#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 576#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
577#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
955154fa 578#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
7ffdf726 579#define QUERY_DEV_CAP_VXLAN 0x9e
114840c3 580#define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
225c7b1f 581
b3416f44 582 dev_cap->flags2 = 0;
225c7b1f
RD		 583 mailbox = mlx4_alloc_cmd_mailbox(dev);
584 if (IS_ERR(mailbox))
585 return PTR_ERR(mailbox);
586 outbox = mailbox->buf;
587
588 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 589 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 590 if (err)
591 goto out;
592
593 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
594 dev_cap->reserved_qps = 1 << (field & 0xf);
595 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
596 dev_cap->max_qps = 1 << (field & 0x1f);
597 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
598 dev_cap->reserved_srqs = 1 << (field >> 4);
599 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
600 dev_cap->max_srqs = 1 << (field & 0x1f);
601 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
602 dev_cap->max_cq_sz = 1 << field;
603 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
604 dev_cap->reserved_cqs = 1 << (field & 0xf);
605 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
606 dev_cap->max_cqs = 1 << (field & 0x1f);
607 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
608 dev_cap->max_mpts = 1 << (field & 0x3f);
609 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 610 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 611 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 612 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 613 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
614 dev_cap->reserved_mtts = 1 << (field >> 4);
615 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
616 dev_cap->max_mrw_sz = 1 << field;
617 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
618 dev_cap->reserved_mrws = 1 << (field & 0xf);
619 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
620 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
621 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
622 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
623 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
624 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 625 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
626 field &= 0x1f;
627 if (!field)
628 dev_cap->max_gso_sz = 0;
629 else
630 dev_cap->max_gso_sz = 1 << field;
631
b3416f44
SP		 632 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
633 if (field & 0x20)
634 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
635 if (field & 0x10)
636 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
637 field &= 0xf;
638 if (field) {
639 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
640 dev_cap->max_rss_tbl_sz = 1 << field;
641 } else
642 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 643 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
644 dev_cap->max_rdma_global = 1 << (field & 0x3f);
645 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
646 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 647 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 648 dev_cap->num_ports = field & 0xf;
149983af
DB		 649 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
650 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 651 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
652 if (field & 0x80)
653 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
654 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
4de65803
MB		 655 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
656 if (field & 0x80)
657 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
0ff1fb65
HHZ		 658 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
659 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 660 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
661 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 662 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
663 if (field & 0x80)
664 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 665 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 666 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 667 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 668 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
669 dev_cap->reserved_uars = field >> 4;
670 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
671 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
672 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
673 dev_cap->min_page_sz = 1 << field;
674
675 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
676 if (field & 0x80) {
677 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
678 dev_cap->bf_reg_size = 1 << (field & 0x1f);
679 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 680 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 681 field = 3;
225c7b1f
RD		 682 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
683 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
684 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
685 } else {
686 dev_cap->bf_reg_size = 0;
687 mlx4_dbg(dev, "BlueFlame not available\n");
688 }
689
690 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
691 dev_cap->max_sq_sg = field;
692 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
693 dev_cap->max_sq_desc_sz = size;
694
695 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
696 dev_cap->max_qp_per_mcg = 1 << field;
697 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
698 dev_cap->reserved_mgms = field & 0xf;
699 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
700 dev_cap->max_mcgs = 1 << field;
701 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
702 dev_cap->reserved_pds = field >> 4;
703 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
704 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 705 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
706 dev_cap->reserved_xrcds = field >> 4;
426dd00d 707 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 708 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 709
710 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
711 dev_cap->rdmarc_entry_sz = size;
712 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
713 dev_cap->qpc_entry_sz = size;
714 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
715 dev_cap->aux_entry_sz = size;
716 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
717 dev_cap->altc_entry_sz = size;
718 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
719 dev_cap->eqc_entry_sz = size;
720 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
721 dev_cap->cqc_entry_sz = size;
722 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
723 dev_cap->srq_entry_sz = size;
724 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
725 dev_cap->cmpt_entry_sz = size;
726 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
727 dev_cap->mtt_entry_sz = size;
728 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
729 dev_cap->dmpt_entry_sz = size;
730
731 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
732 dev_cap->max_srq_sz = 1 << field;
733 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
734 dev_cap->max_qp_sz = 1 << field;
735 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
736 dev_cap->resize_srq = field & 1;
737 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
738 dev_cap->max_rq_sg = field;
739 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
740 dev_cap->max_rq_desc_sz = size;
77507aa2 741 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
adbc7ac5
SM		 742 if (field & (1 << 5))
743 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
77507aa2
IS		 744 if (field & (1 << 6))
745 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
746 if (field & (1 << 7))
747 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
225c7b1f
RD		 748 MLX4_GET(dev_cap->bmme_flags, outbox,
749 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
750 MLX4_GET(dev_cap->reserved_lkey, outbox,
751 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
955154fa
MB		 752 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
753 if (field & 1<<6)
5930e8d0 754 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
7ffdf726
OG		 755 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
756 if (field & 1<<3)
757 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
225c7b1f
RD		 758 MLX4_GET(dev_cap->max_icm_sz, outbox,
759 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 760 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
761 MLX4_GET(dev_cap->max_counters, outbox,
762 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 763
114840c3
JM		 764 MLX4_GET(field32, outbox,
765 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
766 if (field32 & (1 << 0))
767 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
768
3f7fb021 769 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 770 if (field32 & (1 << 16))
771 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
3f7fb021
RE		 772 if (field32 & (1 << 26))
773 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 774 if (field32 & (1 << 20))
775 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
3f7fb021 776
5ae2a7a8
RD		 777 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
778 for (i = 1; i <= dev_cap->num_ports; ++i) {
779 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
780 dev_cap->max_vl[i] = field >> 4;
781 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 782 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 783 dev_cap->max_port_width[i] = field & 0xf;
784 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
785 dev_cap->max_gids[i] = 1 << (field & 0xf);
786 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
787 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
788 }
789 } else {
7ff93f8b 790#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 791#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 792#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 793#define QUERY_PORT_WIDTH_OFFSET 0x06
794#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 795#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 796#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 797#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 798#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
799#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
800#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 801
802 for (i = 1; i <= dev_cap->num_ports; ++i) {
803 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 804 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 805 if (err)
806 goto out;
807
7ff93f8b
YP		 808 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
809 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 810 dev_cap->suggested_type[i] = (field >> 3) & 1;
811 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 812 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 813 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 814 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
815 dev_cap->max_port_width[i] = field & 0xf;
816 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
817 dev_cap->max_gids[i] = 1 << (field >> 4);
818 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
819 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
820 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 821 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
822 dev_cap->log_max_macs[i] = field & 0xf;
823 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 824 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
825 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 826 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
827 dev_cap->trans_type[i] = field32 >> 24;
828 dev_cap->vendor_oui[i] = field32 & 0xffffff;
829 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
830 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 831 }
832 }
833
95d04f07
RD		 834 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
835 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 836
837 /*
838 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
839 * we can't use any EQs whose doorbell falls on that page,
840 * even if the EQ itself isn't reserved.
841 */
842 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
843 dev_cap->reserved_eqs);
844
845 mlx4_dbg(dev, "Max ICM size %lld MB\n",
846 (unsigned long long) dev_cap->max_icm_sz >> 20);
847 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
848 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
849 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
850 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
851 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
852 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
853 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
854 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
855 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
856 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
857 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
858 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
859 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
860 dev_cap->max_pds, dev_cap->reserved_mgms);
861 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
862 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
863 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 864 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 865 dev_cap->max_port_width[1]);
225c7b1f
RD		 866 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
867 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
868 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
869 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 870 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 871 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 872 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 873
874 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 875 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 876
877out:
878 mlx4_free_cmd_mailbox(dev, mailbox);
879 return err;
880}
881
b91cb3eb
JM		 882int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
883 struct mlx4_vhcr *vhcr,
884 struct mlx4_cmd_mailbox *inbox,
885 struct mlx4_cmd_mailbox *outbox,
886 struct mlx4_cmd_info *cmd)
887{
2a4fae14 888 u64 flags;
b91cb3eb
JM		 889 int err = 0;
890 u8 field;
cc1ade94 891 u32 bmme_flags;
449fc488
MB		 892 int real_port;
893 int slave_port;
894 int first_port;
895 struct mlx4_active_ports actv_ports;
b91cb3eb
JM		 896
897 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
898 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
899 if (err)
900 return err;
901
cc1ade94
SM		 902 /* add port mng change event capability and disable mw type 1
903 * unconditionally to slaves
904 */
2a4fae14
JM		 905 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
906 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 907 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
449fc488
MB		 908 actv_ports = mlx4_get_active_ports(dev, slave);
909 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
910 for (slave_port = 0, real_port = first_port;
911 real_port < first_port +
912 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
913 ++real_port, ++slave_port) {
914 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
915 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
916 else
917 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
918 }
919 for (; slave_port < dev->caps.num_ports; ++slave_port)
920 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
2a4fae14
JM		 921 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
922
449fc488
MB		 923 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
924 field &= ~0x0F;
925 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
926 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
927
30b40c31
AV		 928 /* For guests, disable timestamp */
929 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
930 field &= 0x7f;
931 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
932
7ffdf726 933 /* For guests, disable vxlan tunneling */
57352ef4 934 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
7ffdf726
OG		 935 field &= 0xf7;
936 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
937
b91cb3eb
JM		 938 /* For guests, report Blueflame disabled */
939 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
940 field &= 0x7f;
941 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
942
cc1ade94 943 /* For guests, disable mw type 2 */
57352ef4 944 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
cc1ade94
SM		 945 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
946 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
947
0081c8f3
JM		 948 /* turn off device-managed steering capability if not enabled */
949 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
950 MLX4_GET(field, outbox->buf,
951 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
952 field &= 0x7f;
953 MLX4_PUT(outbox->buf, field,
954 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
955 }
4de65803
MB		 956
957 /* turn off ipoib managed steering for guests */
57352ef4 958 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
4de65803
MB		 959 field &= ~0x80;
960 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
961
b91cb3eb
JM		 962 return 0;
963}
964
5cc914f1
MA		 965int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
966 struct mlx4_vhcr *vhcr,
967 struct mlx4_cmd_mailbox *inbox,
968 struct mlx4_cmd_mailbox *outbox,
969 struct mlx4_cmd_info *cmd)
970{
0eb62b93 971 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 972 u64 def_mac;
973 u8 port_type;
6634961c 974 u16 short_field;
5cc914f1 975 int err;
948e306d 976 int admin_link_state;
449fc488
MB		 977 int port = mlx4_slave_convert_port(dev, slave,
978 vhcr->in_modifier & 0xFF);
5cc914f1 979
105c320f 980#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 981#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 982#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
983#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 984
449fc488
MB		 985 if (port < 0)
986 return -EINVAL;
987
a7401b9c
JM		 988 /* Protect against untrusted guests: enforce that this is the
989 * QUERY_PORT general query.
990 */
991 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
992 return -EINVAL;
993
994 vhcr->in_modifier = port;
449fc488 995
5cc914f1
MA		 996 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
997 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
998 MLX4_CMD_NATIVE);
999
1000 if (!err && dev->caps.function != slave) {
0508ad64 1001 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 1002 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1003
1004 /* get port type - currently only eth is enabled */
1005 MLX4_GET(port_type, outbox->buf,
1006 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1007
105c320f
JM		 1008 /* No link sensing allowed */
1009 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1010 /* set port type to currently operating port type */
1011 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 1012
948e306d
RE		 1013 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1014 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1015 port_type |= MLX4_PORT_LINK_UP_MASK;
1016 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1017 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1018
5cc914f1
MA		 1019 MLX4_PUT(outbox->buf, port_type,
1020 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c 1021
b6ffaeff 1022 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
449fc488 1023 short_field = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 1024 else
1025 short_field = 1; /* slave max gids */
6634961c
JM		 1026 MLX4_PUT(outbox->buf, short_field,
1027 QUERY_PORT_CUR_MAX_GID_OFFSET);
1028
1029 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1030 MLX4_PUT(outbox->buf, short_field,
1031 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 1032 }
1033
1034 return err;
1035}
1036
6634961c
JM		 1037int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1038 int *gid_tbl_len, int *pkey_tbl_len)
1039{
1040 struct mlx4_cmd_mailbox *mailbox;
1041 u32 *outbox;
1042 u16 field;
1043 int err;
1044
1045 mailbox = mlx4_alloc_cmd_mailbox(dev);
1046 if (IS_ERR(mailbox))
1047 return PTR_ERR(mailbox);
1048
1049 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1050 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1051 MLX4_CMD_WRAPPED);
1052 if (err)
1053 goto out;
1054
1055 outbox = mailbox->buf;
1056
1057 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1058 *gid_tbl_len = field;
1059
1060 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1061 *pkey_tbl_len = field;
1062
1063out:
1064 mlx4_free_cmd_mailbox(dev, mailbox);
1065 return err;
1066}
1067EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1068
225c7b1f
RD		 1069int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1070{
1071 struct mlx4_cmd_mailbox *mailbox;
1072 struct mlx4_icm_iter iter;
1073 __be64 *pages;
1074 int lg;
1075 int nent = 0;
1076 int i;
1077 int err = 0;
1078 int ts = 0, tc = 0;
1079
1080 mailbox = mlx4_alloc_cmd_mailbox(dev);
1081 if (IS_ERR(mailbox))
1082 return PTR_ERR(mailbox);
225c7b1f
RD		 1083 pages = mailbox->buf;
1084
1085 for (mlx4_icm_first(icm, &iter);
1086 !mlx4_icm_last(&iter);
1087 mlx4_icm_next(&iter)) {
1088 /*
1089 * We have to pass pages that are aligned to their
1090 * size, so find the least significant 1 in the
1091 * address or size and use that as our log2 size.
1092 */
1093 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1094 if (lg < MLX4_ICM_PAGE_SHIFT) {
1a91de28
JP		 1095 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1096 MLX4_ICM_PAGE_SIZE,
1097 (unsigned long long) mlx4_icm_addr(&iter),
1098 mlx4_icm_size(&iter));
225c7b1f
RD		 1099 err = -EINVAL;
1100 goto out;
1101 }
1102
1103 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1104 if (virt != -1) {
1105 pages[nent * 2] = cpu_to_be64(virt);
1106 virt += 1 << lg;
1107 }
1108
1109 pages[nent * 2 + 1] =
1110 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1111 (lg - MLX4_ICM_PAGE_SHIFT));
1112 ts += 1 << (lg - 10);
1113 ++tc;
1114
1115 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1116 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 1117 MLX4_CMD_TIME_CLASS_B,
1118 MLX4_CMD_NATIVE);
225c7b1f
RD		 1119 if (err)
1120 goto out;
1121 nent = 0;
1122 }
1123 }
1124 }
1125
1126 if (nent)
f9baff50
JM		 1127 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1128 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1129 if (err)
1130 goto out;
1131
1132 switch (op) {
1133 case MLX4_CMD_MAP_FA:
1a91de28 1134 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
225c7b1f
RD		 1135 break;
1136 case MLX4_CMD_MAP_ICM_AUX:
1a91de28 1137 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
225c7b1f
RD		 1138 break;
1139 case MLX4_CMD_MAP_ICM:
1a91de28
JP		 1140 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1141 tc, ts, (unsigned long long) virt - (ts << 10));
225c7b1f
RD		 1142 break;
1143 }
1144
1145out:
1146 mlx4_free_cmd_mailbox(dev, mailbox);
1147 return err;
1148}
1149
1150int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1151{
1152 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1153}
1154
1155int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1156{
f9baff50
JM		 1157 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1158 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1159}
1160
1161
1162int mlx4_RUN_FW(struct mlx4_dev *dev)
1163{
f9baff50
JM		 1164 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1165 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1166}
1167
1168int mlx4_QUERY_FW(struct mlx4_dev *dev)
1169{
1170 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1171 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1172 struct mlx4_cmd_mailbox *mailbox;
1173 u32 *outbox;
1174 int err = 0;
1175 u64 fw_ver;
fe40900f 1176 u16 cmd_if_rev;
225c7b1f
RD		 1177 u8 lg;
1178
1179#define QUERY_FW_OUT_SIZE 0x100
1180#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1181#define QUERY_FW_PPF_ID 0x09
fe40900f 1182#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1183#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1184#define QUERY_FW_ERR_START_OFFSET 0x30
1185#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1186#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1187
1188#define QUERY_FW_SIZE_OFFSET 0x00
1189#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1190#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1191
5cc914f1
MA		 1192#define QUERY_FW_COMM_BASE_OFFSET 0x40
1193#define QUERY_FW_COMM_BAR_OFFSET 0x48
1194
ddd8a6c1
EE		 1195#define QUERY_FW_CLOCK_OFFSET 0x50
1196#define QUERY_FW_CLOCK_BAR 0x58
1197
225c7b1f
RD		 1198 mailbox = mlx4_alloc_cmd_mailbox(dev);
1199 if (IS_ERR(mailbox))
1200 return PTR_ERR(mailbox);
1201 outbox = mailbox->buf;
1202
1203 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1204 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1205 if (err)
1206 goto out;
1207
1208 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1209 /*
3e1db334 1210 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1211 * version, so swap here.
1212 */
1213 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1214 ((fw_ver & 0xffff0000ull) >> 16) |
1215 ((fw_ver & 0x0000ffffull) << 16);
1216
752a50ca
JM		 1217 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1218 dev->caps.function = lg;
1219
b91cb3eb
JM		 1220 if (mlx4_is_slave(dev))
1221 goto out;
1222
5cc914f1 1223
fe40900f 1224 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1225 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1226 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1a91de28 1227 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
fe40900f
RD		 1228 cmd_if_rev);
1229 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1230 (int) (dev->caps.fw_ver >> 32),
1231 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1232 (int) dev->caps.fw_ver & 0xffff);
1a91de28 1233 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
5ae2a7a8 1234 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1235 err = -ENODEV;
1236 goto out;
1237 }
1238
5ae2a7a8
RD		 1239 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1240 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1241
225c7b1f
RD		 1242 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1243 cmd->max_cmds = 1 << lg;
1244
fe40900f 1245 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1246 (int) (dev->caps.fw_ver >> 32),
1247 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1248 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1249 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1250
1251 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1252 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1253 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1254 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1255
1256 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1257 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1258
1259 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1260 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1261 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1262 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1263
5cc914f1
MA		 1264 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1265 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1266 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1267 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1268 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1269 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1270
ddd8a6c1
EE		 1271 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1272 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1273 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1274 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1275 fw->clock_bar, fw->clock_offset);
1276
225c7b1f
RD		 1277 /*
1278 * Round up number of system pages needed in case
1279 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1280 */
1281 fw->fw_pages =
1282 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1283 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1284
1285 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1286 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1287
1288out:
1289 mlx4_free_cmd_mailbox(dev, mailbox);
1290 return err;
1291}
1292
b91cb3eb
JM		 1293int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1294 struct mlx4_vhcr *vhcr,
1295 struct mlx4_cmd_mailbox *inbox,
1296 struct mlx4_cmd_mailbox *outbox,
1297 struct mlx4_cmd_info *cmd)
1298{
1299 u8 *outbuf;
1300 int err;
1301
1302 outbuf = outbox->buf;
1303 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1304 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1305 if (err)
1306 return err;
1307
752a50ca
JM		 1308 /* for slaves, set pci PPF ID to invalid and zero out everything
1309 * else except FW version */
b91cb3eb
JM		 1310 outbuf[0] = outbuf[1] = 0;
1311 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1312 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1313
b91cb3eb
JM		 1314 return 0;
1315}
1316
225c7b1f
RD		 1317static void get_board_id(void *vsd, char *board_id)
1318{
1319 int i;
1320
1321#define VSD_OFFSET_SIG1 0x00
1322#define VSD_OFFSET_SIG2 0xde
1323#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1324#define VSD_OFFSET_TS_BOARD_ID 0x20
1325
1326#define VSD_SIGNATURE_TOPSPIN 0x5ad
1327
1328 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1329
1330 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1331 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1332 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1333 } else {
1334 /*
1335 * The board ID is a string but the firmware byte
1336 * swaps each 4-byte word before passing it back to
1337 * us. Therefore we need to swab it before printing.
1338 */
1339 for (i = 0; i < 4; ++i)
1340 ((u32 *) board_id)[i] =
1341 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1342 }
1343}
1344
1345int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1346{
1347 struct mlx4_cmd_mailbox *mailbox;
1348 u32 *outbox;
1349 int err;
1350
1351#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1352#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1353#define QUERY_ADAPTER_VSD_OFFSET 0x20
1354
1355 mailbox = mlx4_alloc_cmd_mailbox(dev);
1356 if (IS_ERR(mailbox))
1357 return PTR_ERR(mailbox);
1358 outbox = mailbox->buf;
1359
1360 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1361 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1362 if (err)
1363 goto out;
1364
225c7b1f
RD		 1365 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1366
1367 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1368 adapter->board_id);
1369
1370out:
1371 mlx4_free_cmd_mailbox(dev, mailbox);
1372 return err;
1373}
1374
1375int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1376{
1377 struct mlx4_cmd_mailbox *mailbox;
1378 __be32 *inbox;
1379 int err;
1380
1381#define INIT_HCA_IN_SIZE 0x200
1382#define INIT_HCA_VERSION_OFFSET 0x000
1383#define INIT_HCA_VERSION 2
7ffdf726 1384#define INIT_HCA_VXLAN_OFFSET 0x0c
c57e20dc 1385#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1386#define INIT_HCA_FLAGS_OFFSET 0x014
1387#define INIT_HCA_QPC_OFFSET 0x020
1388#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1389#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1390#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1391#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1392#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1393#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1394#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
77507aa2 1395#define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
225c7b1f
RD		 1396#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1397#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1398#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1399#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1400#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1401#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1402#define INIT_HCA_MCAST_OFFSET 0x0c0
1403#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1404#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1405#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1406#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1407#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1408#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1409#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1410#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1411#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1412#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1413#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1414#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1415#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1416#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1417#define INIT_HCA_TPT_OFFSET 0x0f0
1418#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1419#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1420#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1421#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1422#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1423#define INIT_HCA_UAR_OFFSET 0x120
1424#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1425#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1426
1427 mailbox = mlx4_alloc_cmd_mailbox(dev);
1428 if (IS_ERR(mailbox))
1429 return PTR_ERR(mailbox);
1430 inbox = mailbox->buf;
1431
225c7b1f
RD		 1432 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1433
c57e20dc
EC		 1434 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1435 (ilog2(cache_line_size()) - 4) << 5;
1436
225c7b1f
RD		 1437#if defined(__LITTLE_ENDIAN)
1438 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1439#elif defined(__BIG_ENDIAN)
1440 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1441#else
1442#error Host endianness not defined
1443#endif
1444 /* Check port for UD address vector: */
1445 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1446
8ff095ec
EC		 1447 /* Enable IPoIB checksumming if we can: */
1448 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1449 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1450
51f5f0ee
JM		 1451 /* Enable QoS support if module parameter set */
1452 if (enable_qos)
1453 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1454
f2a3f6a3
OG		 1455 /* enable counters */
1456 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1457 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1458
08ff3235
OG		 1459 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1460 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1461 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1462 dev->caps.eqe_size = 64;
1463 dev->caps.eqe_factor = 1;
1464 } else {
1465 dev->caps.eqe_size = 32;
1466 dev->caps.eqe_factor = 0;
1467 }
1468
1469 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1470 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1471 dev->caps.cqe_size = 64;
77507aa2 1472 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1473 } else {
1474 dev->caps.cqe_size = 32;
1475 }
1476
77507aa2
IS		 1477 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1478 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1479 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1480 dev->caps.eqe_size = cache_line_size();
1481 dev->caps.cqe_size = cache_line_size();
1482 dev->caps.eqe_factor = 0;
1483 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1484 (ilog2(dev->caps.eqe_size) - 5)),
1485 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1486
1487 /* User still need to know to support CQE > 32B */
1488 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1489 }
1490
225c7b1f
RD		 1491 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1492
1493 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1494 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1495 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1496 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1497 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1498 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1499 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1500 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1501 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1502 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1503 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1504 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1505
0ff1fb65
HHZ		 1506 /* steering attributes */
1507 if (dev->caps.steering_mode ==
1508 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1509 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1510 cpu_to_be32(1 <<
1511 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1512
1513 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1514 MLX4_PUT(inbox, param->log_mc_entry_sz,
1515 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1516 MLX4_PUT(inbox, param->log_mc_table_sz,
1517 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1518 /* Enable Ethernet flow steering
1519 * with udp unicast and tcp unicast
1520 */
23537b73 1521 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1522 INIT_HCA_FS_ETH_BITS_OFFSET);
1523 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1524 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1525 /* Enable IPoIB flow steering
1526 * with udp unicast and tcp unicast
1527 */
23537b73 1528 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1529 INIT_HCA_FS_IB_BITS_OFFSET);
1530 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1531 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1532 } else {
1533 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1534 MLX4_PUT(inbox, param->log_mc_entry_sz,
1535 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1536 MLX4_PUT(inbox, param->log_mc_hash_sz,
1537 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1538 MLX4_PUT(inbox, param->log_mc_table_sz,
1539 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1540 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1541 MLX4_PUT(inbox, (u8) (1 << 3),
1542 INIT_HCA_UC_STEERING_OFFSET);
1543 }
225c7b1f
RD		 1544
1545 /* TPT attributes */
1546
1547 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1548 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1549 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1550 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1551 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1552
1553 /* UAR attributes */
1554
ab9c17a0 1555 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1556 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1557
7ffdf726
OG		 1558 /* set parser VXLAN attributes */
1559 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1560 u8 parser_params = 0;
1561 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1562 }
1563
f9baff50
JM		 1564 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1565 MLX4_CMD_NATIVE);
225c7b1f
RD		 1566
1567 if (err)
1568 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1569
1570 mlx4_free_cmd_mailbox(dev, mailbox);
1571 return err;
1572}
1573
ab9c17a0
JM		 1574int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1575 struct mlx4_init_hca_param *param)
1576{
1577 struct mlx4_cmd_mailbox *mailbox;
1578 __be32 *outbox;
7b8157be 1579 u32 dword_field;
ab9c17a0 1580 int err;
08ff3235 1581 u8 byte_field;
ab9c17a0
JM		 1582
1583#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1584#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1585
1586 mailbox = mlx4_alloc_cmd_mailbox(dev);
1587 if (IS_ERR(mailbox))
1588 return PTR_ERR(mailbox);
1589 outbox = mailbox->buf;
1590
1591 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1592 MLX4_CMD_QUERY_HCA,
1593 MLX4_CMD_TIME_CLASS_B,
1594 !mlx4_is_slave(dev));
1595 if (err)
1596 goto out;
1597
1598 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1599 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1600
1601 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1602
1603 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1604 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1605 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1606 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1607 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1608 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1609 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1610 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1611 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1612 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1613 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1614 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1615
7b8157be
JM		 1616 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1617 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1618 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1619 } else {
1620 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1621 if (byte_field & 0x8)
1622 param->steering_mode = MLX4_STEERING_MODE_B0;
1623 else
1624 param->steering_mode = MLX4_STEERING_MODE_A0;
1625 }
0ff1fb65 1626 /* steering attributes */
7b8157be 1627 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1628 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1629 MLX4_GET(param->log_mc_entry_sz, outbox,
1630 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1631 MLX4_GET(param->log_mc_table_sz, outbox,
1632 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1633 } else {
1634 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1635 MLX4_GET(param->log_mc_entry_sz, outbox,
1636 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1637 MLX4_GET(param->log_mc_hash_sz, outbox,
1638 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1639 MLX4_GET(param->log_mc_table_sz, outbox,
1640 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1641 }
ab9c17a0 1642
08ff3235
OG		 1643 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1644 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1645 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1646 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1647 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1648 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1649
77507aa2
IS		 1650 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1651 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1652 if (byte_field) {
1653 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1654 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1655 param->cqe_size = 1 << ((byte_field &
1656 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
1657 param->eqe_size = 1 << (((byte_field &
1658 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
1659 }
1660
ab9c17a0
JM		 1661 /* TPT attributes */
1662
1663 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1664 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1665 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1666 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1667 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1668
1669 /* UAR attributes */
1670
1671 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1672 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1673
1674out:
1675 mlx4_free_cmd_mailbox(dev, mailbox);
1676
1677 return err;
1678}
1679
980e9001
JM		 1680/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1681 * and real QP0 are active, so that the paravirtualized QP0 is ready
1682 * to operate */
1683static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1684{
1685 struct mlx4_priv *priv = mlx4_priv(dev);
1686 /* irrelevant if not infiniband */
1687 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1688 priv->mfunc.master.qp0_state[port].qp0_active)
1689 return 1;
1690 return 0;
1691}
1692
5cc914f1
MA		 1693int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1694 struct mlx4_vhcr *vhcr,
1695 struct mlx4_cmd_mailbox *inbox,
1696 struct mlx4_cmd_mailbox *outbox,
1697 struct mlx4_cmd_info *cmd)
1698{
1699 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1700 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1701 int err;
1702
449fc488
MB		 1703 if (port < 0)
1704 return -EINVAL;
1705
5cc914f1
MA		 1706 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1707 return 0;
1708
980e9001
JM		 1709 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1710 /* Enable port only if it was previously disabled */
1711 if (!priv->mfunc.master.init_port_ref[port]) {
1712 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1713 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1714 if (err)
1715 return err;
1716 }
1717 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1718 } else {
1719 if (slave == mlx4_master_func_num(dev)) {
1720 if (check_qp0_state(dev, slave, port) &&
1721 !priv->mfunc.master.qp0_state[port].port_active) {
1722 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1723 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1724 if (err)
1725 return err;
1726 priv->mfunc.master.qp0_state[port].port_active = 1;
1727 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1728 }
1729 } else
1730 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1731 }
1732 ++priv->mfunc.master.init_port_ref[port];
1733 return 0;
1734}
1735
5ae2a7a8 1736int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1737{
1738 struct mlx4_cmd_mailbox *mailbox;
1739 u32 *inbox;
1740 int err;
1741 u32 flags;
5ae2a7a8 1742 u16 field;
225c7b1f 1743
5ae2a7a8 1744 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1745#define INIT_PORT_IN_SIZE 256
1746#define INIT_PORT_FLAGS_OFFSET 0x00
1747#define INIT_PORT_FLAG_SIG (1 << 18)
1748#define INIT_PORT_FLAG_NG (1 << 17)
1749#define INIT_PORT_FLAG_G0 (1 << 16)
1750#define INIT_PORT_VL_SHIFT 4
1751#define INIT_PORT_PORT_WIDTH_SHIFT 8
1752#define INIT_PORT_MTU_OFFSET 0x04
1753#define INIT_PORT_MAX_GID_OFFSET 0x06
1754#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1755#define INIT_PORT_GUID0_OFFSET 0x10
1756#define INIT_PORT_NODE_GUID_OFFSET 0x18
1757#define INIT_PORT_SI_GUID_OFFSET 0x20
1758
5ae2a7a8
RD		 1759 mailbox = mlx4_alloc_cmd_mailbox(dev);
1760 if (IS_ERR(mailbox))
1761 return PTR_ERR(mailbox);
1762 inbox = mailbox->buf;
225c7b1f 1763
5ae2a7a8
RD		 1764 flags = 0;
1765 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1766 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1767 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1768
b79acb49 1769 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1770 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1771 field = dev->caps.gid_table_len[port];
1772 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1773 field = dev->caps.pkey_table_len[port];
1774 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1775
5ae2a7a8 1776 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1777 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1778
5ae2a7a8
RD		 1779 mlx4_free_cmd_mailbox(dev, mailbox);
1780 } else
1781 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1782 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1783
1784 return err;
1785}
1786EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1787
5cc914f1
MA		 1788int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1789 struct mlx4_vhcr *vhcr,
1790 struct mlx4_cmd_mailbox *inbox,
1791 struct mlx4_cmd_mailbox *outbox,
1792 struct mlx4_cmd_info *cmd)
1793{
1794 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1795 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1796 int err;
1797
449fc488
MB		 1798 if (port < 0)
1799 return -EINVAL;
1800
5cc914f1
MA		 1801 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1802 (1 << port)))
1803 return 0;
1804
980e9001
JM		 1805 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1806 if (priv->mfunc.master.init_port_ref[port] == 1) {
1807 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1808 1000, MLX4_CMD_NATIVE);
1809 if (err)
1810 return err;
1811 }
1812 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1813 } else {
1814 /* infiniband port */
1815 if (slave == mlx4_master_func_num(dev)) {
1816 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1817 priv->mfunc.master.qp0_state[port].port_active) {
1818 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1819 1000, MLX4_CMD_NATIVE);
1820 if (err)
1821 return err;
1822 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1823 priv->mfunc.master.qp0_state[port].port_active = 0;
1824 }
1825 } else
1826 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1827 }
5cc914f1
MA		 1828 --priv->mfunc.master.init_port_ref[port];
1829 return 0;
1830}
1831
225c7b1f
RD		 1832int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1833{
f9baff50
JM		 1834 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1835 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1836}
1837EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1838
1839int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1840{
f9baff50
JM		 1841 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1842 MLX4_CMD_NATIVE);
225c7b1f
RD		 1843}
1844
d18f141a
OG		 1845struct mlx4_config_dev {
1846 __be32 update_flags;
1847 __be32 rsdv1[3];
1848 __be16 vxlan_udp_dport;
1849 __be16 rsvd2;
1850};
1851
1852#define MLX4_VXLAN_UDP_DPORT (1 << 0)
1853
1854static int mlx4_CONFIG_DEV(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
1855{
1856 int err;
1857 struct mlx4_cmd_mailbox *mailbox;
1858
1859 mailbox = mlx4_alloc_cmd_mailbox(dev);
1860 if (IS_ERR(mailbox))
1861 return PTR_ERR(mailbox);
1862
1863 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
1864
1865 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
1866 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1867
1868 mlx4_free_cmd_mailbox(dev, mailbox);
1869 return err;
1870}
1871
1872int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
1873{
1874 struct mlx4_config_dev config_dev;
1875
1876 memset(&config_dev, 0, sizeof(config_dev));
1877 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
1878 config_dev.vxlan_udp_dport = udp_port;
1879
1880 return mlx4_CONFIG_DEV(dev, &config_dev);
1881}
1882EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
1883
1884
225c7b1f
RD		 1885int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1886{
1887 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1888 MLX4_CMD_SET_ICM_SIZE,
f9baff50 1889 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1890 if (ret)
1891 return ret;
1892
1893 /*
1894 * Round up number of system pages needed in case
1895 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1896 */
1897 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1898 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1899
1900 return 0;
1901}
1902
1903int mlx4_NOP(struct mlx4_dev *dev)
1904{
1905 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 1906 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 1907}
14c07b13 1908
8e1a28e8
HHZ		 1909int mlx4_get_phys_port_id(struct mlx4_dev *dev)
1910{
1911 u8 port;
1912 u32 *outbox;
1913 struct mlx4_cmd_mailbox *mailbox;
1914 u32 in_mod;
1915 u32 guid_hi, guid_lo;
1916 int err, ret = 0;
1917#define MOD_STAT_CFG_PORT_OFFSET 8
1918#define MOD_STAT_CFG_GUID_H 0X14
1919#define MOD_STAT_CFG_GUID_L 0X1c
1920
1921 mailbox = mlx4_alloc_cmd_mailbox(dev);
1922 if (IS_ERR(mailbox))
1923 return PTR_ERR(mailbox);
1924 outbox = mailbox->buf;
1925
1926 for (port = 1; port <= dev->caps.num_ports; port++) {
1927 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
1928 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
1929 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1930 MLX4_CMD_NATIVE);
1931 if (err) {
1932 mlx4_err(dev, "Fail to get port %d uplink guid\n",
1933 port);
1934 ret = err;
1935 } else {
1936 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
1937 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
1938 dev->caps.phys_port_id[port] = (u64)guid_lo |
1939 (u64)guid_hi << 32;
1940 }
1941 }
1942 mlx4_free_cmd_mailbox(dev, mailbox);
1943 return ret;
1944}
1945
14c07b13
YP		 1946#define MLX4_WOL_SETUP_MODE (5 << 28)
1947int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1948{
1949 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1950
1951 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 1952 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1953 MLX4_CMD_NATIVE);
14c07b13
YP		 1954}
1955EXPORT_SYMBOL_GPL(mlx4_wol_read);
1956
1957int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1958{
1959 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1960
1961 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 1962 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 1963}
1964EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 1965
1966enum {
1967 ADD_TO_MCG = 0x26,
1968};
1969
1970
1971void mlx4_opreq_action(struct work_struct *work)
1972{
1973 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
1974 opreq_task);
1975 struct mlx4_dev *dev = &priv->dev;
1976 int num_tasks = atomic_read(&priv->opreq_count);
1977 struct mlx4_cmd_mailbox *mailbox;
1978 struct mlx4_mgm *mgm;
1979 u32 *outbox;
1980 u32 modifier;
1981 u16 token;
fe6f700d
YP		 1982 u16 type;
1983 int err;
1984 u32 num_qps;
1985 struct mlx4_qp qp;
1986 int i;
1987 u8 rem_mcg;
1988 u8 prot;
1989
1990#define GET_OP_REQ_MODIFIER_OFFSET 0x08
1991#define GET_OP_REQ_TOKEN_OFFSET 0x14
1992#define GET_OP_REQ_TYPE_OFFSET 0x1a
1993#define GET_OP_REQ_DATA_OFFSET 0x20
1994
1995 mailbox = mlx4_alloc_cmd_mailbox(dev);
1996 if (IS_ERR(mailbox)) {
1997 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
1998 return;
1999 }
2000 outbox = mailbox->buf;
2001
2002 while (num_tasks) {
2003 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2004 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2005 MLX4_CMD_NATIVE);
2006 if (err) {
6d3be300 2007 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 2008 err);
2009 return;
2010 }
2011 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2012 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2013 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 2014 type &= 0xfff;
2015
2016 switch (type) {
2017 case ADD_TO_MCG:
2018 if (dev->caps.steering_mode ==
2019 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2020 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2021 err = EPERM;
2022 break;
2023 }
2024 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2025 GET_OP_REQ_DATA_OFFSET);
2026 num_qps = be32_to_cpu(mgm->members_count) &
2027 MGM_QPN_MASK;
2028 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2029 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2030
2031 for (i = 0; i < num_qps; i++) {
2032 qp.qpn = be32_to_cpu(mgm->qp[i]);
2033 if (rem_mcg)
2034 err = mlx4_multicast_detach(dev, &qp,
2035 mgm->gid,
2036 prot, 0);
2037 else
2038 err = mlx4_multicast_attach(dev, &qp,
2039 mgm->gid,
2040 mgm->gid[5]
2041 , 0, prot,
2042 NULL);
2043 if (err)
2044 break;
2045 }
2046 break;
2047 default:
2048 mlx4_warn(dev, "Bad type for required operation\n");
2049 err = EINVAL;
2050 break;
2051 }
28d222bb
EP		 2052 err = mlx4_cmd(dev, 0, ((u32) err |
2053 (__force u32)cpu_to_be32(token) << 16),
fe6f700d
YP		 2054 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2055 MLX4_CMD_NATIVE);
2056 if (err) {
2057 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2058 err);
2059 goto out;
2060 }
2061 memset(outbox, 0, 0xffc);
2062 num_tasks = atomic_dec_return(&priv->opreq_count);
2063 }
2064
2065out:
2066 mlx4_free_cmd_mailbox(dev, mailbox);
2067}
114840c3
JM		 2068
2069static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2070 struct mlx4_cmd_mailbox *mailbox)
2071{
2072#define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2073#define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2074#define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2075#define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2076
2077 u32 set_attr_mask, getresp_attr_mask;
2078 u32 trap_attr_mask, traprepress_attr_mask;
2079
2080 MLX4_GET(set_attr_mask, mailbox->buf,
2081 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2082 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2083 set_attr_mask);
2084
2085 MLX4_GET(getresp_attr_mask, mailbox->buf,
2086 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2087 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2088 getresp_attr_mask);
2089
2090 MLX4_GET(trap_attr_mask, mailbox->buf,
2091 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2092 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2093 trap_attr_mask);
2094
2095 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2096 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2097 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2098 traprepress_attr_mask);
2099
2100 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2101 traprepress_attr_mask)
2102 return 1;
2103
2104 return 0;
2105}
2106
2107int mlx4_config_mad_demux(struct mlx4_dev *dev)
2108{
2109 struct mlx4_cmd_mailbox *mailbox;
2110 int secure_host_active;
2111 int err;
2112
2113 /* Check if mad_demux is supported */
2114 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2115 return 0;
2116
2117 mailbox = mlx4_alloc_cmd_mailbox(dev);
2118 if (IS_ERR(mailbox)) {
2119 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2120 return -ENOMEM;
2121 }
2122
2123 /* Query mad_demux to find out which MADs are handled by internal sma */
2124 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2125 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2126 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2127 if (err) {
2128 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2129 err);
2130 goto out;
2131 }
2132
2133 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2134
2135 /* Config mad_demux to handle all MADs returned by the query above */
2136 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2137 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2138 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2139 if (err) {
2140 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2141 goto out;
2142 }
2143
2144 if (secure_host_active)
2145 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2146out:
2147 mlx4_free_cmd_mailbox(dev, mailbox);
2148 return err;
2149}
adbc7ac5
SM		 2150
2151/* Access Reg commands */
2152enum mlx4_access_reg_masks {
2153 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2154 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2155 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2156};
2157
2158struct mlx4_access_reg {
2159 __be16 constant1;
2160 u8 status;
2161 u8 resrvd1;
2162 __be16 reg_id;
2163 u8 method;
2164 u8 constant2;
2165 __be32 resrvd2[2];
2166 __be16 len_const;
2167 __be16 resrvd3;
2168#define MLX4_ACCESS_REG_HEADER_SIZE (20)
2169 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2170} __attribute__((__packed__));
2171
2172/**
2173 * mlx4_ACCESS_REG - Generic access reg command.
2174 * @dev: mlx4_dev.
2175 * @reg_id: register ID to access.
2176 * @method: Access method Read/Write.
2177 * @reg_len: register length to Read/Write in bytes.
2178 * @reg_data: reg_data pointer to Read/Write From/To.
2179 *
2180 * Access ConnectX registers FW command.
2181 * Returns 0 on success and copies outbox mlx4_access_reg data
2182 * field into reg_data or a negative error code.
2183 */
2184static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2185 enum mlx4_access_reg_method method,
2186 u16 reg_len, void *reg_data)
2187{
2188 struct mlx4_cmd_mailbox *inbox, *outbox;
2189 struct mlx4_access_reg *inbuf, *outbuf;
2190 int err;
2191
2192 inbox = mlx4_alloc_cmd_mailbox(dev);
2193 if (IS_ERR(inbox))
2194 return PTR_ERR(inbox);
2195
2196 outbox = mlx4_alloc_cmd_mailbox(dev);
2197 if (IS_ERR(outbox)) {
2198 mlx4_free_cmd_mailbox(dev, inbox);
2199 return PTR_ERR(outbox);
2200 }
2201
2202 inbuf = inbox->buf;
2203 outbuf = outbox->buf;
2204
2205 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2206 inbuf->constant2 = 0x1;
2207 inbuf->reg_id = cpu_to_be16(reg_id);
2208 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2209
2210 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2211 inbuf->len_const =
2212 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2213 ((0x3) << 12));
2214
2215 memcpy(inbuf->reg_data, reg_data, reg_len);
2216 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2217 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2218 MLX4_CMD_NATIVE);
2219 if (err)
2220 goto out;
2221
2222 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2223 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2224 mlx4_err(dev,
2225 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2226 reg_id, err);
2227 goto out;
2228 }
2229
2230 memcpy(reg_data, outbuf->reg_data, reg_len);
2231out:
2232 mlx4_free_cmd_mailbox(dev, inbox);
2233 mlx4_free_cmd_mailbox(dev, outbox);
2234 return err;
2235}
2236
2237/* ConnectX registers IDs */
2238enum mlx4_reg_id {
2239 MLX4_REG_ID_PTYS = 0x5004,
2240};
2241
2242/**
2243 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2244 * register
2245 * @dev: mlx4_dev.
2246 * @method: Access method Read/Write.
2247 * @ptys_reg: PTYS register data pointer.
2248 *
2249 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2250 * configuration
2251 * Returns 0 on success or a negative error code.
2252 */
2253int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2254 enum mlx4_access_reg_method method,
2255 struct mlx4_ptys_reg *ptys_reg)
2256{
2257 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2258 method, sizeof(*ptys_reg), ptys_reg);
2259}
2260EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
Linux 6.x block layer and io_uring tree(s)