projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net/mlx4: Refactor QUERY_PORT
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
4d531aa8 94 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
540b3a39 112 [53] = "Port ETS Scheduler support",
4d531aa8 113 [55] = "Port link type sensing support",
00f5ce99 114 [59] = "Port management change event support",
08ff3235
OG		 115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
225c7b1f
RD		 117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 122 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
b3416f44
SP		 126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 131 [2] = "RSS XOR Hash Function support",
56cb4567 132 [3] = "Device managed flow steering support",
d998735f 133 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
b01978ca 136 [7] = "FSM (MAC anti-spoofing) support",
7ffdf726 137 [8] = "Dynamic QP updates support",
56cb4567 138 [9] = "Device managed flow steering IPoIB support",
114840c3 139 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
77507aa2
IS		 140 [11] = "MAD DEMUX (Secure-Host) support",
141 [12] = "Large cache line (>64B) CQE stride support",
adbc7ac5 142 [13] = "Large cache line (>64B) EQE stride support",
a53e3e8c 143 [14] = "Ethernet protocol control support",
d475c95b 144 [15] = "Ethernet Backplane autoneg support",
7ae0e400 145 [16] = "CONFIG DEV support",
de966c59
MB		 146 [17] = "Asymmetric EQs support",
147 [18] = "More than 80 VFs support"
b3416f44
SP		 148 };
149 int i;
150
151 for (i = 0; i < ARRAY_SIZE(fname); ++i)
152 if (fname[i] && (flags & (1LL << i)))
153 mlx4_dbg(dev, " %s\n", fname[i]);
154}
155
2d928651
VS		 156int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
157{
158 struct mlx4_cmd_mailbox *mailbox;
159 u32 *inbox;
160 int err = 0;
161
162#define MOD_STAT_CFG_IN_SIZE 0x100
163
164#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
165#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
166
167 mailbox = mlx4_alloc_cmd_mailbox(dev);
168 if (IS_ERR(mailbox))
169 return PTR_ERR(mailbox);
170 inbox = mailbox->buf;
171
2d928651
VS		 172 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
173 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
174
175 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 176 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 177
178 mlx4_free_cmd_mailbox(dev, mailbox);
179 return err;
180}
181
e8c4265b
MB		 182int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave)
183{
184 struct mlx4_cmd_mailbox *mailbox;
185 u32 *outbox;
186 u8 in_modifier;
187 u8 field;
188 u16 field16;
189 int err;
190
191#define QUERY_FUNC_BUS_OFFSET 0x00
192#define QUERY_FUNC_DEVICE_OFFSET 0x01
193#define QUERY_FUNC_FUNCTION_OFFSET 0x01
194#define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
195#define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
196#define QUERY_FUNC_MAX_EQ_OFFSET 0x06
197#define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
198
199 mailbox = mlx4_alloc_cmd_mailbox(dev);
200 if (IS_ERR(mailbox))
201 return PTR_ERR(mailbox);
202 outbox = mailbox->buf;
203
204 in_modifier = slave;
e8c4265b
MB		 205
206 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0,
207 MLX4_CMD_QUERY_FUNC,
208 MLX4_CMD_TIME_CLASS_A,
209 MLX4_CMD_NATIVE);
210 if (err)
211 goto out;
212
213 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
214 func->bus = field & 0xf;
215 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
216 func->device = field & 0xf1;
217 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
218 func->function = field & 0x7;
219 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
220 func->physical_function = field & 0xf;
221 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
222 func->rsvd_eqs = field16 & 0xffff;
223 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
224 func->max_eq = field16 & 0xffff;
225 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
226 func->rsvd_uars = field & 0x0f;
227
228 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
229 func->bus, func->device, func->function, func->physical_function,
230 func->max_eq, func->rsvd_eqs, func->rsvd_uars);
231
232out:
233 mlx4_free_cmd_mailbox(dev, mailbox);
234 return err;
235}
236
5cc914f1
MA		 237int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
238 struct mlx4_vhcr *vhcr,
239 struct mlx4_cmd_mailbox *inbox,
240 struct mlx4_cmd_mailbox *outbox,
241 struct mlx4_cmd_info *cmd)
242{
5a0d0a61 243 struct mlx4_priv *priv = mlx4_priv(dev);
99ec41d0
JM		 244 u8 field, port;
245 u32 size, proxy_qp, qkey;
5cc914f1 246 int err = 0;
7ae0e400 247 struct mlx4_func func;
5cc914f1
MA		 248
249#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
250#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 251#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 252#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 253#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
254#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
255#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
256#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
257#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
258#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 259#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 260#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 261
eb456a68
JM		 262#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
263#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
264#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
265#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
266#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
267#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
268
ddae0349
EE		 269#define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c
270
105c320f
JM		 271#define QUERY_FUNC_CAP_FMR_FLAG 0x80
272#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
273#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 274#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
ddae0349
EE		 275#define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04
276
277#define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31)
d57febe1 278#define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30)
105c320f
JM		 279
280/* when opcode modifier = 1 */
5cc914f1 281#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
99ec41d0 282#define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
73e74ab4
HHZ		 283#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
284#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 285
47605df9
JM		 286#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
287#define QUERY_FUNC_CAP_QP0_PROXY 0x14
288#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
289#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
8e1a28e8 290#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
47605df9 291
73e74ab4
HHZ		 292#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
293#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
eb17711b 294#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
99ec41d0 295#define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
105c320f 296
73e74ab4 297#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
7ae0e400 298#define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
105c320f 299
5cc914f1 300 if (vhcr->op_modifier == 1) {
449fc488
MB		 301 struct mlx4_active_ports actv_ports =
302 mlx4_get_active_ports(dev, slave);
303 int converted_port = mlx4_slave_convert_port(
304 dev, slave, vhcr->in_modifier);
305
306 if (converted_port < 0)
307 return -EINVAL;
308
309 vhcr->in_modifier = converted_port;
449fc488
MB		 310 /* phys-port = logical-port */
311 field = vhcr->in_modifier -
312 find_first_bit(actv_ports.ports, dev->caps.num_ports);
47605df9
JM		 313 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
314
99ec41d0
JM		 315 port = vhcr->in_modifier;
316 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
317
318 /* Set nic_info bit to mark new fields support */
319 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
320
321 if (mlx4_vf_smi_enabled(dev, slave, port) &&
322 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
323 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
324 MLX4_PUT(outbox->buf, qkey,
325 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
326 }
327 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
328
47605df9 329 /* size is now the QP number */
99ec41d0 330 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
47605df9
JM		 331 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
332
333 size += 2;
334 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
335
99ec41d0
JM		 336 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
337 proxy_qp += 2;
338 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
47605df9 339
8e1a28e8
HHZ		 340 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
341 QUERY_FUNC_CAP_PHYS_PORT_ID);
342
5cc914f1 343 } else if (vhcr->op_modifier == 0) {
449fc488
MB		 344 struct mlx4_active_ports actv_ports =
345 mlx4_get_active_ports(dev, slave);
eb456a68
JM		 346 /* enable rdma and ethernet interfaces, and new quota locations */
347 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
ddae0349 348 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX);
5cc914f1
MA		 349 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
350
449fc488
MB		 351 field = min(
352 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
353 dev->caps.num_ports);
5cc914f1
MA		 354 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
355
08ff3235 356 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 357 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
358
105c320f
JM		 359 field = 0; /* protected FMR support not available as yet */
360 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
361
5a0d0a61 362 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 363 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 364 size = dev->caps.num_qps;
365 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 366
5a0d0a61 367 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 368 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 369 size = dev->caps.num_srqs;
370 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 371
5a0d0a61 372 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 373 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 374 size = dev->caps.num_cqs;
375 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1 376
7ae0e400
MB		 377 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
378 mlx4_QUERY_FUNC(dev, &func, slave)) {
379 size = vhcr->in_modifier &
380 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
381 dev->caps.num_eqs :
382 rounddown_pow_of_two(dev->caps.num_eqs);
383 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
384 size = dev->caps.reserved_eqs;
385 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
386 } else {
387 size = vhcr->in_modifier &
388 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
389 func.max_eq :
390 rounddown_pow_of_two(func.max_eq);
391 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
392 size = func.rsvd_eqs;
393 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
394 }
5cc914f1 395
5a0d0a61 396 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 397 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 398 size = dev->caps.num_mpts;
399 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 400
5a0d0a61 401 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 402 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 403 size = dev->caps.num_mtts;
404 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 405
406 size = dev->caps.num_mgms + dev->caps.num_amgms;
407 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 408 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1 409
d57febe1
MB		 410 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG |
411 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG;
ddae0349 412 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
5cc914f1
MA		 413 } else
414 err = -EINVAL;
415
416 return err;
417}
418
225c6c8c 419int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
47605df9 420 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 421{
422 struct mlx4_cmd_mailbox *mailbox;
423 u32 *outbox;
47605df9 424 u8 field, op_modifier;
99ec41d0 425 u32 size, qkey;
eb456a68 426 int err = 0, quotas = 0;
7ae0e400 427 u32 in_modifier;
5cc914f1 428
47605df9 429 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
7ae0e400
MB		 430 in_modifier = op_modifier ? gen_or_port :
431 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS;
5cc914f1
MA		 432
433 mailbox = mlx4_alloc_cmd_mailbox(dev);
434 if (IS_ERR(mailbox))
435 return PTR_ERR(mailbox);
436
7ae0e400 437 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier,
47605df9 438 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 439 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
440 if (err)
441 goto out;
442
443 outbox = mailbox->buf;
444
47605df9
JM		 445 if (!op_modifier) {
446 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
447 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
448 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
449 err = -EPROTONOSUPPORT;
450 goto out;
451 }
452 func_cap->flags = field;
eb456a68 453 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 454
47605df9
JM		 455 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
456 func_cap->num_ports = field;
5cc914f1 457
47605df9
JM		 458 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
459 func_cap->pf_context_behaviour = size;
5cc914f1 460
eb456a68
JM		 461 if (quotas) {
462 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
463 func_cap->qp_quota = size & 0xFFFFFF;
464
465 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
466 func_cap->srq_quota = size & 0xFFFFFF;
467
468 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
469 func_cap->cq_quota = size & 0xFFFFFF;
470
471 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
472 func_cap->mpt_quota = size & 0xFFFFFF;
473
474 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
475 func_cap->mtt_quota = size & 0xFFFFFF;
476
477 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
478 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 479
eb456a68
JM		 480 } else {
481 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
482 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 483
eb456a68
JM		 484 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
485 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 486
eb456a68
JM		 487 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
488 func_cap->cq_quota = size & 0xFFFFFF;
489
490 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
491 func_cap->mpt_quota = size & 0xFFFFFF;
492
493 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
494 func_cap->mtt_quota = size & 0xFFFFFF;
495
496 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
497 func_cap->mcg_quota = size & 0xFFFFFF;
498 }
47605df9
JM		 499 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
500 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 501
47605df9
JM		 502 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
503 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 504
ddae0349
EE		 505 func_cap->extra_flags = 0;
506
507 /* Mailbox data from 0x6c and onward should only be treated if
508 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags
509 */
510 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) {
511 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
512 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG)
513 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP;
d57febe1
MB		 514 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG)
515 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP;
ddae0349
EE		 516 }
517
47605df9
JM		 518 goto out;
519 }
5cc914f1 520
47605df9
JM		 521 /* logical port query */
522 if (gen_or_port > dev->caps.num_ports) {
523 err = -EINVAL;
524 goto out;
525 }
5cc914f1 526
eb17711b 527 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
47605df9 528 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
bc82878b 529 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
47605df9
JM		 530 mlx4_err(dev, "VLAN is enforced on this port\n");
531 err = -EPROTONOSUPPORT;
5cc914f1 532 goto out;
47605df9 533 }
5cc914f1 534
eb17711b 535 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 536 mlx4_err(dev, "Force mac is enabled on this port\n");
537 err = -EPROTONOSUPPORT;
538 goto out;
5cc914f1 539 }
47605df9 540 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 541 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
542 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
1a91de28 543 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
47605df9
JM		 544 err = -EPROTONOSUPPORT;
545 goto out;
546 }
547 }
5cc914f1 548
47605df9
JM		 549 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
550 func_cap->physical_port = field;
551 if (func_cap->physical_port != gen_or_port) {
552 err = -ENOSYS;
553 goto out;
5cc914f1
MA		 554 }
555
99ec41d0
JM		 556 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
557 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
558 func_cap->qp0_qkey = qkey;
559 } else {
560 func_cap->qp0_qkey = 0;
561 }
562
47605df9
JM		 563 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
564 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
565
566 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
567 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
568
569 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
570 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
571
572 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
573 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
574
8e1a28e8
HHZ		 575 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
576 MLX4_GET(func_cap->phys_port_id, outbox,
577 QUERY_FUNC_CAP_PHYS_PORT_ID);
578
5cc914f1
MA		 579 /* All other resources are allocated by the master, but we still report
580 * 'num' and 'reserved' capabilities as follows:
581 * - num remains the maximum resource index
582 * - 'num - reserved' is the total available objects of a resource, but
583 * resource indices may be less than 'reserved'
584 * TODO: set per-resource quotas */
585
586out:
587 mlx4_free_cmd_mailbox(dev, mailbox);
588
589 return err;
590}
591
225c7b1f
RD		 592int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
593{
594 struct mlx4_cmd_mailbox *mailbox;
595 u32 *outbox;
596 u8 field;
ccf86321 597 u32 field32, flags, ext_flags;
225c7b1f
RD		 598 u16 size;
599 u16 stat_rate;
600 int err;
5ae2a7a8 601 int i;
225c7b1f
RD		 602
603#define QUERY_DEV_CAP_OUT_SIZE 0x100
604#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
605#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
606#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
607#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
608#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
609#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
610#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
611#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
612#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
613#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
614#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
615#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
616#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
617#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
618#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
619#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
620#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
621#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
7ae0e400 622#define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
225c7b1f
RD		 623#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
624#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
625#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 626#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 627#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 628#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
629#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
630#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
631#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
632#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 633#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 634#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
635#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 636#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 637#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 638#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 639#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
640#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
641#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
642#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
643#define QUERY_DEV_CAP_BF_OFFSET 0x4c
644#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
645#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
646#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
647#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
648#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
649#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
650#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
651#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
652#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
653#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
654#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
655#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 656#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
657#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 658#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
3f7fb021 659#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
4de65803 660#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
0ff1fb65
HHZ		 661#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
662#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
77507aa2 663#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
adbc7ac5 664#define QUERY_DEV_CAP_ETH_PROT_CTRL_OFFSET 0x7a
225c7b1f
RD		 665#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
666#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
667#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
668#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
669#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
670#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
671#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
672#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
673#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
674#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 675#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
d475c95b 676#define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
225c7b1f
RD		 677#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
678#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
a53e3e8c 679#define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
955154fa 680#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
7ffdf726 681#define QUERY_DEV_CAP_VXLAN 0x9e
114840c3 682#define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
225c7b1f 683
b3416f44 684 dev_cap->flags2 = 0;
225c7b1f
RD		 685 mailbox = mlx4_alloc_cmd_mailbox(dev);
686 if (IS_ERR(mailbox))
687 return PTR_ERR(mailbox);
688 outbox = mailbox->buf;
689
690 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 691 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 692 if (err)
693 goto out;
694
695 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
696 dev_cap->reserved_qps = 1 << (field & 0xf);
697 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
698 dev_cap->max_qps = 1 << (field & 0x1f);
699 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
700 dev_cap->reserved_srqs = 1 << (field >> 4);
701 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
702 dev_cap->max_srqs = 1 << (field & 0x1f);
703 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
704 dev_cap->max_cq_sz = 1 << field;
705 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
706 dev_cap->reserved_cqs = 1 << (field & 0xf);
707 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
708 dev_cap->max_cqs = 1 << (field & 0x1f);
709 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
710 dev_cap->max_mpts = 1 << (field & 0x3f);
711 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
7c68dd43 712 dev_cap->reserved_eqs = 1 << (field & 0xf);
225c7b1f 713 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 714 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 715 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
716 dev_cap->reserved_mtts = 1 << (field >> 4);
717 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
718 dev_cap->max_mrw_sz = 1 << field;
719 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
720 dev_cap->reserved_mrws = 1 << (field & 0xf);
721 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
722 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
7ae0e400
MB		 723 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
724 dev_cap->num_sys_eqs = size & 0xfff;
225c7b1f
RD		 725 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
726 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
727 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
728 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 729 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
730 field &= 0x1f;
731 if (!field)
732 dev_cap->max_gso_sz = 0;
733 else
734 dev_cap->max_gso_sz = 1 << field;
735
b3416f44
SP		 736 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
737 if (field & 0x20)
738 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
739 if (field & 0x10)
740 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
741 field &= 0xf;
742 if (field) {
743 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
744 dev_cap->max_rss_tbl_sz = 1 << field;
745 } else
746 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 747 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
748 dev_cap->max_rdma_global = 1 << (field & 0x3f);
749 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
750 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 751 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 752 dev_cap->num_ports = field & 0xf;
149983af
DB		 753 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
754 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 755 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
756 if (field & 0x80)
757 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
758 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
4de65803
MB		 759 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
760 if (field & 0x80)
761 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
0ff1fb65
HHZ		 762 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
763 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 764 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
765 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 766 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
767 if (field & 0x80)
768 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 769 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 770 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 771 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 772 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
773 dev_cap->reserved_uars = field >> 4;
774 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
775 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
776 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
777 dev_cap->min_page_sz = 1 << field;
778
779 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
780 if (field & 0x80) {
781 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
782 dev_cap->bf_reg_size = 1 << (field & 0x1f);
783 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 784 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 785 field = 3;
225c7b1f
RD		 786 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
787 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
788 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
789 } else {
790 dev_cap->bf_reg_size = 0;
791 mlx4_dbg(dev, "BlueFlame not available\n");
792 }
793
794 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
795 dev_cap->max_sq_sg = field;
796 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
797 dev_cap->max_sq_desc_sz = size;
798
799 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
800 dev_cap->max_qp_per_mcg = 1 << field;
801 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
802 dev_cap->reserved_mgms = field & 0xf;
803 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
804 dev_cap->max_mcgs = 1 << field;
805 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
806 dev_cap->reserved_pds = field >> 4;
807 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
808 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 809 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
810 dev_cap->reserved_xrcds = field >> 4;
426dd00d 811 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 812 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 813
814 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
815 dev_cap->rdmarc_entry_sz = size;
816 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
817 dev_cap->qpc_entry_sz = size;
818 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
819 dev_cap->aux_entry_sz = size;
820 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
821 dev_cap->altc_entry_sz = size;
822 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
823 dev_cap->eqc_entry_sz = size;
824 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
825 dev_cap->cqc_entry_sz = size;
826 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
827 dev_cap->srq_entry_sz = size;
828 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
829 dev_cap->cmpt_entry_sz = size;
830 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
831 dev_cap->mtt_entry_sz = size;
832 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
833 dev_cap->dmpt_entry_sz = size;
834
835 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
836 dev_cap->max_srq_sz = 1 << field;
837 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
838 dev_cap->max_qp_sz = 1 << field;
839 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
840 dev_cap->resize_srq = field & 1;
841 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
842 dev_cap->max_rq_sg = field;
843 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
844 dev_cap->max_rq_desc_sz = size;
77507aa2 845 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
adbc7ac5
SM		 846 if (field & (1 << 5))
847 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
77507aa2
IS		 848 if (field & (1 << 6))
849 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
850 if (field & (1 << 7))
851 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
225c7b1f
RD		 852 MLX4_GET(dev_cap->bmme_flags, outbox,
853 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
d475c95b
MB		 854 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
855 if (field & 0x20)
856 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
225c7b1f
RD		 857 MLX4_GET(dev_cap->reserved_lkey, outbox,
858 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
a53e3e8c
SM		 859 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
860 if (field32 & (1 << 0))
861 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
955154fa
MB		 862 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
863 if (field & 1<<6)
5930e8d0 864 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
7ffdf726
OG		 865 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
866 if (field & 1<<3)
867 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
225c7b1f
RD		 868 MLX4_GET(dev_cap->max_icm_sz, outbox,
869 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 870 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
871 MLX4_GET(dev_cap->max_counters, outbox,
872 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 873
114840c3
JM		 874 MLX4_GET(field32, outbox,
875 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
876 if (field32 & (1 << 0))
877 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
878
3f7fb021 879 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 880 if (field32 & (1 << 16))
881 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
3f7fb021
RE		 882 if (field32 & (1 << 26))
883 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 884 if (field32 & (1 << 20))
885 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
de966c59
MB		 886 if (field32 & (1 << 21))
887 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
3f7fb021 888
431df8c7
MB		 889 for (i = 1; i <= dev_cap->num_ports; i++) {
890 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);
891 if (err)
892 goto out;
5ae2a7a8
RD		 893 }
894
95d04f07
RD		 895 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
896 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 897
898 /*
899 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
900 * we can't use any EQs whose doorbell falls on that page,
901 * even if the EQ itself isn't reserved.
902 */
7ae0e400
MB		 903 if (dev_cap->num_sys_eqs == 0)
904 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
905 dev_cap->reserved_eqs);
906 else
907 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
225c7b1f
RD		 908
909 mlx4_dbg(dev, "Max ICM size %lld MB\n",
910 (unsigned long long) dev_cap->max_icm_sz >> 20);
911 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
912 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
913 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
914 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
915 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
916 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
7ae0e400
MB		 917 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
918 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
919 dev_cap->eqc_entry_sz);
225c7b1f
RD		 920 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
921 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
922 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
923 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
924 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
925 dev_cap->max_pds, dev_cap->reserved_mgms);
926 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
927 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
928 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
431df8c7
MB		 929 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,
930 dev_cap->port_cap[1].max_port_width);
225c7b1f
RD		 931 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
932 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
933 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
934 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 935 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 936 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 937 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 938
939 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 940 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 941
942out:
943 mlx4_free_cmd_mailbox(dev, mailbox);
944 return err;
945}
946
431df8c7
MB		 947int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap)
948{
949 struct mlx4_cmd_mailbox *mailbox;
950 u32 *outbox;
951 u8 field;
952 u32 field32;
953 int err;
954
955 mailbox = mlx4_alloc_cmd_mailbox(dev);
956 if (IS_ERR(mailbox))
957 return PTR_ERR(mailbox);
958 outbox = mailbox->buf;
959
960 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
961 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
962 MLX4_CMD_TIME_CLASS_A,
963 MLX4_CMD_NATIVE);
964
965 if (err)
966 goto out;
967
968 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
969 port_cap->max_vl = field >> 4;
970 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
971 port_cap->ib_mtu = field >> 4;
972 port_cap->max_port_width = field & 0xf;
973 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
974 port_cap->max_gids = 1 << (field & 0xf);
975 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
976 port_cap->max_pkeys = 1 << (field & 0xf);
977 } else {
978#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
979#define QUERY_PORT_MTU_OFFSET 0x01
980#define QUERY_PORT_ETH_MTU_OFFSET 0x02
981#define QUERY_PORT_WIDTH_OFFSET 0x06
982#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
983#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
984#define QUERY_PORT_MAX_VL_OFFSET 0x0b
985#define QUERY_PORT_MAC_OFFSET 0x10
986#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
987#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
988#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
989
990 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT,
991 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
992 if (err)
993 goto out;
994
995 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
996 port_cap->supported_port_types = field & 3;
997 port_cap->suggested_type = (field >> 3) & 1;
998 port_cap->default_sense = (field >> 4) & 1;
999 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
1000 port_cap->ib_mtu = field & 0xf;
1001 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
1002 port_cap->max_port_width = field & 0xf;
1003 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
1004 port_cap->max_gids = 1 << (field >> 4);
1005 port_cap->max_pkeys = 1 << (field & 0xf);
1006 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
1007 port_cap->max_vl = field & 0xf;
1008 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
1009 port_cap->log_max_macs = field & 0xf;
1010 port_cap->log_max_vlans = field >> 4;
1011 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);
1012 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);
1013 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
1014 port_cap->trans_type = field32 >> 24;
1015 port_cap->vendor_oui = field32 & 0xffffff;
1016 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);
1017 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);
1018 }
1019
1020out:
1021 mlx4_free_cmd_mailbox(dev, mailbox);
1022 return err;
1023}
1024
383677da
OG		 1025#define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
1026#define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
1027#define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
1028
b91cb3eb
JM		 1029int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1030 struct mlx4_vhcr *vhcr,
1031 struct mlx4_cmd_mailbox *inbox,
1032 struct mlx4_cmd_mailbox *outbox,
1033 struct mlx4_cmd_info *cmd)
1034{
2a4fae14 1035 u64 flags;
b91cb3eb
JM		 1036 int err = 0;
1037 u8 field;
383677da 1038 u32 bmme_flags, field32;
449fc488
MB		 1039 int real_port;
1040 int slave_port;
1041 int first_port;
1042 struct mlx4_active_ports actv_ports;
b91cb3eb
JM		 1043
1044 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1045 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1046 if (err)
1047 return err;
1048
cc1ade94
SM		 1049 /* add port mng change event capability and disable mw type 1
1050 * unconditionally to slaves
1051 */
2a4fae14
JM		 1052 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1053 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 1054 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
449fc488
MB		 1055 actv_ports = mlx4_get_active_ports(dev, slave);
1056 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
1057 for (slave_port = 0, real_port = first_port;
1058 real_port < first_port +
1059 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
1060 ++real_port, ++slave_port) {
1061 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
1062 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
1063 else
1064 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1065 }
1066 for (; slave_port < dev->caps.num_ports; ++slave_port)
1067 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
2a4fae14
JM		 1068 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1069
449fc488
MB		 1070 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1071 field &= ~0x0F;
1072 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1073 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1074
30b40c31
AV		 1075 /* For guests, disable timestamp */
1076 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1077 field &= 0x7f;
1078 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1079
7ffdf726 1080 /* For guests, disable vxlan tunneling */
57352ef4 1081 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
7ffdf726
OG		 1082 field &= 0xf7;
1083 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1084
b91cb3eb
JM		 1085 /* For guests, report Blueflame disabled */
1086 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1087 field &= 0x7f;
1088 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1089
cc1ade94 1090 /* For guests, disable mw type 2 */
57352ef4 1091 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
cc1ade94
SM		 1092 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
1093 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1094
0081c8f3
JM		 1095 /* turn off device-managed steering capability if not enabled */
1096 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1097 MLX4_GET(field, outbox->buf,
1098 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1099 field &= 0x7f;
1100 MLX4_PUT(outbox->buf, field,
1101 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1102 }
4de65803
MB		 1103
1104 /* turn off ipoib managed steering for guests */
57352ef4 1105 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
4de65803
MB		 1106 field &= ~0x80;
1107 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1108
383677da
OG		 1109 /* turn off host side virt features (VST, FSM, etc) for guests */
1110 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1111 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS |
1112 DEV_CAP_EXT_2_FLAG_FSM);
1113 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1114
b91cb3eb
JM		 1115 return 0;
1116}
1117
5cc914f1
MA		 1118int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1119 struct mlx4_vhcr *vhcr,
1120 struct mlx4_cmd_mailbox *inbox,
1121 struct mlx4_cmd_mailbox *outbox,
1122 struct mlx4_cmd_info *cmd)
1123{
0eb62b93 1124 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 1125 u64 def_mac;
1126 u8 port_type;
6634961c 1127 u16 short_field;
5cc914f1 1128 int err;
948e306d 1129 int admin_link_state;
449fc488
MB		 1130 int port = mlx4_slave_convert_port(dev, slave,
1131 vhcr->in_modifier & 0xFF);
5cc914f1 1132
105c320f 1133#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 1134#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 1135#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1136#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 1137
449fc488
MB		 1138 if (port < 0)
1139 return -EINVAL;
1140
a7401b9c
JM		 1141 /* Protect against untrusted guests: enforce that this is the
1142 * QUERY_PORT general query.
1143 */
1144 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
1145 return -EINVAL;
1146
1147 vhcr->in_modifier = port;
449fc488 1148
5cc914f1
MA		 1149 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1150 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1151 MLX4_CMD_NATIVE);
1152
1153 if (!err && dev->caps.function != slave) {
0508ad64 1154 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 1155 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1156
1157 /* get port type - currently only eth is enabled */
1158 MLX4_GET(port_type, outbox->buf,
1159 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1160
105c320f
JM		 1161 /* No link sensing allowed */
1162 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1163 /* set port type to currently operating port type */
1164 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 1165
948e306d
RE		 1166 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1167 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1168 port_type |= MLX4_PORT_LINK_UP_MASK;
1169 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1170 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1171
5cc914f1
MA		 1172 MLX4_PUT(outbox->buf, port_type,
1173 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c 1174
b6ffaeff 1175 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
449fc488 1176 short_field = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 1177 else
1178 short_field = 1; /* slave max gids */
6634961c
JM		 1179 MLX4_PUT(outbox->buf, short_field,
1180 QUERY_PORT_CUR_MAX_GID_OFFSET);
1181
1182 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1183 MLX4_PUT(outbox->buf, short_field,
1184 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 1185 }
1186
1187 return err;
1188}
1189
6634961c
JM		 1190int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1191 int *gid_tbl_len, int *pkey_tbl_len)
1192{
1193 struct mlx4_cmd_mailbox *mailbox;
1194 u32 *outbox;
1195 u16 field;
1196 int err;
1197
1198 mailbox = mlx4_alloc_cmd_mailbox(dev);
1199 if (IS_ERR(mailbox))
1200 return PTR_ERR(mailbox);
1201
1202 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1203 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1204 MLX4_CMD_WRAPPED);
1205 if (err)
1206 goto out;
1207
1208 outbox = mailbox->buf;
1209
1210 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1211 *gid_tbl_len = field;
1212
1213 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1214 *pkey_tbl_len = field;
1215
1216out:
1217 mlx4_free_cmd_mailbox(dev, mailbox);
1218 return err;
1219}
1220EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1221
225c7b1f
RD		 1222int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1223{
1224 struct mlx4_cmd_mailbox *mailbox;
1225 struct mlx4_icm_iter iter;
1226 __be64 *pages;
1227 int lg;
1228 int nent = 0;
1229 int i;
1230 int err = 0;
1231 int ts = 0, tc = 0;
1232
1233 mailbox = mlx4_alloc_cmd_mailbox(dev);
1234 if (IS_ERR(mailbox))
1235 return PTR_ERR(mailbox);
225c7b1f
RD		 1236 pages = mailbox->buf;
1237
1238 for (mlx4_icm_first(icm, &iter);
1239 !mlx4_icm_last(&iter);
1240 mlx4_icm_next(&iter)) {
1241 /*
1242 * We have to pass pages that are aligned to their
1243 * size, so find the least significant 1 in the
1244 * address or size and use that as our log2 size.
1245 */
1246 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1247 if (lg < MLX4_ICM_PAGE_SHIFT) {
1a91de28
JP		 1248 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1249 MLX4_ICM_PAGE_SIZE,
1250 (unsigned long long) mlx4_icm_addr(&iter),
1251 mlx4_icm_size(&iter));
225c7b1f
RD		 1252 err = -EINVAL;
1253 goto out;
1254 }
1255
1256 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1257 if (virt != -1) {
1258 pages[nent * 2] = cpu_to_be64(virt);
1259 virt += 1 << lg;
1260 }
1261
1262 pages[nent * 2 + 1] =
1263 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1264 (lg - MLX4_ICM_PAGE_SHIFT));
1265 ts += 1 << (lg - 10);
1266 ++tc;
1267
1268 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1269 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 1270 MLX4_CMD_TIME_CLASS_B,
1271 MLX4_CMD_NATIVE);
225c7b1f
RD		 1272 if (err)
1273 goto out;
1274 nent = 0;
1275 }
1276 }
1277 }
1278
1279 if (nent)
f9baff50
JM		 1280 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1281 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1282 if (err)
1283 goto out;
1284
1285 switch (op) {
1286 case MLX4_CMD_MAP_FA:
1a91de28 1287 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
225c7b1f
RD		 1288 break;
1289 case MLX4_CMD_MAP_ICM_AUX:
1a91de28 1290 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
225c7b1f
RD		 1291 break;
1292 case MLX4_CMD_MAP_ICM:
1a91de28
JP		 1293 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1294 tc, ts, (unsigned long long) virt - (ts << 10));
225c7b1f
RD		 1295 break;
1296 }
1297
1298out:
1299 mlx4_free_cmd_mailbox(dev, mailbox);
1300 return err;
1301}
1302
1303int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1304{
1305 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1306}
1307
1308int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1309{
f9baff50
JM		 1310 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1311 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1312}
1313
1314
1315int mlx4_RUN_FW(struct mlx4_dev *dev)
1316{
f9baff50
JM		 1317 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1318 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1319}
1320
1321int mlx4_QUERY_FW(struct mlx4_dev *dev)
1322{
1323 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1324 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1325 struct mlx4_cmd_mailbox *mailbox;
1326 u32 *outbox;
1327 int err = 0;
1328 u64 fw_ver;
fe40900f 1329 u16 cmd_if_rev;
225c7b1f
RD		 1330 u8 lg;
1331
1332#define QUERY_FW_OUT_SIZE 0x100
1333#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1334#define QUERY_FW_PPF_ID 0x09
fe40900f 1335#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1336#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1337#define QUERY_FW_ERR_START_OFFSET 0x30
1338#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1339#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1340
1341#define QUERY_FW_SIZE_OFFSET 0x00
1342#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1343#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1344
5cc914f1
MA		 1345#define QUERY_FW_COMM_BASE_OFFSET 0x40
1346#define QUERY_FW_COMM_BAR_OFFSET 0x48
1347
ddd8a6c1
EE		 1348#define QUERY_FW_CLOCK_OFFSET 0x50
1349#define QUERY_FW_CLOCK_BAR 0x58
1350
225c7b1f
RD		 1351 mailbox = mlx4_alloc_cmd_mailbox(dev);
1352 if (IS_ERR(mailbox))
1353 return PTR_ERR(mailbox);
1354 outbox = mailbox->buf;
1355
1356 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1357 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1358 if (err)
1359 goto out;
1360
1361 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1362 /*
3e1db334 1363 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1364 * version, so swap here.
1365 */
1366 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1367 ((fw_ver & 0xffff0000ull) >> 16) |
1368 ((fw_ver & 0x0000ffffull) << 16);
1369
752a50ca
JM		 1370 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1371 dev->caps.function = lg;
1372
b91cb3eb
JM		 1373 if (mlx4_is_slave(dev))
1374 goto out;
1375
5cc914f1 1376
fe40900f 1377 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1378 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1379 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1a91de28 1380 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
fe40900f
RD		 1381 cmd_if_rev);
1382 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1383 (int) (dev->caps.fw_ver >> 32),
1384 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1385 (int) dev->caps.fw_ver & 0xffff);
1a91de28 1386 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
5ae2a7a8 1387 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1388 err = -ENODEV;
1389 goto out;
1390 }
1391
5ae2a7a8
RD		 1392 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1393 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1394
225c7b1f
RD		 1395 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1396 cmd->max_cmds = 1 << lg;
1397
fe40900f 1398 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1399 (int) (dev->caps.fw_ver >> 32),
1400 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1401 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1402 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1403
1404 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1405 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1406 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1407 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1408
1409 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1410 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1411
1412 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1413 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1414 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1415 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1416
5cc914f1
MA		 1417 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1418 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1419 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1420 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1421 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1422 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1423
ddd8a6c1
EE		 1424 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1425 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1426 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1427 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1428 fw->clock_bar, fw->clock_offset);
1429
225c7b1f
RD		 1430 /*
1431 * Round up number of system pages needed in case
1432 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1433 */
1434 fw->fw_pages =
1435 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1436 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1437
1438 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1439 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1440
1441out:
1442 mlx4_free_cmd_mailbox(dev, mailbox);
1443 return err;
1444}
1445
b91cb3eb
JM		 1446int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1447 struct mlx4_vhcr *vhcr,
1448 struct mlx4_cmd_mailbox *inbox,
1449 struct mlx4_cmd_mailbox *outbox,
1450 struct mlx4_cmd_info *cmd)
1451{
1452 u8 *outbuf;
1453 int err;
1454
1455 outbuf = outbox->buf;
1456 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1457 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1458 if (err)
1459 return err;
1460
752a50ca
JM		 1461 /* for slaves, set pci PPF ID to invalid and zero out everything
1462 * else except FW version */
b91cb3eb
JM		 1463 outbuf[0] = outbuf[1] = 0;
1464 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1465 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1466
b91cb3eb
JM		 1467 return 0;
1468}
1469
225c7b1f
RD		 1470static void get_board_id(void *vsd, char *board_id)
1471{
1472 int i;
1473
1474#define VSD_OFFSET_SIG1 0x00
1475#define VSD_OFFSET_SIG2 0xde
1476#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1477#define VSD_OFFSET_TS_BOARD_ID 0x20
1478
1479#define VSD_SIGNATURE_TOPSPIN 0x5ad
1480
1481 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1482
1483 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1484 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1485 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1486 } else {
1487 /*
1488 * The board ID is a string but the firmware byte
1489 * swaps each 4-byte word before passing it back to
1490 * us. Therefore we need to swab it before printing.
1491 */
1492 for (i = 0; i < 4; ++i)
1493 ((u32 *) board_id)[i] =
1494 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1495 }
1496}
1497
1498int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1499{
1500 struct mlx4_cmd_mailbox *mailbox;
1501 u32 *outbox;
1502 int err;
1503
1504#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1505#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1506#define QUERY_ADAPTER_VSD_OFFSET 0x20
1507
1508 mailbox = mlx4_alloc_cmd_mailbox(dev);
1509 if (IS_ERR(mailbox))
1510 return PTR_ERR(mailbox);
1511 outbox = mailbox->buf;
1512
1513 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1514 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1515 if (err)
1516 goto out;
1517
225c7b1f
RD		 1518 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1519
1520 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1521 adapter->board_id);
1522
1523out:
1524 mlx4_free_cmd_mailbox(dev, mailbox);
1525 return err;
1526}
1527
1528int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1529{
1530 struct mlx4_cmd_mailbox *mailbox;
1531 __be32 *inbox;
1532 int err;
1533
1534#define INIT_HCA_IN_SIZE 0x200
1535#define INIT_HCA_VERSION_OFFSET 0x000
1536#define INIT_HCA_VERSION 2
7ffdf726 1537#define INIT_HCA_VXLAN_OFFSET 0x0c
c57e20dc 1538#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1539#define INIT_HCA_FLAGS_OFFSET 0x014
1540#define INIT_HCA_QPC_OFFSET 0x020
1541#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1542#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1543#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1544#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1545#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1546#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1547#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
77507aa2 1548#define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
225c7b1f
RD		 1549#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1550#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1551#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1552#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
7ae0e400 1553#define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
225c7b1f
RD		 1554#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1555#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1556#define INIT_HCA_MCAST_OFFSET 0x0c0
1557#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1558#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1559#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1560#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1561#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1562#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1563#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1564#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1565#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1566#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1567#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1568#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1569#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1570#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1571#define INIT_HCA_TPT_OFFSET 0x0f0
1572#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1573#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1574#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1575#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1576#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1577#define INIT_HCA_UAR_OFFSET 0x120
1578#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1579#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1580
1581 mailbox = mlx4_alloc_cmd_mailbox(dev);
1582 if (IS_ERR(mailbox))
1583 return PTR_ERR(mailbox);
1584 inbox = mailbox->buf;
1585
225c7b1f
RD		 1586 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1587
c57e20dc
EC		 1588 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1589 (ilog2(cache_line_size()) - 4) << 5;
1590
225c7b1f
RD		 1591#if defined(__LITTLE_ENDIAN)
1592 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1593#elif defined(__BIG_ENDIAN)
1594 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1595#else
1596#error Host endianness not defined
1597#endif
1598 /* Check port for UD address vector: */
1599 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1600
8ff095ec
EC		 1601 /* Enable IPoIB checksumming if we can: */
1602 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1603 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1604
51f5f0ee
JM		 1605 /* Enable QoS support if module parameter set */
1606 if (enable_qos)
1607 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1608
f2a3f6a3
OG		 1609 /* enable counters */
1610 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1611 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1612
08ff3235
OG		 1613 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1614 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1615 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1616 dev->caps.eqe_size = 64;
1617 dev->caps.eqe_factor = 1;
1618 } else {
1619 dev->caps.eqe_size = 32;
1620 dev->caps.eqe_factor = 0;
1621 }
1622
1623 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1624 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1625 dev->caps.cqe_size = 64;
77507aa2 1626 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1627 } else {
1628 dev->caps.cqe_size = 32;
1629 }
1630
77507aa2
IS		 1631 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1632 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1633 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1634 dev->caps.eqe_size = cache_line_size();
1635 dev->caps.cqe_size = cache_line_size();
1636 dev->caps.eqe_factor = 0;
1637 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1638 (ilog2(dev->caps.eqe_size) - 5)),
1639 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1640
1641 /* User still need to know to support CQE > 32B */
1642 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1643 }
1644
225c7b1f
RD		 1645 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1646
1647 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1648 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1649 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1650 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1651 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1652 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1653 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1654 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1655 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1656 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1657 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
225c7b1f
RD		 1658 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1659 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1660
0ff1fb65
HHZ		 1661 /* steering attributes */
1662 if (dev->caps.steering_mode ==
1663 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1664 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1665 cpu_to_be32(1 <<
1666 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1667
1668 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1669 MLX4_PUT(inbox, param->log_mc_entry_sz,
1670 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1671 MLX4_PUT(inbox, param->log_mc_table_sz,
1672 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1673 /* Enable Ethernet flow steering
1674 * with udp unicast and tcp unicast
1675 */
23537b73 1676 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1677 INIT_HCA_FS_ETH_BITS_OFFSET);
1678 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1679 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1680 /* Enable IPoIB flow steering
1681 * with udp unicast and tcp unicast
1682 */
23537b73 1683 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1684 INIT_HCA_FS_IB_BITS_OFFSET);
1685 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1686 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1687 } else {
1688 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1689 MLX4_PUT(inbox, param->log_mc_entry_sz,
1690 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1691 MLX4_PUT(inbox, param->log_mc_hash_sz,
1692 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1693 MLX4_PUT(inbox, param->log_mc_table_sz,
1694 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1695 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1696 MLX4_PUT(inbox, (u8) (1 << 3),
1697 INIT_HCA_UC_STEERING_OFFSET);
1698 }
225c7b1f
RD		 1699
1700 /* TPT attributes */
1701
1702 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1703 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1704 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1705 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1706 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1707
1708 /* UAR attributes */
1709
ab9c17a0 1710 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1711 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1712
7ffdf726
OG		 1713 /* set parser VXLAN attributes */
1714 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1715 u8 parser_params = 0;
1716 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1717 }
1718
f9baff50
JM		 1719 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1720 MLX4_CMD_NATIVE);
225c7b1f
RD		 1721
1722 if (err)
1723 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1724
1725 mlx4_free_cmd_mailbox(dev, mailbox);
1726 return err;
1727}
1728
ab9c17a0
JM		 1729int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1730 struct mlx4_init_hca_param *param)
1731{
1732 struct mlx4_cmd_mailbox *mailbox;
1733 __be32 *outbox;
7b8157be 1734 u32 dword_field;
ab9c17a0 1735 int err;
08ff3235 1736 u8 byte_field;
ab9c17a0
JM		 1737
1738#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1739#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1740
1741 mailbox = mlx4_alloc_cmd_mailbox(dev);
1742 if (IS_ERR(mailbox))
1743 return PTR_ERR(mailbox);
1744 outbox = mailbox->buf;
1745
1746 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1747 MLX4_CMD_QUERY_HCA,
1748 MLX4_CMD_TIME_CLASS_B,
1749 !mlx4_is_slave(dev));
1750 if (err)
1751 goto out;
1752
1753 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1754 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1755
1756 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1757
1758 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1759 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1760 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1761 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1762 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1763 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1764 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1765 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1766 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1767 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1768 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
ab9c17a0
JM		 1769 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1770 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1771
7b8157be
JM		 1772 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1773 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1774 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1775 } else {
1776 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1777 if (byte_field & 0x8)
1778 param->steering_mode = MLX4_STEERING_MODE_B0;
1779 else
1780 param->steering_mode = MLX4_STEERING_MODE_A0;
1781 }
0ff1fb65 1782 /* steering attributes */
7b8157be 1783 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1784 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1785 MLX4_GET(param->log_mc_entry_sz, outbox,
1786 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1787 MLX4_GET(param->log_mc_table_sz, outbox,
1788 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1789 } else {
1790 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1791 MLX4_GET(param->log_mc_entry_sz, outbox,
1792 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1793 MLX4_GET(param->log_mc_hash_sz, outbox,
1794 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1795 MLX4_GET(param->log_mc_table_sz, outbox,
1796 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1797 }
ab9c17a0 1798
08ff3235
OG		 1799 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1800 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1801 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1802 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1803 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1804 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1805
77507aa2
IS		 1806 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1807 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1808 if (byte_field) {
1809 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1810 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1811 param->cqe_size = 1 << ((byte_field &
1812 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
1813 param->eqe_size = 1 << (((byte_field &
1814 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
1815 }
1816
ab9c17a0
JM		 1817 /* TPT attributes */
1818
1819 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1820 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1821 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1822 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1823 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1824
1825 /* UAR attributes */
1826
1827 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1828 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1829
1830out:
1831 mlx4_free_cmd_mailbox(dev, mailbox);
1832
1833 return err;
1834}
1835
980e9001
JM		 1836/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1837 * and real QP0 are active, so that the paravirtualized QP0 is ready
1838 * to operate */
1839static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1840{
1841 struct mlx4_priv *priv = mlx4_priv(dev);
1842 /* irrelevant if not infiniband */
1843 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1844 priv->mfunc.master.qp0_state[port].qp0_active)
1845 return 1;
1846 return 0;
1847}
1848
5cc914f1
MA		 1849int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1850 struct mlx4_vhcr *vhcr,
1851 struct mlx4_cmd_mailbox *inbox,
1852 struct mlx4_cmd_mailbox *outbox,
1853 struct mlx4_cmd_info *cmd)
1854{
1855 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1856 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1857 int err;
1858
449fc488
MB		 1859 if (port < 0)
1860 return -EINVAL;
1861
5cc914f1
MA		 1862 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1863 return 0;
1864
980e9001
JM		 1865 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1866 /* Enable port only if it was previously disabled */
1867 if (!priv->mfunc.master.init_port_ref[port]) {
1868 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1869 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1870 if (err)
1871 return err;
1872 }
1873 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1874 } else {
1875 if (slave == mlx4_master_func_num(dev)) {
1876 if (check_qp0_state(dev, slave, port) &&
1877 !priv->mfunc.master.qp0_state[port].port_active) {
1878 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1879 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1880 if (err)
1881 return err;
1882 priv->mfunc.master.qp0_state[port].port_active = 1;
1883 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1884 }
1885 } else
1886 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1887 }
1888 ++priv->mfunc.master.init_port_ref[port];
1889 return 0;
1890}
1891
5ae2a7a8 1892int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1893{
1894 struct mlx4_cmd_mailbox *mailbox;
1895 u32 *inbox;
1896 int err;
1897 u32 flags;
5ae2a7a8 1898 u16 field;
225c7b1f 1899
5ae2a7a8 1900 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1901#define INIT_PORT_IN_SIZE 256
1902#define INIT_PORT_FLAGS_OFFSET 0x00
1903#define INIT_PORT_FLAG_SIG (1 << 18)
1904#define INIT_PORT_FLAG_NG (1 << 17)
1905#define INIT_PORT_FLAG_G0 (1 << 16)
1906#define INIT_PORT_VL_SHIFT 4
1907#define INIT_PORT_PORT_WIDTH_SHIFT 8
1908#define INIT_PORT_MTU_OFFSET 0x04
1909#define INIT_PORT_MAX_GID_OFFSET 0x06
1910#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1911#define INIT_PORT_GUID0_OFFSET 0x10
1912#define INIT_PORT_NODE_GUID_OFFSET 0x18
1913#define INIT_PORT_SI_GUID_OFFSET 0x20
1914
5ae2a7a8
RD		 1915 mailbox = mlx4_alloc_cmd_mailbox(dev);
1916 if (IS_ERR(mailbox))
1917 return PTR_ERR(mailbox);
1918 inbox = mailbox->buf;
225c7b1f 1919
5ae2a7a8
RD		 1920 flags = 0;
1921 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1922 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1923 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1924
b79acb49 1925 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1926 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1927 field = dev->caps.gid_table_len[port];
1928 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1929 field = dev->caps.pkey_table_len[port];
1930 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1931
5ae2a7a8 1932 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1933 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1934
5ae2a7a8
RD		 1935 mlx4_free_cmd_mailbox(dev, mailbox);
1936 } else
1937 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1938 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1939
1940 return err;
1941}
1942EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1943
5cc914f1
MA		 1944int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1945 struct mlx4_vhcr *vhcr,
1946 struct mlx4_cmd_mailbox *inbox,
1947 struct mlx4_cmd_mailbox *outbox,
1948 struct mlx4_cmd_info *cmd)
1949{
1950 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1951 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1952 int err;
1953
449fc488
MB		 1954 if (port < 0)
1955 return -EINVAL;
1956
5cc914f1
MA		 1957 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1958 (1 << port)))
1959 return 0;
1960
980e9001
JM		 1961 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1962 if (priv->mfunc.master.init_port_ref[port] == 1) {
1963 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1964 1000, MLX4_CMD_NATIVE);
1965 if (err)
1966 return err;
1967 }
1968 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1969 } else {
1970 /* infiniband port */
1971 if (slave == mlx4_master_func_num(dev)) {
1972 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1973 priv->mfunc.master.qp0_state[port].port_active) {
1974 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1975 1000, MLX4_CMD_NATIVE);
1976 if (err)
1977 return err;
1978 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1979 priv->mfunc.master.qp0_state[port].port_active = 0;
1980 }
1981 } else
1982 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1983 }
5cc914f1
MA		 1984 --priv->mfunc.master.init_port_ref[port];
1985 return 0;
1986}
1987
225c7b1f
RD		 1988int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1989{
f9baff50
JM		 1990 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1991 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1992}
1993EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1994
1995int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1996{
f9baff50
JM		 1997 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1998 MLX4_CMD_NATIVE);
225c7b1f
RD		 1999}
2000
d18f141a
OG		 2001struct mlx4_config_dev {
2002 __be32 update_flags;
d475c95b 2003 __be32 rsvd1[3];
d18f141a
OG		 2004 __be16 vxlan_udp_dport;
2005 __be16 rsvd2;
d475c95b
MB		 2006 __be32 rsvd3[27];
2007 __be16 rsvd4;
2008 u8 rsvd5;
2009 u8 rx_checksum_val;
d18f141a
OG		 2010};
2011
2012#define MLX4_VXLAN_UDP_DPORT (1 << 0)
2013
d475c95b 2014static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
d18f141a
OG		 2015{
2016 int err;
2017 struct mlx4_cmd_mailbox *mailbox;
2018
2019 mailbox = mlx4_alloc_cmd_mailbox(dev);
2020 if (IS_ERR(mailbox))
2021 return PTR_ERR(mailbox);
2022
2023 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
2024
2025 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
2026 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2027
2028 mlx4_free_cmd_mailbox(dev, mailbox);
2029 return err;
2030}
2031
d475c95b
MB		 2032static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2033{
2034 int err;
2035 struct mlx4_cmd_mailbox *mailbox;
2036
2037 mailbox = mlx4_alloc_cmd_mailbox(dev);
2038 if (IS_ERR(mailbox))
2039 return PTR_ERR(mailbox);
2040
2041 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV,
2042 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2043
2044 if (!err)
2045 memcpy(config_dev, mailbox->buf, sizeof(*config_dev));
2046
2047 mlx4_free_cmd_mailbox(dev, mailbox);
2048 return err;
2049}
2050
2051/* Conversion between the HW values and the actual functionality.
2052 * The value represented by the array index,
2053 * and the functionality determined by the flags.
2054 */
2055static const u8 config_dev_csum_flags[] = {
2056 [0] = 0,
2057 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP,
2058 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP |
2059 MLX4_RX_CSUM_MODE_L4,
2060 [3] = MLX4_RX_CSUM_MODE_L4 |
2061 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP |
2062 MLX4_RX_CSUM_MODE_MULTI_VLAN
2063};
2064
2065int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
2066 struct mlx4_config_dev_params *params)
2067{
2068 struct mlx4_config_dev config_dev;
2069 int err;
2070 u8 csum_mask;
2071
2072#define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2073#define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2074#define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2075
2076 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2077 return -ENOTSUPP;
2078
2079 err = mlx4_CONFIG_DEV_get(dev, &config_dev);
2080 if (err)
2081 return err;
2082
2083 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) &
2084 CONFIG_DEV_RX_CSUM_MODE_MASK;
2085
2086 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2087 return -EINVAL;
2088 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask];
2089
2090 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) &
2091 CONFIG_DEV_RX_CSUM_MODE_MASK;
2092
2093 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2094 return -EINVAL;
2095 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask];
2096
2097 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport);
2098
2099 return 0;
2100}
2101EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval);
2102
d18f141a
OG		 2103int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
2104{
2105 struct mlx4_config_dev config_dev;
2106
2107 memset(&config_dev, 0, sizeof(config_dev));
2108 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
2109 config_dev.vxlan_udp_dport = udp_port;
2110
d475c95b 2111 return mlx4_CONFIG_DEV_set(dev, &config_dev);
d18f141a
OG		 2112}
2113EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
2114
2115
225c7b1f
RD		 2116int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
2117{
2118 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
2119 MLX4_CMD_SET_ICM_SIZE,
f9baff50 2120 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 2121 if (ret)
2122 return ret;
2123
2124 /*
2125 * Round up number of system pages needed in case
2126 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2127 */
2128 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
2129 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
2130
2131 return 0;
2132}
2133
2134int mlx4_NOP(struct mlx4_dev *dev)
2135{
2136 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 2137 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 2138}
14c07b13 2139
8e1a28e8
HHZ		 2140int mlx4_get_phys_port_id(struct mlx4_dev *dev)
2141{
2142 u8 port;
2143 u32 *outbox;
2144 struct mlx4_cmd_mailbox *mailbox;
2145 u32 in_mod;
2146 u32 guid_hi, guid_lo;
2147 int err, ret = 0;
2148#define MOD_STAT_CFG_PORT_OFFSET 8
2149#define MOD_STAT_CFG_GUID_H 0X14
2150#define MOD_STAT_CFG_GUID_L 0X1c
2151
2152 mailbox = mlx4_alloc_cmd_mailbox(dev);
2153 if (IS_ERR(mailbox))
2154 return PTR_ERR(mailbox);
2155 outbox = mailbox->buf;
2156
2157 for (port = 1; port <= dev->caps.num_ports; port++) {
2158 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
2159 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
2160 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2161 MLX4_CMD_NATIVE);
2162 if (err) {
2163 mlx4_err(dev, "Fail to get port %d uplink guid\n",
2164 port);
2165 ret = err;
2166 } else {
2167 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2168 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2169 dev->caps.phys_port_id[port] = (u64)guid_lo |
2170 (u64)guid_hi << 32;
2171 }
2172 }
2173 mlx4_free_cmd_mailbox(dev, mailbox);
2174 return ret;
2175}
2176
14c07b13
YP		 2177#define MLX4_WOL_SETUP_MODE (5 << 28)
2178int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
2179{
2180 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2181
2182 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 2183 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2184 MLX4_CMD_NATIVE);
14c07b13
YP		 2185}
2186EXPORT_SYMBOL_GPL(mlx4_wol_read);
2187
2188int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
2189{
2190 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2191
2192 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 2193 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 2194}
2195EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 2196
2197enum {
2198 ADD_TO_MCG = 0x26,
2199};
2200
2201
2202void mlx4_opreq_action(struct work_struct *work)
2203{
2204 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
2205 opreq_task);
2206 struct mlx4_dev *dev = &priv->dev;
2207 int num_tasks = atomic_read(&priv->opreq_count);
2208 struct mlx4_cmd_mailbox *mailbox;
2209 struct mlx4_mgm *mgm;
2210 u32 *outbox;
2211 u32 modifier;
2212 u16 token;
fe6f700d
YP		 2213 u16 type;
2214 int err;
2215 u32 num_qps;
2216 struct mlx4_qp qp;
2217 int i;
2218 u8 rem_mcg;
2219 u8 prot;
2220
2221#define GET_OP_REQ_MODIFIER_OFFSET 0x08
2222#define GET_OP_REQ_TOKEN_OFFSET 0x14
2223#define GET_OP_REQ_TYPE_OFFSET 0x1a
2224#define GET_OP_REQ_DATA_OFFSET 0x20
2225
2226 mailbox = mlx4_alloc_cmd_mailbox(dev);
2227 if (IS_ERR(mailbox)) {
2228 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2229 return;
2230 }
2231 outbox = mailbox->buf;
2232
2233 while (num_tasks) {
2234 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2235 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2236 MLX4_CMD_NATIVE);
2237 if (err) {
6d3be300 2238 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 2239 err);
2240 return;
2241 }
2242 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2243 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2244 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 2245 type &= 0xfff;
2246
2247 switch (type) {
2248 case ADD_TO_MCG:
2249 if (dev->caps.steering_mode ==
2250 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2251 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2252 err = EPERM;
2253 break;
2254 }
2255 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2256 GET_OP_REQ_DATA_OFFSET);
2257 num_qps = be32_to_cpu(mgm->members_count) &
2258 MGM_QPN_MASK;
2259 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2260 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2261
2262 for (i = 0; i < num_qps; i++) {
2263 qp.qpn = be32_to_cpu(mgm->qp[i]);
2264 if (rem_mcg)
2265 err = mlx4_multicast_detach(dev, &qp,
2266 mgm->gid,
2267 prot, 0);
2268 else
2269 err = mlx4_multicast_attach(dev, &qp,
2270 mgm->gid,
2271 mgm->gid[5]
2272 , 0, prot,
2273 NULL);
2274 if (err)
2275 break;
2276 }
2277 break;
2278 default:
2279 mlx4_warn(dev, "Bad type for required operation\n");
2280 err = EINVAL;
2281 break;
2282 }
28d222bb
EP		 2283 err = mlx4_cmd(dev, 0, ((u32) err |
2284 (__force u32)cpu_to_be32(token) << 16),
fe6f700d
YP		 2285 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2286 MLX4_CMD_NATIVE);
2287 if (err) {
2288 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2289 err);
2290 goto out;
2291 }
2292 memset(outbox, 0, 0xffc);
2293 num_tasks = atomic_dec_return(&priv->opreq_count);
2294 }
2295
2296out:
2297 mlx4_free_cmd_mailbox(dev, mailbox);
2298}
114840c3
JM		 2299
2300static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2301 struct mlx4_cmd_mailbox *mailbox)
2302{
2303#define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2304#define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2305#define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2306#define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2307
2308 u32 set_attr_mask, getresp_attr_mask;
2309 u32 trap_attr_mask, traprepress_attr_mask;
2310
2311 MLX4_GET(set_attr_mask, mailbox->buf,
2312 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2313 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2314 set_attr_mask);
2315
2316 MLX4_GET(getresp_attr_mask, mailbox->buf,
2317 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2318 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2319 getresp_attr_mask);
2320
2321 MLX4_GET(trap_attr_mask, mailbox->buf,
2322 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2323 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2324 trap_attr_mask);
2325
2326 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2327 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2328 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2329 traprepress_attr_mask);
2330
2331 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2332 traprepress_attr_mask)
2333 return 1;
2334
2335 return 0;
2336}
2337
2338int mlx4_config_mad_demux(struct mlx4_dev *dev)
2339{
2340 struct mlx4_cmd_mailbox *mailbox;
2341 int secure_host_active;
2342 int err;
2343
2344 /* Check if mad_demux is supported */
2345 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2346 return 0;
2347
2348 mailbox = mlx4_alloc_cmd_mailbox(dev);
2349 if (IS_ERR(mailbox)) {
2350 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2351 return -ENOMEM;
2352 }
2353
2354 /* Query mad_demux to find out which MADs are handled by internal sma */
2355 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2356 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2357 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2358 if (err) {
2359 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2360 err);
2361 goto out;
2362 }
2363
2364 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2365
2366 /* Config mad_demux to handle all MADs returned by the query above */
2367 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2368 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2369 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2370 if (err) {
2371 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2372 goto out;
2373 }
2374
2375 if (secure_host_active)
2376 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2377out:
2378 mlx4_free_cmd_mailbox(dev, mailbox);
2379 return err;
2380}
adbc7ac5
SM		 2381
2382/* Access Reg commands */
2383enum mlx4_access_reg_masks {
2384 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2385 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2386 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2387};
2388
2389struct mlx4_access_reg {
2390 __be16 constant1;
2391 u8 status;
2392 u8 resrvd1;
2393 __be16 reg_id;
2394 u8 method;
2395 u8 constant2;
2396 __be32 resrvd2[2];
2397 __be16 len_const;
2398 __be16 resrvd3;
2399#define MLX4_ACCESS_REG_HEADER_SIZE (20)
2400 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2401} __attribute__((__packed__));
2402
2403/**
2404 * mlx4_ACCESS_REG - Generic access reg command.
2405 * @dev: mlx4_dev.
2406 * @reg_id: register ID to access.
2407 * @method: Access method Read/Write.
2408 * @reg_len: register length to Read/Write in bytes.
2409 * @reg_data: reg_data pointer to Read/Write From/To.
2410 *
2411 * Access ConnectX registers FW command.
2412 * Returns 0 on success and copies outbox mlx4_access_reg data
2413 * field into reg_data or a negative error code.
2414 */
2415static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2416 enum mlx4_access_reg_method method,
2417 u16 reg_len, void *reg_data)
2418{
2419 struct mlx4_cmd_mailbox *inbox, *outbox;
2420 struct mlx4_access_reg *inbuf, *outbuf;
2421 int err;
2422
2423 inbox = mlx4_alloc_cmd_mailbox(dev);
2424 if (IS_ERR(inbox))
2425 return PTR_ERR(inbox);
2426
2427 outbox = mlx4_alloc_cmd_mailbox(dev);
2428 if (IS_ERR(outbox)) {
2429 mlx4_free_cmd_mailbox(dev, inbox);
2430 return PTR_ERR(outbox);
2431 }
2432
2433 inbuf = inbox->buf;
2434 outbuf = outbox->buf;
2435
2436 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2437 inbuf->constant2 = 0x1;
2438 inbuf->reg_id = cpu_to_be16(reg_id);
2439 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2440
2441 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2442 inbuf->len_const =
2443 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2444 ((0x3) << 12));
2445
2446 memcpy(inbuf->reg_data, reg_data, reg_len);
2447 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2448 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
6e806699 2449 MLX4_CMD_WRAPPED);
adbc7ac5
SM		 2450 if (err)
2451 goto out;
2452
2453 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2454 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2455 mlx4_err(dev,
2456 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2457 reg_id, err);
2458 goto out;
2459 }
2460
2461 memcpy(reg_data, outbuf->reg_data, reg_len);
2462out:
2463 mlx4_free_cmd_mailbox(dev, inbox);
2464 mlx4_free_cmd_mailbox(dev, outbox);
2465 return err;
2466}
2467
2468/* ConnectX registers IDs */
2469enum mlx4_reg_id {
2470 MLX4_REG_ID_PTYS = 0x5004,
2471};
2472
2473/**
2474 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2475 * register
2476 * @dev: mlx4_dev.
2477 * @method: Access method Read/Write.
2478 * @ptys_reg: PTYS register data pointer.
2479 *
2480 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2481 * configuration
2482 * Returns 0 on success or a negative error code.
2483 */
2484int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2485 enum mlx4_access_reg_method method,
2486 struct mlx4_ptys_reg *ptys_reg)
2487{
2488 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2489 method, sizeof(*ptys_reg), ptys_reg);
2490}
2491EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
6e806699
SM		 2492
2493int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2494 struct mlx4_vhcr *vhcr,
2495 struct mlx4_cmd_mailbox *inbox,
2496 struct mlx4_cmd_mailbox *outbox,
2497 struct mlx4_cmd_info *cmd)
2498{
2499 struct mlx4_access_reg *inbuf = inbox->buf;
2500 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2501 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2502
2503 if (slave != mlx4_master_func_num(dev) &&
2504 method == MLX4_ACCESS_REG_WRITE)
2505 return -EPERM;
2506
2507 if (reg_id == MLX4_REG_ID_PTYS) {
2508 struct mlx4_ptys_reg *ptys_reg =
2509 (struct mlx4_ptys_reg *)inbuf->reg_data;
2510
2511 ptys_reg->local_port =
2512 mlx4_slave_convert_port(dev, slave,
2513 ptys_reg->local_port);
2514 }
2515
2516 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2517 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2518 MLX4_CMD_NATIVE);
2519}
Linux 6.x block layer and io_uring tree(s)