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net/mlx4_core: Add explicit error message when rule doesn't meet configuration
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
4d531aa8 94 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
540b3a39 112 [53] = "Port ETS Scheduler support",
4d531aa8 113 [55] = "Port link type sensing support",
00f5ce99 114 [59] = "Port management change event support",
08ff3235
OG		 115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
225c7b1f
RD		 117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 122 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
b3416f44
SP		 126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 131 [2] = "RSS XOR Hash Function support",
56cb4567 132 [3] = "Device managed flow steering support",
d998735f 133 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
b01978ca 136 [7] = "FSM (MAC anti-spoofing) support",
7ffdf726 137 [8] = "Dynamic QP updates support",
56cb4567 138 [9] = "Device managed flow steering IPoIB support",
114840c3 139 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
77507aa2
IS		 140 [11] = "MAD DEMUX (Secure-Host) support",
141 [12] = "Large cache line (>64B) CQE stride support",
adbc7ac5 142 [13] = "Large cache line (>64B) EQE stride support",
a53e3e8c 143 [14] = "Ethernet protocol control support",
d475c95b 144 [15] = "Ethernet Backplane autoneg support",
7ae0e400 145 [16] = "CONFIG DEV support",
de966c59
MB		 146 [17] = "Asymmetric EQs support",
147 [18] = "More than 80 VFs support"
b3416f44
SP		 148 };
149 int i;
150
151 for (i = 0; i < ARRAY_SIZE(fname); ++i)
152 if (fname[i] && (flags & (1LL << i)))
153 mlx4_dbg(dev, " %s\n", fname[i]);
154}
155
2d928651
VS		 156int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
157{
158 struct mlx4_cmd_mailbox *mailbox;
159 u32 *inbox;
160 int err = 0;
161
162#define MOD_STAT_CFG_IN_SIZE 0x100
163
164#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
165#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
166
167 mailbox = mlx4_alloc_cmd_mailbox(dev);
168 if (IS_ERR(mailbox))
169 return PTR_ERR(mailbox);
170 inbox = mailbox->buf;
171
2d928651
VS		 172 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
173 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
174
175 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 176 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 177
178 mlx4_free_cmd_mailbox(dev, mailbox);
179 return err;
180}
181
e8c4265b
MB		 182int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave)
183{
184 struct mlx4_cmd_mailbox *mailbox;
185 u32 *outbox;
186 u8 in_modifier;
187 u8 field;
188 u16 field16;
189 int err;
190
191#define QUERY_FUNC_BUS_OFFSET 0x00
192#define QUERY_FUNC_DEVICE_OFFSET 0x01
193#define QUERY_FUNC_FUNCTION_OFFSET 0x01
194#define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
195#define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
196#define QUERY_FUNC_MAX_EQ_OFFSET 0x06
197#define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
198
199 mailbox = mlx4_alloc_cmd_mailbox(dev);
200 if (IS_ERR(mailbox))
201 return PTR_ERR(mailbox);
202 outbox = mailbox->buf;
203
204 in_modifier = slave;
e8c4265b
MB		 205
206 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0,
207 MLX4_CMD_QUERY_FUNC,
208 MLX4_CMD_TIME_CLASS_A,
209 MLX4_CMD_NATIVE);
210 if (err)
211 goto out;
212
213 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
214 func->bus = field & 0xf;
215 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
216 func->device = field & 0xf1;
217 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
218 func->function = field & 0x7;
219 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
220 func->physical_function = field & 0xf;
221 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
222 func->rsvd_eqs = field16 & 0xffff;
223 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
224 func->max_eq = field16 & 0xffff;
225 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
226 func->rsvd_uars = field & 0x0f;
227
228 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
229 func->bus, func->device, func->function, func->physical_function,
230 func->max_eq, func->rsvd_eqs, func->rsvd_uars);
231
232out:
233 mlx4_free_cmd_mailbox(dev, mailbox);
234 return err;
235}
236
5cc914f1
MA		 237int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
238 struct mlx4_vhcr *vhcr,
239 struct mlx4_cmd_mailbox *inbox,
240 struct mlx4_cmd_mailbox *outbox,
241 struct mlx4_cmd_info *cmd)
242{
5a0d0a61 243 struct mlx4_priv *priv = mlx4_priv(dev);
99ec41d0
JM		 244 u8 field, port;
245 u32 size, proxy_qp, qkey;
5cc914f1 246 int err = 0;
7ae0e400 247 struct mlx4_func func;
5cc914f1
MA		 248
249#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
250#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 251#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 252#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 253#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
254#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
255#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
256#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
257#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
258#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 259#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 260#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 261
eb456a68
JM		 262#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
263#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
264#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
265#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
266#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
267#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
268
ddae0349
EE		 269#define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c
270
105c320f
JM		 271#define QUERY_FUNC_CAP_FMR_FLAG 0x80
272#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
273#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 274#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
ddae0349
EE		 275#define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04
276
277#define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31)
d57febe1 278#define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30)
105c320f
JM		 279
280/* when opcode modifier = 1 */
5cc914f1 281#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
99ec41d0 282#define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
73e74ab4
HHZ		 283#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
284#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 285
47605df9
JM		 286#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
287#define QUERY_FUNC_CAP_QP0_PROXY 0x14
288#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
289#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
8e1a28e8 290#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
47605df9 291
73e74ab4
HHZ		 292#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
293#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
eb17711b 294#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
99ec41d0 295#define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
105c320f 296
73e74ab4 297#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
7ae0e400 298#define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
105c320f 299
5cc914f1 300 if (vhcr->op_modifier == 1) {
449fc488
MB		 301 struct mlx4_active_ports actv_ports =
302 mlx4_get_active_ports(dev, slave);
303 int converted_port = mlx4_slave_convert_port(
304 dev, slave, vhcr->in_modifier);
305
306 if (converted_port < 0)
307 return -EINVAL;
308
309 vhcr->in_modifier = converted_port;
449fc488
MB		 310 /* phys-port = logical-port */
311 field = vhcr->in_modifier -
312 find_first_bit(actv_ports.ports, dev->caps.num_ports);
47605df9
JM		 313 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
314
99ec41d0
JM		 315 port = vhcr->in_modifier;
316 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
317
318 /* Set nic_info bit to mark new fields support */
319 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
320
321 if (mlx4_vf_smi_enabled(dev, slave, port) &&
322 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
323 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
324 MLX4_PUT(outbox->buf, qkey,
325 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
326 }
327 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
328
47605df9 329 /* size is now the QP number */
99ec41d0 330 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
47605df9
JM		 331 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
332
333 size += 2;
334 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
335
99ec41d0
JM		 336 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
337 proxy_qp += 2;
338 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
47605df9 339
8e1a28e8
HHZ		 340 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
341 QUERY_FUNC_CAP_PHYS_PORT_ID);
342
5cc914f1 343 } else if (vhcr->op_modifier == 0) {
449fc488
MB		 344 struct mlx4_active_ports actv_ports =
345 mlx4_get_active_ports(dev, slave);
eb456a68
JM		 346 /* enable rdma and ethernet interfaces, and new quota locations */
347 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
ddae0349 348 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX);
5cc914f1
MA		 349 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
350
449fc488
MB		 351 field = min(
352 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
353 dev->caps.num_ports);
5cc914f1
MA		 354 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
355
08ff3235 356 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 357 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
358
105c320f
JM		 359 field = 0; /* protected FMR support not available as yet */
360 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
361
5a0d0a61 362 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 363 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 364 size = dev->caps.num_qps;
365 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 366
5a0d0a61 367 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 368 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 369 size = dev->caps.num_srqs;
370 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 371
5a0d0a61 372 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 373 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 374 size = dev->caps.num_cqs;
375 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1 376
7ae0e400
MB		 377 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
378 mlx4_QUERY_FUNC(dev, &func, slave)) {
379 size = vhcr->in_modifier &
380 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
381 dev->caps.num_eqs :
382 rounddown_pow_of_two(dev->caps.num_eqs);
383 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
384 size = dev->caps.reserved_eqs;
385 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
386 } else {
387 size = vhcr->in_modifier &
388 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
389 func.max_eq :
390 rounddown_pow_of_two(func.max_eq);
391 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
392 size = func.rsvd_eqs;
393 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
394 }
5cc914f1 395
5a0d0a61 396 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 397 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 398 size = dev->caps.num_mpts;
399 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 400
5a0d0a61 401 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 402 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 403 size = dev->caps.num_mtts;
404 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 405
406 size = dev->caps.num_mgms + dev->caps.num_amgms;
407 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 408 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1 409
d57febe1
MB		 410 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG |
411 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG;
ddae0349 412 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
5cc914f1
MA		 413 } else
414 err = -EINVAL;
415
416 return err;
417}
418
225c6c8c 419int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
47605df9 420 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 421{
422 struct mlx4_cmd_mailbox *mailbox;
423 u32 *outbox;
47605df9 424 u8 field, op_modifier;
99ec41d0 425 u32 size, qkey;
eb456a68 426 int err = 0, quotas = 0;
7ae0e400 427 u32 in_modifier;
5cc914f1 428
47605df9 429 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
7ae0e400
MB		 430 in_modifier = op_modifier ? gen_or_port :
431 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS;
5cc914f1
MA		 432
433 mailbox = mlx4_alloc_cmd_mailbox(dev);
434 if (IS_ERR(mailbox))
435 return PTR_ERR(mailbox);
436
7ae0e400 437 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier,
47605df9 438 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 439 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
440 if (err)
441 goto out;
442
443 outbox = mailbox->buf;
444
47605df9
JM		 445 if (!op_modifier) {
446 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
447 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
448 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
449 err = -EPROTONOSUPPORT;
450 goto out;
451 }
452 func_cap->flags = field;
eb456a68 453 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 454
47605df9
JM		 455 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
456 func_cap->num_ports = field;
5cc914f1 457
47605df9
JM		 458 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
459 func_cap->pf_context_behaviour = size;
5cc914f1 460
eb456a68
JM		 461 if (quotas) {
462 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
463 func_cap->qp_quota = size & 0xFFFFFF;
464
465 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
466 func_cap->srq_quota = size & 0xFFFFFF;
467
468 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
469 func_cap->cq_quota = size & 0xFFFFFF;
470
471 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
472 func_cap->mpt_quota = size & 0xFFFFFF;
473
474 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
475 func_cap->mtt_quota = size & 0xFFFFFF;
476
477 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
478 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 479
eb456a68
JM		 480 } else {
481 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
482 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 483
eb456a68
JM		 484 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
485 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 486
eb456a68
JM		 487 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
488 func_cap->cq_quota = size & 0xFFFFFF;
489
490 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
491 func_cap->mpt_quota = size & 0xFFFFFF;
492
493 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
494 func_cap->mtt_quota = size & 0xFFFFFF;
495
496 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
497 func_cap->mcg_quota = size & 0xFFFFFF;
498 }
47605df9
JM		 499 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
500 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 501
47605df9
JM		 502 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
503 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 504
ddae0349
EE		 505 func_cap->extra_flags = 0;
506
507 /* Mailbox data from 0x6c and onward should only be treated if
508 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags
509 */
510 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) {
511 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
512 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG)
513 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP;
d57febe1
MB		 514 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG)
515 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP;
ddae0349
EE		 516 }
517
47605df9
JM		 518 goto out;
519 }
5cc914f1 520
47605df9
JM		 521 /* logical port query */
522 if (gen_or_port > dev->caps.num_ports) {
523 err = -EINVAL;
524 goto out;
525 }
5cc914f1 526
eb17711b 527 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
47605df9 528 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
bc82878b 529 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
47605df9
JM		 530 mlx4_err(dev, "VLAN is enforced on this port\n");
531 err = -EPROTONOSUPPORT;
5cc914f1 532 goto out;
47605df9 533 }
5cc914f1 534
eb17711b 535 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 536 mlx4_err(dev, "Force mac is enabled on this port\n");
537 err = -EPROTONOSUPPORT;
538 goto out;
5cc914f1 539 }
47605df9 540 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 541 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
542 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
1a91de28 543 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
47605df9
JM		 544 err = -EPROTONOSUPPORT;
545 goto out;
546 }
547 }
5cc914f1 548
47605df9
JM		 549 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
550 func_cap->physical_port = field;
551 if (func_cap->physical_port != gen_or_port) {
552 err = -ENOSYS;
553 goto out;
5cc914f1
MA		 554 }
555
99ec41d0
JM		 556 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
557 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
558 func_cap->qp0_qkey = qkey;
559 } else {
560 func_cap->qp0_qkey = 0;
561 }
562
47605df9
JM		 563 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
564 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
565
566 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
567 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
568
569 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
570 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
571
572 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
573 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
574
8e1a28e8
HHZ		 575 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
576 MLX4_GET(func_cap->phys_port_id, outbox,
577 QUERY_FUNC_CAP_PHYS_PORT_ID);
578
5cc914f1
MA		 579 /* All other resources are allocated by the master, but we still report
580 * 'num' and 'reserved' capabilities as follows:
581 * - num remains the maximum resource index
582 * - 'num - reserved' is the total available objects of a resource, but
583 * resource indices may be less than 'reserved'
584 * TODO: set per-resource quotas */
585
586out:
587 mlx4_free_cmd_mailbox(dev, mailbox);
588
589 return err;
590}
591
225c7b1f
RD		 592int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
593{
594 struct mlx4_cmd_mailbox *mailbox;
595 u32 *outbox;
596 u8 field;
ccf86321 597 u32 field32, flags, ext_flags;
225c7b1f
RD		 598 u16 size;
599 u16 stat_rate;
600 int err;
5ae2a7a8 601 int i;
225c7b1f
RD		 602
603#define QUERY_DEV_CAP_OUT_SIZE 0x100
604#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
605#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
606#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
607#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
608#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
609#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
610#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
611#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
612#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
613#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
614#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
615#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
616#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
617#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
618#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
619#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
620#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
621#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
7ae0e400 622#define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
225c7b1f
RD		 623#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
624#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
625#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 626#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 627#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 628#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
629#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
630#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
631#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
632#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 633#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 634#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
635#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 636#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 637#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 638#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 639#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
640#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
641#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
642#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
643#define QUERY_DEV_CAP_BF_OFFSET 0x4c
644#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
645#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
646#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
647#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
648#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
649#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
650#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
651#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
652#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
653#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
654#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
655#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 656#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
657#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 658#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
3f7fb021 659#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
4de65803 660#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
0ff1fb65
HHZ		 661#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
662#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
77507aa2 663#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
adbc7ac5 664#define QUERY_DEV_CAP_ETH_PROT_CTRL_OFFSET 0x7a
225c7b1f
RD		 665#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
666#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
667#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
668#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
669#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
670#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
671#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
672#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
673#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
674#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 675#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
d475c95b 676#define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
225c7b1f
RD		 677#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
678#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
a53e3e8c 679#define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
955154fa 680#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
7ffdf726 681#define QUERY_DEV_CAP_VXLAN 0x9e
114840c3 682#define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
225c7b1f 683
b3416f44 684 dev_cap->flags2 = 0;
225c7b1f
RD		 685 mailbox = mlx4_alloc_cmd_mailbox(dev);
686 if (IS_ERR(mailbox))
687 return PTR_ERR(mailbox);
688 outbox = mailbox->buf;
689
690 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 691 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 692 if (err)
693 goto out;
694
695 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
696 dev_cap->reserved_qps = 1 << (field & 0xf);
697 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
698 dev_cap->max_qps = 1 << (field & 0x1f);
699 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
700 dev_cap->reserved_srqs = 1 << (field >> 4);
701 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
702 dev_cap->max_srqs = 1 << (field & 0x1f);
703 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
704 dev_cap->max_cq_sz = 1 << field;
705 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
706 dev_cap->reserved_cqs = 1 << (field & 0xf);
707 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
708 dev_cap->max_cqs = 1 << (field & 0x1f);
709 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
710 dev_cap->max_mpts = 1 << (field & 0x3f);
711 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
7c68dd43 712 dev_cap->reserved_eqs = 1 << (field & 0xf);
225c7b1f 713 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 714 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 715 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
716 dev_cap->reserved_mtts = 1 << (field >> 4);
717 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
718 dev_cap->max_mrw_sz = 1 << field;
719 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
720 dev_cap->reserved_mrws = 1 << (field & 0xf);
721 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
722 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
7ae0e400
MB		 723 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
724 dev_cap->num_sys_eqs = size & 0xfff;
225c7b1f
RD		 725 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
726 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
727 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
728 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 729 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
730 field &= 0x1f;
731 if (!field)
732 dev_cap->max_gso_sz = 0;
733 else
734 dev_cap->max_gso_sz = 1 << field;
735
b3416f44
SP		 736 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
737 if (field & 0x20)
738 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
739 if (field & 0x10)
740 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
741 field &= 0xf;
742 if (field) {
743 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
744 dev_cap->max_rss_tbl_sz = 1 << field;
745 } else
746 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 747 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
748 dev_cap->max_rdma_global = 1 << (field & 0x3f);
749 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
750 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 751 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 752 dev_cap->num_ports = field & 0xf;
149983af
DB		 753 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
754 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 755 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
756 if (field & 0x80)
757 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
758 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
4de65803
MB		 759 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
760 if (field & 0x80)
761 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
0ff1fb65
HHZ		 762 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
763 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 764 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
765 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 766 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
767 if (field & 0x80)
768 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 769 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 770 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 771 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 772 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
773 dev_cap->reserved_uars = field >> 4;
774 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
775 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
776 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
777 dev_cap->min_page_sz = 1 << field;
778
779 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
780 if (field & 0x80) {
781 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
782 dev_cap->bf_reg_size = 1 << (field & 0x1f);
783 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 784 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 785 field = 3;
225c7b1f
RD		 786 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
787 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
788 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
789 } else {
790 dev_cap->bf_reg_size = 0;
791 mlx4_dbg(dev, "BlueFlame not available\n");
792 }
793
794 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
795 dev_cap->max_sq_sg = field;
796 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
797 dev_cap->max_sq_desc_sz = size;
798
799 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
800 dev_cap->max_qp_per_mcg = 1 << field;
801 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
802 dev_cap->reserved_mgms = field & 0xf;
803 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
804 dev_cap->max_mcgs = 1 << field;
805 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
806 dev_cap->reserved_pds = field >> 4;
807 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
808 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 809 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
810 dev_cap->reserved_xrcds = field >> 4;
426dd00d 811 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 812 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 813
814 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
815 dev_cap->rdmarc_entry_sz = size;
816 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
817 dev_cap->qpc_entry_sz = size;
818 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
819 dev_cap->aux_entry_sz = size;
820 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
821 dev_cap->altc_entry_sz = size;
822 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
823 dev_cap->eqc_entry_sz = size;
824 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
825 dev_cap->cqc_entry_sz = size;
826 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
827 dev_cap->srq_entry_sz = size;
828 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
829 dev_cap->cmpt_entry_sz = size;
830 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
831 dev_cap->mtt_entry_sz = size;
832 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
833 dev_cap->dmpt_entry_sz = size;
834
835 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
836 dev_cap->max_srq_sz = 1 << field;
837 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
838 dev_cap->max_qp_sz = 1 << field;
839 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
840 dev_cap->resize_srq = field & 1;
841 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
842 dev_cap->max_rq_sg = field;
843 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
844 dev_cap->max_rq_desc_sz = size;
77507aa2 845 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
adbc7ac5
SM		 846 if (field & (1 << 5))
847 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
77507aa2
IS		 848 if (field & (1 << 6))
849 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
850 if (field & (1 << 7))
851 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
225c7b1f
RD		 852 MLX4_GET(dev_cap->bmme_flags, outbox,
853 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
d475c95b
MB		 854 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
855 if (field & 0x20)
856 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
225c7b1f
RD		 857 MLX4_GET(dev_cap->reserved_lkey, outbox,
858 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
a53e3e8c
SM		 859 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
860 if (field32 & (1 << 0))
861 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
955154fa
MB		 862 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
863 if (field & 1<<6)
5930e8d0 864 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
7ffdf726
OG		 865 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
866 if (field & 1<<3)
867 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
225c7b1f
RD		 868 MLX4_GET(dev_cap->max_icm_sz, outbox,
869 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 870 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
871 MLX4_GET(dev_cap->max_counters, outbox,
872 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 873
114840c3
JM		 874 MLX4_GET(field32, outbox,
875 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
876 if (field32 & (1 << 0))
877 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
878
3f7fb021 879 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 880 if (field32 & (1 << 16))
881 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
3f7fb021
RE		 882 if (field32 & (1 << 26))
883 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 884 if (field32 & (1 << 20))
885 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
de966c59
MB		 886 if (field32 & (1 << 21))
887 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
3f7fb021 888
5ae2a7a8
RD		 889 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
890 for (i = 1; i <= dev_cap->num_ports; ++i) {
891 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
892 dev_cap->max_vl[i] = field >> 4;
893 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 894 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 895 dev_cap->max_port_width[i] = field & 0xf;
896 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
897 dev_cap->max_gids[i] = 1 << (field & 0xf);
898 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
899 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
900 }
901 } else {
7ff93f8b 902#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 903#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 904#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 905#define QUERY_PORT_WIDTH_OFFSET 0x06
906#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 907#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 908#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 909#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 910#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
911#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
912#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 913
914 for (i = 1; i <= dev_cap->num_ports; ++i) {
915 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 916 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 917 if (err)
918 goto out;
919
7ff93f8b
YP		 920 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
921 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 922 dev_cap->suggested_type[i] = (field >> 3) & 1;
923 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 924 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 925 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 926 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
927 dev_cap->max_port_width[i] = field & 0xf;
928 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
929 dev_cap->max_gids[i] = 1 << (field >> 4);
930 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
931 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
932 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 933 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
934 dev_cap->log_max_macs[i] = field & 0xf;
935 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 936 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
937 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 938 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
939 dev_cap->trans_type[i] = field32 >> 24;
940 dev_cap->vendor_oui[i] = field32 & 0xffffff;
941 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
942 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 943 }
944 }
945
95d04f07
RD		 946 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
947 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 948
949 /*
950 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
951 * we can't use any EQs whose doorbell falls on that page,
952 * even if the EQ itself isn't reserved.
953 */
7ae0e400
MB		 954 if (dev_cap->num_sys_eqs == 0)
955 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
956 dev_cap->reserved_eqs);
957 else
958 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
225c7b1f
RD		 959
960 mlx4_dbg(dev, "Max ICM size %lld MB\n",
961 (unsigned long long) dev_cap->max_icm_sz >> 20);
962 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
963 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
964 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
965 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
966 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
967 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
7ae0e400
MB		 968 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
969 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
970 dev_cap->eqc_entry_sz);
225c7b1f
RD		 971 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
972 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
973 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
974 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
975 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
976 dev_cap->max_pds, dev_cap->reserved_mgms);
977 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
978 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
979 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 980 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 981 dev_cap->max_port_width[1]);
225c7b1f
RD		 982 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
983 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
984 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
985 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 986 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 987 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 988 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 989
990 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 991 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 992
993out:
994 mlx4_free_cmd_mailbox(dev, mailbox);
995 return err;
996}
997
383677da
OG		 998#define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
999#define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
1000#define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
1001
b91cb3eb
JM		 1002int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1003 struct mlx4_vhcr *vhcr,
1004 struct mlx4_cmd_mailbox *inbox,
1005 struct mlx4_cmd_mailbox *outbox,
1006 struct mlx4_cmd_info *cmd)
1007{
2a4fae14 1008 u64 flags;
b91cb3eb
JM		 1009 int err = 0;
1010 u8 field;
383677da 1011 u32 bmme_flags, field32;
449fc488
MB		 1012 int real_port;
1013 int slave_port;
1014 int first_port;
1015 struct mlx4_active_ports actv_ports;
b91cb3eb
JM		 1016
1017 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1018 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1019 if (err)
1020 return err;
1021
cc1ade94
SM		 1022 /* add port mng change event capability and disable mw type 1
1023 * unconditionally to slaves
1024 */
2a4fae14
JM		 1025 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1026 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 1027 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
449fc488
MB		 1028 actv_ports = mlx4_get_active_ports(dev, slave);
1029 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
1030 for (slave_port = 0, real_port = first_port;
1031 real_port < first_port +
1032 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
1033 ++real_port, ++slave_port) {
1034 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
1035 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
1036 else
1037 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1038 }
1039 for (; slave_port < dev->caps.num_ports; ++slave_port)
1040 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
2a4fae14
JM		 1041 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1042
449fc488
MB		 1043 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1044 field &= ~0x0F;
1045 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1046 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1047
30b40c31
AV		 1048 /* For guests, disable timestamp */
1049 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1050 field &= 0x7f;
1051 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1052
7ffdf726 1053 /* For guests, disable vxlan tunneling */
57352ef4 1054 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
7ffdf726
OG		 1055 field &= 0xf7;
1056 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1057
b91cb3eb
JM		 1058 /* For guests, report Blueflame disabled */
1059 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1060 field &= 0x7f;
1061 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1062
cc1ade94 1063 /* For guests, disable mw type 2 */
57352ef4 1064 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
cc1ade94
SM		 1065 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
1066 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1067
0081c8f3
JM		 1068 /* turn off device-managed steering capability if not enabled */
1069 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1070 MLX4_GET(field, outbox->buf,
1071 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1072 field &= 0x7f;
1073 MLX4_PUT(outbox->buf, field,
1074 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1075 }
4de65803
MB		 1076
1077 /* turn off ipoib managed steering for guests */
57352ef4 1078 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
4de65803
MB		 1079 field &= ~0x80;
1080 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1081
383677da
OG		 1082 /* turn off host side virt features (VST, FSM, etc) for guests */
1083 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1084 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS |
1085 DEV_CAP_EXT_2_FLAG_FSM);
1086 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1087
b91cb3eb
JM		 1088 return 0;
1089}
1090
5cc914f1
MA		 1091int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1092 struct mlx4_vhcr *vhcr,
1093 struct mlx4_cmd_mailbox *inbox,
1094 struct mlx4_cmd_mailbox *outbox,
1095 struct mlx4_cmd_info *cmd)
1096{
0eb62b93 1097 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 1098 u64 def_mac;
1099 u8 port_type;
6634961c 1100 u16 short_field;
5cc914f1 1101 int err;
948e306d 1102 int admin_link_state;
449fc488
MB		 1103 int port = mlx4_slave_convert_port(dev, slave,
1104 vhcr->in_modifier & 0xFF);
5cc914f1 1105
105c320f 1106#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 1107#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 1108#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1109#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 1110
449fc488
MB		 1111 if (port < 0)
1112 return -EINVAL;
1113
a7401b9c
JM		 1114 /* Protect against untrusted guests: enforce that this is the
1115 * QUERY_PORT general query.
1116 */
1117 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
1118 return -EINVAL;
1119
1120 vhcr->in_modifier = port;
449fc488 1121
5cc914f1
MA		 1122 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1123 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1124 MLX4_CMD_NATIVE);
1125
1126 if (!err && dev->caps.function != slave) {
0508ad64 1127 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 1128 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1129
1130 /* get port type - currently only eth is enabled */
1131 MLX4_GET(port_type, outbox->buf,
1132 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1133
105c320f
JM		 1134 /* No link sensing allowed */
1135 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1136 /* set port type to currently operating port type */
1137 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 1138
948e306d
RE		 1139 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1140 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1141 port_type |= MLX4_PORT_LINK_UP_MASK;
1142 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1143 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1144
5cc914f1
MA		 1145 MLX4_PUT(outbox->buf, port_type,
1146 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c 1147
b6ffaeff 1148 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
449fc488 1149 short_field = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 1150 else
1151 short_field = 1; /* slave max gids */
6634961c
JM		 1152 MLX4_PUT(outbox->buf, short_field,
1153 QUERY_PORT_CUR_MAX_GID_OFFSET);
1154
1155 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1156 MLX4_PUT(outbox->buf, short_field,
1157 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 1158 }
1159
1160 return err;
1161}
1162
6634961c
JM		 1163int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1164 int *gid_tbl_len, int *pkey_tbl_len)
1165{
1166 struct mlx4_cmd_mailbox *mailbox;
1167 u32 *outbox;
1168 u16 field;
1169 int err;
1170
1171 mailbox = mlx4_alloc_cmd_mailbox(dev);
1172 if (IS_ERR(mailbox))
1173 return PTR_ERR(mailbox);
1174
1175 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1176 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1177 MLX4_CMD_WRAPPED);
1178 if (err)
1179 goto out;
1180
1181 outbox = mailbox->buf;
1182
1183 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1184 *gid_tbl_len = field;
1185
1186 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1187 *pkey_tbl_len = field;
1188
1189out:
1190 mlx4_free_cmd_mailbox(dev, mailbox);
1191 return err;
1192}
1193EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1194
225c7b1f
RD		 1195int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1196{
1197 struct mlx4_cmd_mailbox *mailbox;
1198 struct mlx4_icm_iter iter;
1199 __be64 *pages;
1200 int lg;
1201 int nent = 0;
1202 int i;
1203 int err = 0;
1204 int ts = 0, tc = 0;
1205
1206 mailbox = mlx4_alloc_cmd_mailbox(dev);
1207 if (IS_ERR(mailbox))
1208 return PTR_ERR(mailbox);
225c7b1f
RD		 1209 pages = mailbox->buf;
1210
1211 for (mlx4_icm_first(icm, &iter);
1212 !mlx4_icm_last(&iter);
1213 mlx4_icm_next(&iter)) {
1214 /*
1215 * We have to pass pages that are aligned to their
1216 * size, so find the least significant 1 in the
1217 * address or size and use that as our log2 size.
1218 */
1219 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1220 if (lg < MLX4_ICM_PAGE_SHIFT) {
1a91de28
JP		 1221 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1222 MLX4_ICM_PAGE_SIZE,
1223 (unsigned long long) mlx4_icm_addr(&iter),
1224 mlx4_icm_size(&iter));
225c7b1f
RD		 1225 err = -EINVAL;
1226 goto out;
1227 }
1228
1229 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1230 if (virt != -1) {
1231 pages[nent * 2] = cpu_to_be64(virt);
1232 virt += 1 << lg;
1233 }
1234
1235 pages[nent * 2 + 1] =
1236 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1237 (lg - MLX4_ICM_PAGE_SHIFT));
1238 ts += 1 << (lg - 10);
1239 ++tc;
1240
1241 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1242 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 1243 MLX4_CMD_TIME_CLASS_B,
1244 MLX4_CMD_NATIVE);
225c7b1f
RD		 1245 if (err)
1246 goto out;
1247 nent = 0;
1248 }
1249 }
1250 }
1251
1252 if (nent)
f9baff50
JM		 1253 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1254 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1255 if (err)
1256 goto out;
1257
1258 switch (op) {
1259 case MLX4_CMD_MAP_FA:
1a91de28 1260 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
225c7b1f
RD		 1261 break;
1262 case MLX4_CMD_MAP_ICM_AUX:
1a91de28 1263 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
225c7b1f
RD		 1264 break;
1265 case MLX4_CMD_MAP_ICM:
1a91de28
JP		 1266 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1267 tc, ts, (unsigned long long) virt - (ts << 10));
225c7b1f
RD		 1268 break;
1269 }
1270
1271out:
1272 mlx4_free_cmd_mailbox(dev, mailbox);
1273 return err;
1274}
1275
1276int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1277{
1278 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1279}
1280
1281int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1282{
f9baff50
JM		 1283 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1284 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1285}
1286
1287
1288int mlx4_RUN_FW(struct mlx4_dev *dev)
1289{
f9baff50
JM		 1290 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1291 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1292}
1293
1294int mlx4_QUERY_FW(struct mlx4_dev *dev)
1295{
1296 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1297 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1298 struct mlx4_cmd_mailbox *mailbox;
1299 u32 *outbox;
1300 int err = 0;
1301 u64 fw_ver;
fe40900f 1302 u16 cmd_if_rev;
225c7b1f
RD		 1303 u8 lg;
1304
1305#define QUERY_FW_OUT_SIZE 0x100
1306#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1307#define QUERY_FW_PPF_ID 0x09
fe40900f 1308#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1309#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1310#define QUERY_FW_ERR_START_OFFSET 0x30
1311#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1312#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1313
1314#define QUERY_FW_SIZE_OFFSET 0x00
1315#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1316#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1317
5cc914f1
MA		 1318#define QUERY_FW_COMM_BASE_OFFSET 0x40
1319#define QUERY_FW_COMM_BAR_OFFSET 0x48
1320
ddd8a6c1
EE		 1321#define QUERY_FW_CLOCK_OFFSET 0x50
1322#define QUERY_FW_CLOCK_BAR 0x58
1323
225c7b1f
RD		 1324 mailbox = mlx4_alloc_cmd_mailbox(dev);
1325 if (IS_ERR(mailbox))
1326 return PTR_ERR(mailbox);
1327 outbox = mailbox->buf;
1328
1329 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1330 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1331 if (err)
1332 goto out;
1333
1334 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1335 /*
3e1db334 1336 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1337 * version, so swap here.
1338 */
1339 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1340 ((fw_ver & 0xffff0000ull) >> 16) |
1341 ((fw_ver & 0x0000ffffull) << 16);
1342
752a50ca
JM		 1343 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1344 dev->caps.function = lg;
1345
b91cb3eb
JM		 1346 if (mlx4_is_slave(dev))
1347 goto out;
1348
5cc914f1 1349
fe40900f 1350 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1351 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1352 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1a91de28 1353 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
fe40900f
RD		 1354 cmd_if_rev);
1355 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1356 (int) (dev->caps.fw_ver >> 32),
1357 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1358 (int) dev->caps.fw_ver & 0xffff);
1a91de28 1359 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
5ae2a7a8 1360 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1361 err = -ENODEV;
1362 goto out;
1363 }
1364
5ae2a7a8
RD		 1365 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1366 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1367
225c7b1f
RD		 1368 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1369 cmd->max_cmds = 1 << lg;
1370
fe40900f 1371 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1372 (int) (dev->caps.fw_ver >> 32),
1373 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1374 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1375 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1376
1377 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1378 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1379 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1380 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1381
1382 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1383 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1384
1385 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1386 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1387 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1388 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1389
5cc914f1
MA		 1390 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1391 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1392 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1393 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1394 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1395 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1396
ddd8a6c1
EE		 1397 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1398 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1399 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1400 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1401 fw->clock_bar, fw->clock_offset);
1402
225c7b1f
RD		 1403 /*
1404 * Round up number of system pages needed in case
1405 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1406 */
1407 fw->fw_pages =
1408 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1409 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1410
1411 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1412 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1413
1414out:
1415 mlx4_free_cmd_mailbox(dev, mailbox);
1416 return err;
1417}
1418
b91cb3eb
JM		 1419int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1420 struct mlx4_vhcr *vhcr,
1421 struct mlx4_cmd_mailbox *inbox,
1422 struct mlx4_cmd_mailbox *outbox,
1423 struct mlx4_cmd_info *cmd)
1424{
1425 u8 *outbuf;
1426 int err;
1427
1428 outbuf = outbox->buf;
1429 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1430 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1431 if (err)
1432 return err;
1433
752a50ca
JM		 1434 /* for slaves, set pci PPF ID to invalid and zero out everything
1435 * else except FW version */
b91cb3eb
JM		 1436 outbuf[0] = outbuf[1] = 0;
1437 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1438 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1439
b91cb3eb
JM		 1440 return 0;
1441}
1442
225c7b1f
RD		 1443static void get_board_id(void *vsd, char *board_id)
1444{
1445 int i;
1446
1447#define VSD_OFFSET_SIG1 0x00
1448#define VSD_OFFSET_SIG2 0xde
1449#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1450#define VSD_OFFSET_TS_BOARD_ID 0x20
1451
1452#define VSD_SIGNATURE_TOPSPIN 0x5ad
1453
1454 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1455
1456 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1457 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1458 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1459 } else {
1460 /*
1461 * The board ID is a string but the firmware byte
1462 * swaps each 4-byte word before passing it back to
1463 * us. Therefore we need to swab it before printing.
1464 */
1465 for (i = 0; i < 4; ++i)
1466 ((u32 *) board_id)[i] =
1467 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1468 }
1469}
1470
1471int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1472{
1473 struct mlx4_cmd_mailbox *mailbox;
1474 u32 *outbox;
1475 int err;
1476
1477#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1478#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1479#define QUERY_ADAPTER_VSD_OFFSET 0x20
1480
1481 mailbox = mlx4_alloc_cmd_mailbox(dev);
1482 if (IS_ERR(mailbox))
1483 return PTR_ERR(mailbox);
1484 outbox = mailbox->buf;
1485
1486 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1487 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1488 if (err)
1489 goto out;
1490
225c7b1f
RD		 1491 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1492
1493 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1494 adapter->board_id);
1495
1496out:
1497 mlx4_free_cmd_mailbox(dev, mailbox);
1498 return err;
1499}
1500
1501int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1502{
1503 struct mlx4_cmd_mailbox *mailbox;
1504 __be32 *inbox;
1505 int err;
1506
1507#define INIT_HCA_IN_SIZE 0x200
1508#define INIT_HCA_VERSION_OFFSET 0x000
1509#define INIT_HCA_VERSION 2
7ffdf726 1510#define INIT_HCA_VXLAN_OFFSET 0x0c
c57e20dc 1511#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1512#define INIT_HCA_FLAGS_OFFSET 0x014
1513#define INIT_HCA_QPC_OFFSET 0x020
1514#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1515#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1516#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1517#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1518#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1519#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1520#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
77507aa2 1521#define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
225c7b1f
RD		 1522#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1523#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1524#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1525#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
7ae0e400 1526#define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
225c7b1f
RD		 1527#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1528#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1529#define INIT_HCA_MCAST_OFFSET 0x0c0
1530#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1531#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1532#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1533#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1534#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1535#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1536#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1537#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1538#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1539#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1540#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1541#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1542#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1543#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1544#define INIT_HCA_TPT_OFFSET 0x0f0
1545#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1546#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1547#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1548#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1549#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1550#define INIT_HCA_UAR_OFFSET 0x120
1551#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1552#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1553
1554 mailbox = mlx4_alloc_cmd_mailbox(dev);
1555 if (IS_ERR(mailbox))
1556 return PTR_ERR(mailbox);
1557 inbox = mailbox->buf;
1558
225c7b1f
RD		 1559 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1560
c57e20dc
EC		 1561 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1562 (ilog2(cache_line_size()) - 4) << 5;
1563
225c7b1f
RD		 1564#if defined(__LITTLE_ENDIAN)
1565 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1566#elif defined(__BIG_ENDIAN)
1567 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1568#else
1569#error Host endianness not defined
1570#endif
1571 /* Check port for UD address vector: */
1572 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1573
8ff095ec
EC		 1574 /* Enable IPoIB checksumming if we can: */
1575 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1576 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1577
51f5f0ee
JM		 1578 /* Enable QoS support if module parameter set */
1579 if (enable_qos)
1580 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1581
f2a3f6a3
OG		 1582 /* enable counters */
1583 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1584 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1585
08ff3235
OG		 1586 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1587 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1588 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1589 dev->caps.eqe_size = 64;
1590 dev->caps.eqe_factor = 1;
1591 } else {
1592 dev->caps.eqe_size = 32;
1593 dev->caps.eqe_factor = 0;
1594 }
1595
1596 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1597 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1598 dev->caps.cqe_size = 64;
77507aa2 1599 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1600 } else {
1601 dev->caps.cqe_size = 32;
1602 }
1603
77507aa2
IS		 1604 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1605 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1606 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1607 dev->caps.eqe_size = cache_line_size();
1608 dev->caps.cqe_size = cache_line_size();
1609 dev->caps.eqe_factor = 0;
1610 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1611 (ilog2(dev->caps.eqe_size) - 5)),
1612 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1613
1614 /* User still need to know to support CQE > 32B */
1615 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1616 }
1617
225c7b1f
RD		 1618 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1619
1620 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1621 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1622 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1623 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1624 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1625 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1626 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1627 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1628 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1629 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1630 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
225c7b1f
RD		 1631 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1632 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1633
0ff1fb65
HHZ		 1634 /* steering attributes */
1635 if (dev->caps.steering_mode ==
1636 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1637 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1638 cpu_to_be32(1 <<
1639 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1640
1641 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1642 MLX4_PUT(inbox, param->log_mc_entry_sz,
1643 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1644 MLX4_PUT(inbox, param->log_mc_table_sz,
1645 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1646 /* Enable Ethernet flow steering
1647 * with udp unicast and tcp unicast
1648 */
23537b73 1649 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1650 INIT_HCA_FS_ETH_BITS_OFFSET);
1651 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1652 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1653 /* Enable IPoIB flow steering
1654 * with udp unicast and tcp unicast
1655 */
23537b73 1656 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1657 INIT_HCA_FS_IB_BITS_OFFSET);
1658 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1659 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1660 } else {
1661 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1662 MLX4_PUT(inbox, param->log_mc_entry_sz,
1663 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1664 MLX4_PUT(inbox, param->log_mc_hash_sz,
1665 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1666 MLX4_PUT(inbox, param->log_mc_table_sz,
1667 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1668 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1669 MLX4_PUT(inbox, (u8) (1 << 3),
1670 INIT_HCA_UC_STEERING_OFFSET);
1671 }
225c7b1f
RD		 1672
1673 /* TPT attributes */
1674
1675 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1676 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1677 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1678 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1679 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1680
1681 /* UAR attributes */
1682
ab9c17a0 1683 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1684 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1685
7ffdf726
OG		 1686 /* set parser VXLAN attributes */
1687 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1688 u8 parser_params = 0;
1689 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1690 }
1691
f9baff50
JM		 1692 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1693 MLX4_CMD_NATIVE);
225c7b1f
RD		 1694
1695 if (err)
1696 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1697
1698 mlx4_free_cmd_mailbox(dev, mailbox);
1699 return err;
1700}
1701
ab9c17a0
JM		 1702int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1703 struct mlx4_init_hca_param *param)
1704{
1705 struct mlx4_cmd_mailbox *mailbox;
1706 __be32 *outbox;
7b8157be 1707 u32 dword_field;
ab9c17a0 1708 int err;
08ff3235 1709 u8 byte_field;
ab9c17a0
JM		 1710
1711#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1712#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1713
1714 mailbox = mlx4_alloc_cmd_mailbox(dev);
1715 if (IS_ERR(mailbox))
1716 return PTR_ERR(mailbox);
1717 outbox = mailbox->buf;
1718
1719 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1720 MLX4_CMD_QUERY_HCA,
1721 MLX4_CMD_TIME_CLASS_B,
1722 !mlx4_is_slave(dev));
1723 if (err)
1724 goto out;
1725
1726 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1727 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1728
1729 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1730
1731 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1732 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1733 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1734 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1735 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1736 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1737 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1738 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1739 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1740 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1741 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
ab9c17a0
JM		 1742 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1743 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1744
7b8157be
JM		 1745 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1746 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1747 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1748 } else {
1749 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1750 if (byte_field & 0x8)
1751 param->steering_mode = MLX4_STEERING_MODE_B0;
1752 else
1753 param->steering_mode = MLX4_STEERING_MODE_A0;
1754 }
0ff1fb65 1755 /* steering attributes */
7b8157be 1756 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1757 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1758 MLX4_GET(param->log_mc_entry_sz, outbox,
1759 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1760 MLX4_GET(param->log_mc_table_sz, outbox,
1761 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1762 } else {
1763 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1764 MLX4_GET(param->log_mc_entry_sz, outbox,
1765 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1766 MLX4_GET(param->log_mc_hash_sz, outbox,
1767 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1768 MLX4_GET(param->log_mc_table_sz, outbox,
1769 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1770 }
ab9c17a0 1771
08ff3235
OG		 1772 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1773 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1774 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1775 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1776 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1777 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1778
77507aa2
IS		 1779 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1780 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1781 if (byte_field) {
1782 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1783 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1784 param->cqe_size = 1 << ((byte_field &
1785 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
1786 param->eqe_size = 1 << (((byte_field &
1787 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
1788 }
1789
ab9c17a0
JM		 1790 /* TPT attributes */
1791
1792 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1793 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1794 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1795 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1796 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1797
1798 /* UAR attributes */
1799
1800 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1801 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1802
1803out:
1804 mlx4_free_cmd_mailbox(dev, mailbox);
1805
1806 return err;
1807}
1808
980e9001
JM		 1809/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1810 * and real QP0 are active, so that the paravirtualized QP0 is ready
1811 * to operate */
1812static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1813{
1814 struct mlx4_priv *priv = mlx4_priv(dev);
1815 /* irrelevant if not infiniband */
1816 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1817 priv->mfunc.master.qp0_state[port].qp0_active)
1818 return 1;
1819 return 0;
1820}
1821
5cc914f1
MA		 1822int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1823 struct mlx4_vhcr *vhcr,
1824 struct mlx4_cmd_mailbox *inbox,
1825 struct mlx4_cmd_mailbox *outbox,
1826 struct mlx4_cmd_info *cmd)
1827{
1828 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1829 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1830 int err;
1831
449fc488
MB		 1832 if (port < 0)
1833 return -EINVAL;
1834
5cc914f1
MA		 1835 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1836 return 0;
1837
980e9001
JM		 1838 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1839 /* Enable port only if it was previously disabled */
1840 if (!priv->mfunc.master.init_port_ref[port]) {
1841 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1842 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1843 if (err)
1844 return err;
1845 }
1846 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1847 } else {
1848 if (slave == mlx4_master_func_num(dev)) {
1849 if (check_qp0_state(dev, slave, port) &&
1850 !priv->mfunc.master.qp0_state[port].port_active) {
1851 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1852 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1853 if (err)
1854 return err;
1855 priv->mfunc.master.qp0_state[port].port_active = 1;
1856 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1857 }
1858 } else
1859 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1860 }
1861 ++priv->mfunc.master.init_port_ref[port];
1862 return 0;
1863}
1864
5ae2a7a8 1865int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1866{
1867 struct mlx4_cmd_mailbox *mailbox;
1868 u32 *inbox;
1869 int err;
1870 u32 flags;
5ae2a7a8 1871 u16 field;
225c7b1f 1872
5ae2a7a8 1873 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1874#define INIT_PORT_IN_SIZE 256
1875#define INIT_PORT_FLAGS_OFFSET 0x00
1876#define INIT_PORT_FLAG_SIG (1 << 18)
1877#define INIT_PORT_FLAG_NG (1 << 17)
1878#define INIT_PORT_FLAG_G0 (1 << 16)
1879#define INIT_PORT_VL_SHIFT 4
1880#define INIT_PORT_PORT_WIDTH_SHIFT 8
1881#define INIT_PORT_MTU_OFFSET 0x04
1882#define INIT_PORT_MAX_GID_OFFSET 0x06
1883#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1884#define INIT_PORT_GUID0_OFFSET 0x10
1885#define INIT_PORT_NODE_GUID_OFFSET 0x18
1886#define INIT_PORT_SI_GUID_OFFSET 0x20
1887
5ae2a7a8
RD		 1888 mailbox = mlx4_alloc_cmd_mailbox(dev);
1889 if (IS_ERR(mailbox))
1890 return PTR_ERR(mailbox);
1891 inbox = mailbox->buf;
225c7b1f 1892
5ae2a7a8
RD		 1893 flags = 0;
1894 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1895 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1896 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1897
b79acb49 1898 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1899 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1900 field = dev->caps.gid_table_len[port];
1901 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1902 field = dev->caps.pkey_table_len[port];
1903 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1904
5ae2a7a8 1905 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1906 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1907
5ae2a7a8
RD		 1908 mlx4_free_cmd_mailbox(dev, mailbox);
1909 } else
1910 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1911 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1912
1913 return err;
1914}
1915EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1916
5cc914f1
MA		 1917int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1918 struct mlx4_vhcr *vhcr,
1919 struct mlx4_cmd_mailbox *inbox,
1920 struct mlx4_cmd_mailbox *outbox,
1921 struct mlx4_cmd_info *cmd)
1922{
1923 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1924 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1925 int err;
1926
449fc488
MB		 1927 if (port < 0)
1928 return -EINVAL;
1929
5cc914f1
MA		 1930 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1931 (1 << port)))
1932 return 0;
1933
980e9001
JM		 1934 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1935 if (priv->mfunc.master.init_port_ref[port] == 1) {
1936 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1937 1000, MLX4_CMD_NATIVE);
1938 if (err)
1939 return err;
1940 }
1941 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1942 } else {
1943 /* infiniband port */
1944 if (slave == mlx4_master_func_num(dev)) {
1945 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1946 priv->mfunc.master.qp0_state[port].port_active) {
1947 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1948 1000, MLX4_CMD_NATIVE);
1949 if (err)
1950 return err;
1951 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1952 priv->mfunc.master.qp0_state[port].port_active = 0;
1953 }
1954 } else
1955 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1956 }
5cc914f1
MA		 1957 --priv->mfunc.master.init_port_ref[port];
1958 return 0;
1959}
1960
225c7b1f
RD		 1961int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1962{
f9baff50
JM		 1963 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1964 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1965}
1966EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1967
1968int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1969{
f9baff50
JM		 1970 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1971 MLX4_CMD_NATIVE);
225c7b1f
RD		 1972}
1973
d18f141a
OG		 1974struct mlx4_config_dev {
1975 __be32 update_flags;
d475c95b 1976 __be32 rsvd1[3];
d18f141a
OG		 1977 __be16 vxlan_udp_dport;
1978 __be16 rsvd2;
d475c95b
MB		 1979 __be32 rsvd3[27];
1980 __be16 rsvd4;
1981 u8 rsvd5;
1982 u8 rx_checksum_val;
d18f141a
OG		 1983};
1984
1985#define MLX4_VXLAN_UDP_DPORT (1 << 0)
1986
d475c95b 1987static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
d18f141a
OG		 1988{
1989 int err;
1990 struct mlx4_cmd_mailbox *mailbox;
1991
1992 mailbox = mlx4_alloc_cmd_mailbox(dev);
1993 if (IS_ERR(mailbox))
1994 return PTR_ERR(mailbox);
1995
1996 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
1997
1998 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
1999 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2000
2001 mlx4_free_cmd_mailbox(dev, mailbox);
2002 return err;
2003}
2004
d475c95b
MB		 2005static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2006{
2007 int err;
2008 struct mlx4_cmd_mailbox *mailbox;
2009
2010 mailbox = mlx4_alloc_cmd_mailbox(dev);
2011 if (IS_ERR(mailbox))
2012 return PTR_ERR(mailbox);
2013
2014 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV,
2015 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2016
2017 if (!err)
2018 memcpy(config_dev, mailbox->buf, sizeof(*config_dev));
2019
2020 mlx4_free_cmd_mailbox(dev, mailbox);
2021 return err;
2022}
2023
2024/* Conversion between the HW values and the actual functionality.
2025 * The value represented by the array index,
2026 * and the functionality determined by the flags.
2027 */
2028static const u8 config_dev_csum_flags[] = {
2029 [0] = 0,
2030 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP,
2031 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP |
2032 MLX4_RX_CSUM_MODE_L4,
2033 [3] = MLX4_RX_CSUM_MODE_L4 |
2034 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP |
2035 MLX4_RX_CSUM_MODE_MULTI_VLAN
2036};
2037
2038int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
2039 struct mlx4_config_dev_params *params)
2040{
2041 struct mlx4_config_dev config_dev;
2042 int err;
2043 u8 csum_mask;
2044
2045#define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2046#define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2047#define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2048
2049 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2050 return -ENOTSUPP;
2051
2052 err = mlx4_CONFIG_DEV_get(dev, &config_dev);
2053 if (err)
2054 return err;
2055
2056 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) &
2057 CONFIG_DEV_RX_CSUM_MODE_MASK;
2058
2059 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2060 return -EINVAL;
2061 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask];
2062
2063 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) &
2064 CONFIG_DEV_RX_CSUM_MODE_MASK;
2065
2066 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2067 return -EINVAL;
2068 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask];
2069
2070 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport);
2071
2072 return 0;
2073}
2074EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval);
2075
d18f141a
OG		 2076int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
2077{
2078 struct mlx4_config_dev config_dev;
2079
2080 memset(&config_dev, 0, sizeof(config_dev));
2081 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
2082 config_dev.vxlan_udp_dport = udp_port;
2083
d475c95b 2084 return mlx4_CONFIG_DEV_set(dev, &config_dev);
d18f141a
OG		 2085}
2086EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
2087
2088
225c7b1f
RD		 2089int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
2090{
2091 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
2092 MLX4_CMD_SET_ICM_SIZE,
f9baff50 2093 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 2094 if (ret)
2095 return ret;
2096
2097 /*
2098 * Round up number of system pages needed in case
2099 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2100 */
2101 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
2102 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
2103
2104 return 0;
2105}
2106
2107int mlx4_NOP(struct mlx4_dev *dev)
2108{
2109 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 2110 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 2111}
14c07b13 2112
8e1a28e8
HHZ		 2113int mlx4_get_phys_port_id(struct mlx4_dev *dev)
2114{
2115 u8 port;
2116 u32 *outbox;
2117 struct mlx4_cmd_mailbox *mailbox;
2118 u32 in_mod;
2119 u32 guid_hi, guid_lo;
2120 int err, ret = 0;
2121#define MOD_STAT_CFG_PORT_OFFSET 8
2122#define MOD_STAT_CFG_GUID_H 0X14
2123#define MOD_STAT_CFG_GUID_L 0X1c
2124
2125 mailbox = mlx4_alloc_cmd_mailbox(dev);
2126 if (IS_ERR(mailbox))
2127 return PTR_ERR(mailbox);
2128 outbox = mailbox->buf;
2129
2130 for (port = 1; port <= dev->caps.num_ports; port++) {
2131 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
2132 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
2133 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2134 MLX4_CMD_NATIVE);
2135 if (err) {
2136 mlx4_err(dev, "Fail to get port %d uplink guid\n",
2137 port);
2138 ret = err;
2139 } else {
2140 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2141 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2142 dev->caps.phys_port_id[port] = (u64)guid_lo |
2143 (u64)guid_hi << 32;
2144 }
2145 }
2146 mlx4_free_cmd_mailbox(dev, mailbox);
2147 return ret;
2148}
2149
14c07b13
YP		 2150#define MLX4_WOL_SETUP_MODE (5 << 28)
2151int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
2152{
2153 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2154
2155 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 2156 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2157 MLX4_CMD_NATIVE);
14c07b13
YP		 2158}
2159EXPORT_SYMBOL_GPL(mlx4_wol_read);
2160
2161int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
2162{
2163 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2164
2165 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 2166 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 2167}
2168EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 2169
2170enum {
2171 ADD_TO_MCG = 0x26,
2172};
2173
2174
2175void mlx4_opreq_action(struct work_struct *work)
2176{
2177 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
2178 opreq_task);
2179 struct mlx4_dev *dev = &priv->dev;
2180 int num_tasks = atomic_read(&priv->opreq_count);
2181 struct mlx4_cmd_mailbox *mailbox;
2182 struct mlx4_mgm *mgm;
2183 u32 *outbox;
2184 u32 modifier;
2185 u16 token;
fe6f700d
YP		 2186 u16 type;
2187 int err;
2188 u32 num_qps;
2189 struct mlx4_qp qp;
2190 int i;
2191 u8 rem_mcg;
2192 u8 prot;
2193
2194#define GET_OP_REQ_MODIFIER_OFFSET 0x08
2195#define GET_OP_REQ_TOKEN_OFFSET 0x14
2196#define GET_OP_REQ_TYPE_OFFSET 0x1a
2197#define GET_OP_REQ_DATA_OFFSET 0x20
2198
2199 mailbox = mlx4_alloc_cmd_mailbox(dev);
2200 if (IS_ERR(mailbox)) {
2201 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2202 return;
2203 }
2204 outbox = mailbox->buf;
2205
2206 while (num_tasks) {
2207 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2208 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2209 MLX4_CMD_NATIVE);
2210 if (err) {
6d3be300 2211 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 2212 err);
2213 return;
2214 }
2215 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2216 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2217 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 2218 type &= 0xfff;
2219
2220 switch (type) {
2221 case ADD_TO_MCG:
2222 if (dev->caps.steering_mode ==
2223 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2224 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2225 err = EPERM;
2226 break;
2227 }
2228 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2229 GET_OP_REQ_DATA_OFFSET);
2230 num_qps = be32_to_cpu(mgm->members_count) &
2231 MGM_QPN_MASK;
2232 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2233 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2234
2235 for (i = 0; i < num_qps; i++) {
2236 qp.qpn = be32_to_cpu(mgm->qp[i]);
2237 if (rem_mcg)
2238 err = mlx4_multicast_detach(dev, &qp,
2239 mgm->gid,
2240 prot, 0);
2241 else
2242 err = mlx4_multicast_attach(dev, &qp,
2243 mgm->gid,
2244 mgm->gid[5]
2245 , 0, prot,
2246 NULL);
2247 if (err)
2248 break;
2249 }
2250 break;
2251 default:
2252 mlx4_warn(dev, "Bad type for required operation\n");
2253 err = EINVAL;
2254 break;
2255 }
28d222bb
EP		 2256 err = mlx4_cmd(dev, 0, ((u32) err |
2257 (__force u32)cpu_to_be32(token) << 16),
fe6f700d
YP		 2258 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2259 MLX4_CMD_NATIVE);
2260 if (err) {
2261 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2262 err);
2263 goto out;
2264 }
2265 memset(outbox, 0, 0xffc);
2266 num_tasks = atomic_dec_return(&priv->opreq_count);
2267 }
2268
2269out:
2270 mlx4_free_cmd_mailbox(dev, mailbox);
2271}
114840c3
JM		 2272
2273static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2274 struct mlx4_cmd_mailbox *mailbox)
2275{
2276#define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2277#define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2278#define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2279#define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2280
2281 u32 set_attr_mask, getresp_attr_mask;
2282 u32 trap_attr_mask, traprepress_attr_mask;
2283
2284 MLX4_GET(set_attr_mask, mailbox->buf,
2285 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2286 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2287 set_attr_mask);
2288
2289 MLX4_GET(getresp_attr_mask, mailbox->buf,
2290 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2291 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2292 getresp_attr_mask);
2293
2294 MLX4_GET(trap_attr_mask, mailbox->buf,
2295 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2296 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2297 trap_attr_mask);
2298
2299 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2300 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2301 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2302 traprepress_attr_mask);
2303
2304 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2305 traprepress_attr_mask)
2306 return 1;
2307
2308 return 0;
2309}
2310
2311int mlx4_config_mad_demux(struct mlx4_dev *dev)
2312{
2313 struct mlx4_cmd_mailbox *mailbox;
2314 int secure_host_active;
2315 int err;
2316
2317 /* Check if mad_demux is supported */
2318 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2319 return 0;
2320
2321 mailbox = mlx4_alloc_cmd_mailbox(dev);
2322 if (IS_ERR(mailbox)) {
2323 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2324 return -ENOMEM;
2325 }
2326
2327 /* Query mad_demux to find out which MADs are handled by internal sma */
2328 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2329 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2330 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2331 if (err) {
2332 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2333 err);
2334 goto out;
2335 }
2336
2337 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2338
2339 /* Config mad_demux to handle all MADs returned by the query above */
2340 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2341 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2342 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2343 if (err) {
2344 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2345 goto out;
2346 }
2347
2348 if (secure_host_active)
2349 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2350out:
2351 mlx4_free_cmd_mailbox(dev, mailbox);
2352 return err;
2353}
adbc7ac5
SM		 2354
2355/* Access Reg commands */
2356enum mlx4_access_reg_masks {
2357 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2358 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2359 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2360};
2361
2362struct mlx4_access_reg {
2363 __be16 constant1;
2364 u8 status;
2365 u8 resrvd1;
2366 __be16 reg_id;
2367 u8 method;
2368 u8 constant2;
2369 __be32 resrvd2[2];
2370 __be16 len_const;
2371 __be16 resrvd3;
2372#define MLX4_ACCESS_REG_HEADER_SIZE (20)
2373 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2374} __attribute__((__packed__));
2375
2376/**
2377 * mlx4_ACCESS_REG - Generic access reg command.
2378 * @dev: mlx4_dev.
2379 * @reg_id: register ID to access.
2380 * @method: Access method Read/Write.
2381 * @reg_len: register length to Read/Write in bytes.
2382 * @reg_data: reg_data pointer to Read/Write From/To.
2383 *
2384 * Access ConnectX registers FW command.
2385 * Returns 0 on success and copies outbox mlx4_access_reg data
2386 * field into reg_data or a negative error code.
2387 */
2388static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2389 enum mlx4_access_reg_method method,
2390 u16 reg_len, void *reg_data)
2391{
2392 struct mlx4_cmd_mailbox *inbox, *outbox;
2393 struct mlx4_access_reg *inbuf, *outbuf;
2394 int err;
2395
2396 inbox = mlx4_alloc_cmd_mailbox(dev);
2397 if (IS_ERR(inbox))
2398 return PTR_ERR(inbox);
2399
2400 outbox = mlx4_alloc_cmd_mailbox(dev);
2401 if (IS_ERR(outbox)) {
2402 mlx4_free_cmd_mailbox(dev, inbox);
2403 return PTR_ERR(outbox);
2404 }
2405
2406 inbuf = inbox->buf;
2407 outbuf = outbox->buf;
2408
2409 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2410 inbuf->constant2 = 0x1;
2411 inbuf->reg_id = cpu_to_be16(reg_id);
2412 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2413
2414 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2415 inbuf->len_const =
2416 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2417 ((0x3) << 12));
2418
2419 memcpy(inbuf->reg_data, reg_data, reg_len);
2420 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2421 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
6e806699 2422 MLX4_CMD_WRAPPED);
adbc7ac5
SM		 2423 if (err)
2424 goto out;
2425
2426 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2427 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2428 mlx4_err(dev,
2429 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2430 reg_id, err);
2431 goto out;
2432 }
2433
2434 memcpy(reg_data, outbuf->reg_data, reg_len);
2435out:
2436 mlx4_free_cmd_mailbox(dev, inbox);
2437 mlx4_free_cmd_mailbox(dev, outbox);
2438 return err;
2439}
2440
2441/* ConnectX registers IDs */
2442enum mlx4_reg_id {
2443 MLX4_REG_ID_PTYS = 0x5004,
2444};
2445
2446/**
2447 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2448 * register
2449 * @dev: mlx4_dev.
2450 * @method: Access method Read/Write.
2451 * @ptys_reg: PTYS register data pointer.
2452 *
2453 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2454 * configuration
2455 * Returns 0 on success or a negative error code.
2456 */
2457int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2458 enum mlx4_access_reg_method method,
2459 struct mlx4_ptys_reg *ptys_reg)
2460{
2461 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2462 method, sizeof(*ptys_reg), ptys_reg);
2463}
2464EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
6e806699
SM		 2465
2466int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2467 struct mlx4_vhcr *vhcr,
2468 struct mlx4_cmd_mailbox *inbox,
2469 struct mlx4_cmd_mailbox *outbox,
2470 struct mlx4_cmd_info *cmd)
2471{
2472 struct mlx4_access_reg *inbuf = inbox->buf;
2473 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2474 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2475
2476 if (slave != mlx4_master_func_num(dev) &&
2477 method == MLX4_ACCESS_REG_WRITE)
2478 return -EPERM;
2479
2480 if (reg_id == MLX4_REG_ID_PTYS) {
2481 struct mlx4_ptys_reg *ptys_reg =
2482 (struct mlx4_ptys_reg *)inbuf->reg_data;
2483
2484 ptys_reg->local_port =
2485 mlx4_slave_convert_port(dev, slave,
2486 ptys_reg->local_port);
2487 }
2488
2489 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2490 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2491 MLX4_CMD_NATIVE);
2492}
Linux 6.x block layer and io_uring tree(s)