net/mlx4: Cache line CQE/EQE stride fixes
authorIdo Shamay <idos@mellanox.com>
Tue, 16 Dec 2014 11:28:54 +0000 (13:28 +0200)
committerDavid S. Miller <davem@davemloft.net>
Tue, 16 Dec 2014 20:23:53 +0000 (15:23 -0500)
commitc3f2511feac088030055012cc8f64ebd84c87dbc
treed0050aaf6f9f5a2571abd772115ff7cd10ccbfb6
parent94191fd6718c6ae000afdad2ade5c473d1439c57
net/mlx4: Cache line CQE/EQE stride fixes

This commit contains 2 fixes for the 128B CQE/EQE stride feaure.
Wei found that mlx4_QUERY_HCA function marked the wrong capability
in flags (64B CQE/EQE), when CQE/EQE stride feature was enabled.
Also added small fix in initial CQE ownership bit assignment, when CQE
is size is not default 32B.

Fixes: 77507aa24 (net/mlx4: Enable CQE/EQE stride support)
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Signed-off-by: Ido Shamay <idos@mellanox.com>
Signed-off-by: Amir Vadai <amirv@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mellanox/mlx4/en_netdev.c
drivers/net/ethernet/mellanox/mlx4/fw.c