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powerpc: Disable DAWR on POWER9 via CPU feature quirk
[linux-2.6-block.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
10b35d99
KG		 2#ifndef __ASM_POWERPC_CPUTABLE_H
3#define __ASM_POWERPC_CPUTABLE_H
4
d1cdcf22 5
6574ba95 6#include <linux/types.h>
d1cdcf22 7#include <asm/asm-compat.h>
c5157e58 8#include <asm/feature-fixups.h>
c3617f72 9#include <uapi/asm/cputable.h>
d1cdcf22 10
10b35d99
KG		 11#ifndef __ASSEMBLY__
12
13/* This structure can grow, it's real size is used by head.S code
14 * via the mkdefs mechanism.
15 */
16struct cpu_spec;
10b35d99 17
10b35d99 18typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 19typedef void (*cpu_restore_t)(void);
10b35d99 20
32a33994 21enum powerpc_oprofile_type {
7a45fb19
AW		 22 PPC_OPROFILE_INVALID = 0,
23 PPC_OPROFILE_RS64 = 1,
24 PPC_OPROFILE_POWER4 = 2,
25 PPC_OPROFILE_G4 = 3,
39aef685 26 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 27 PPC_OPROFILE_CELL = 5,
25fc530e 28 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 29};
30
1bd2e5ae
OJ		 31enum powerpc_pmc_type {
32 PPC_PMC_DEFAULT = 0,
33 PPC_PMC_IBM = 1,
34 PPC_PMC_PA6T = 2,
b950bdd0 35 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 36};
37
47c0bd1a
BH		 38struct pt_regs;
39
40extern int machine_check_generic(struct pt_regs *regs);
41extern int machine_check_4xx(struct pt_regs *regs);
42extern int machine_check_440A(struct pt_regs *regs);
fe04b112 43extern int machine_check_e500mc(struct pt_regs *regs);
47c0bd1a
BH		 44extern int machine_check_e500(struct pt_regs *regs);
45extern int machine_check_e200(struct pt_regs *regs);
fc5e7097 46extern int machine_check_47x(struct pt_regs *regs);
e627f8dc 47int machine_check_8xx(struct pt_regs *regs);
47c0bd1a 48
e7affb1d 49extern void cpu_down_flush_e500v2(void);
50extern void cpu_down_flush_e500mc(void);
51extern void cpu_down_flush_e5500(void);
52extern void cpu_down_flush_e6500(void);
53
87a72f9e 54/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 55struct cpu_spec {
56 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
57 unsigned int pvr_mask;
58 unsigned int pvr_value;
59
60 char *cpu_name;
61 unsigned long cpu_features; /* Kernel features */
62 unsigned int cpu_user_features; /* Userland features */
2171364d 63 unsigned int cpu_user_features2; /* Userland features v2 */
7c03d653 64 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 65
66 /* cache line sizes */
67 unsigned int icache_bsize;
68 unsigned int dcache_bsize;
69
e7affb1d 70 /* flush caches inside the current cpu */
71 void (*cpu_down_flush)(void);
72
10b35d99
KG		 73 /* number of performance monitor counters */
74 unsigned int num_pmcs;
1bd2e5ae 75 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 76
77 /* this is called to initialize various CPU bits like L1 cache,
78 * BHT, SPD, etc... from head.S before branching to identify_machine
79 */
80 cpu_setup_t cpu_setup;
f39b7a55
OJ		 81 /* Used to restore cpu setup on secondary processors and at resume */
82 cpu_restore_t cpu_restore;
10b35d99
KG		 83
84 /* Used by oprofile userspace to select the right counters */
85 char *oprofile_cpu_type;
86
87 /* Processor specific oprofile operations */
32a33994 88 enum powerpc_oprofile_type oprofile_type;
80f15dc7 89
e78dbc80
MN		 90 /* Bit locations inside the mmcra change */
91 unsigned long oprofile_mmcra_sihv;
92 unsigned long oprofile_mmcra_sipr;
93
94 /* Bits to clear during an oprofile exception */
95 unsigned long oprofile_mmcra_clear;
96
80f15dc7
PM		 97 /* Name of processor class, for the ELF AT_PLATFORM entry */
98 char *platform;
47c0bd1a
BH		 99
100 /* Processor specific machine check handling. Return negative
101 * if the error is fatal, 1 if it was fully recovered and 0 to
102 * pass up (not CPU originated) */
103 int (*machine_check)(struct pt_regs *regs);
4c703416
MS		 104
105 /*
106 * Processor specific early machine check handler which is
107 * called in real mode to handle SLB and TLB errors.
108 */
109 long (*machine_check_early)(struct pt_regs *regs);
10b35d99
KG		 110};
111
10b35d99 112extern struct cpu_spec *cur_cpu_spec;
10b35d99 113
42c4aaad
BH		 114extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
115
5a61ef74 116extern void set_cur_cpu_spec(struct cpu_spec *s);
974a76f5 117extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
5a61ef74 118extern void identify_cpu_name(unsigned int pvr);
0909c8c2
BH		 119extern void do_feature_fixups(unsigned long value, void *fixup_start,
120 void *fixup_end);
9b6b563c 121
9115d134
NL		 122extern const char *powerpc_base_platform;
123
4db73271
KH		 124#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
125extern void cpu_feature_keys_init(void);
126#else
127static inline void cpu_feature_keys_init(void) { }
128#endif
129
10b35d99
KG		 130#endif /* __ASSEMBLY__ */
131
132/* CPU kernel features */
133
9bbf0b57 134/* Definitions for features that we have on both 32-bit and 64-bit chips */
cde4d494 135#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
9bbf0b57
PM		 136#define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
137#define CPU_FTR_DBELL ASM_CONST(0x00000004)
138#define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
139#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
140#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00000020)
141#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
142#define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
143#define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
144#define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
145
146/* Definitions for features that only exist on 32-bit chips */
147#ifdef CONFIG_PPC32
148#define CPU_FTR_601 ASM_CONST(0x00001000)
149#define CPU_FTR_L2CR ASM_CONST(0x00002000)
150#define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
151#define CPU_FTR_TAU ASM_CONST(0x00008000)
152#define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
153#define CPU_FTR_USE_RTC ASM_CONST(0x00020000)
154#define CPU_FTR_L3CR ASM_CONST(0x00040000)
155#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
156#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
157#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
158#define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
159#define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
160#define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
161#define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
162#define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
163#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x08000000)
164#define CPU_FTR_SPE ASM_CONST(0x10000000)
165#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
166#define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
167
168#else /* CONFIG_PPC32 */
169/* Define these to 0 for the sake of tests in common code */
170#define CPU_FTR_601 (0)
171#define CPU_FTR_PPC_LE (0)
172#endif
10b35d99 173
3965f8c5 174/*
9bbf0b57 175 * Definitions for the 64-bit processor unique features;
3965f8c5
PM		 176 * on 32-bit, make the names available but defined to be 0.
177 */
10b35d99 178#ifdef __powerpc64__
3965f8c5 179#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 180#else
3965f8c5 181#define LONG_ASM_CONST(x) 0
10b35d99
KG		 182#endif
183
9bbf0b57
PM		 184#define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
185#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
186#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000000004000)
187#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
188#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
189#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
190#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
191#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
192#define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
193#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
194#define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
195#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
196#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
197#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
198#define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
199#define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
200#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
201#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
202#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
203#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
204#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
205#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
206#define CPU_FTR_PKEY LONG_ASM_CONST(0x0000000400000000)
207#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
208#define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
209#define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
210#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
211#define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
212#define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
213#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
214#define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x0000040000000000)
215#define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
b5af4f27
PM		 216#define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
217#define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
3965f8c5 218
10b35d99
KG		 219#ifndef __ASSEMBLY__
220
44ae3ab3
ME		 221#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
222
13b3d13b 223#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
10b35d99
KG		 224
225/* We only set the altivec features if the kernel was compiled with altivec
226 * support
227 */
228#ifdef CONFIG_ALTIVEC
229#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
230#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
231#else
232#define CPU_FTR_ALTIVEC_COMP 0
233#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
234#endif
235
b962ce9d
MN		 236/* We only set the VSX features if the kernel was compiled with VSX
237 * support
238 */
239#ifdef CONFIG_VSX
240#define CPU_FTR_VSX_COMP CPU_FTR_VSX
241#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
242#else
243#define CPU_FTR_VSX_COMP 0
244#define PPC_FEATURE_HAS_VSX_COMP 0
245#endif
246
5e14d21e
KG		 247/* We only set the spe features if the kernel was compiled with spe
248 * support
249 */
250#ifdef CONFIG_SPE
251#define CPU_FTR_SPE_COMP CPU_FTR_SPE
252#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
253#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
254#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
255#else
256#define CPU_FTR_SPE_COMP 0
257#define PPC_FEATURE_HAS_SPE_COMP 0
258#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
259#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
260#endif
261
6a6d541f
MN		 262/* We only set the TM feature if the kernel was compiled with TM supprt */
263#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
b4b56f9e
S		 264#define CPU_FTR_TM_COMP CPU_FTR_TM
265#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
266#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
6a6d541f 267#else
b4b56f9e
S		 268#define CPU_FTR_TM_COMP 0
269#define PPC_FEATURE2_HTM_COMP 0
270#define PPC_FEATURE2_HTM_NOSC_COMP 0
6a6d541f
MN		 271#endif
272
11af1192
SW		 273/* We need to mark all pages as being coherent if we're SMP or we have a
274 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
275 * require it for PCI "streaming/prefetch" to work properly.
c9310920 276 * This is also required by 52xx family.
10b35d99 277 */
1775dbbc 278#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
c9310920
PZ		 279 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
280 || defined(CONFIG_PPC_MPC52xx)
10b35d99
KG		 281#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
282#else
283#define CPU_FTR_COMMON 0
284#endif
285
286/* The powersave features NAP & DOZE seems to confuse BDI when
287 debugging. So if a BDI is used, disable theses
288 */
289#ifndef CONFIG_BDI_SWITCH
290#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
291#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
292#else
293#define CPU_FTR_MAYBE_CAN_DOZE 0
294#define CPU_FTR_MAYBE_CAN_NAP 0
295#endif
296
7c03d653 297#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
c0d64cf9
PM		 298 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_USE_RTC)
299#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
fab5db97 300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
c0d64cf9 301#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
4508dc21 302#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
c0d64cf9 303 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 304 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 305#define CPU_FTRS_740 (CPU_FTR_COMMON | \
c0d64cf9 306 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 307 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 308 CPU_FTR_PPC_LE)
4508dc21 309#define CPU_FTRS_750 (CPU_FTR_COMMON | \
c0d64cf9 310 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 311 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 312 CPU_FTR_PPC_LE)
7c03d653 313#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 314#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
315#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 316#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 317#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 318#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
c0d64cf9 319 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 320 CPU_FTR_ALTIVEC_COMP | \
fab5db97 321 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 322#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
c0d64cf9 323 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
7c03d653 324 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 325 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 326#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
c0d64cf9 327 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 328 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 329 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 330#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c 331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 332 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 333 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 334 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 335#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
c0d64cf9 336 CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 337 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 338 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 339 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 340#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
c0d64cf9 341 CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 342 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 343 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 344#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
c0d64cf9 345 CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 346 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 347 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 348 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 349 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 350#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c 351 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 352 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 353 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 354#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c 355 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 356 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 357 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
358 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 359#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c 360 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 361 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 362 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 363#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c 364 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 365 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 366 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 367#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548 368 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 369 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 370 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
c0d64cf9 371#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE)
11af1192 372#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
c0d64cf9 373 CPU_FTR_MAYBE_CAN_NAP)
4508dc21 374#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
c0d64cf9 375 CPU_FTR_MAYBE_CAN_NAP | \
7c92943c 376 CPU_FTR_COMMON)
4508dc21 377#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
c0d64cf9 378 CPU_FTR_MAYBE_CAN_NAP | \
aa42c69c 379 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
c0d64cf9
PM		 380#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
381#define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
382#define CPU_FTRS_40X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
383#define CPU_FTRS_44X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
384#define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
6d2170be 385 CPU_FTR_INDEXED_DCR)
e7f75ad0 386#define CPU_FTRS_47X (CPU_FTRS_440x6)
c0d64cf9 387#define CPU_FTRS_E200 (CPU_FTR_SPE_COMP | \
5e14d21e 388 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
52b066fa
SW		 389 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
390 CPU_FTR_DEBUG_LVL_EXC)
c0d64cf9 391#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \
8309ce72
BH		 392 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
393 CPU_FTR_NOEXECUTE)
c0d64cf9 394#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 395 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 396 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
c0d64cf9 397#define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \
dd0efb3f 398 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
73196cd3 399 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
d52459ca
SW		 400/*
401 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
402 * same workaround as CPU_FTR_CELL_TB_BUG.
403 */
c0d64cf9 404#define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \
dd0efb3f 405 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
d36b4c4f 406 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 407 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
c0d64cf9 408#define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \
dd0efb3f 409 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
10241842 410 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 411 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
e16c8765 412 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
7c92943c 413#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 414
415/* 64-bit CPUs */
c0d64cf9 416#define CPU_FTRS_POWER4 (CPU_FTR_LWSYNC | \
7c03d653 417 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
f89451fb
AB		 418 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
419 CPU_FTR_STCX_CHECKS_ADDRESS)
c0d64cf9 420#define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
969391c5 421 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
2a929436 422 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
969391c5 423 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
82a9f16a 424 CPU_FTR_HVMODE | CPU_FTR_DABRX)
c0d64cf9 425#define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
7c03d653 426 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 427 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 428 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
82a9f16a 429 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
c0d64cf9 430#define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
7c03d653 431 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51 432 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 433 CPU_FTR_COHERENT_ICACHE | \
4c198557 434 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 435 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
82a9f16a
MN		 436 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
437 CPU_FTR_DABRX)
c0d64cf9 438#define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
969391c5 439 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
e952e6c4 440 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 441 CPU_FTR_COHERENT_ICACHE | \
e952e6c4 442 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 443 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
851d2e2f 444 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
c1807e3f 445 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
cf43d3b2 446 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX | CPU_FTR_PKEY)
c0d64cf9 447#define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
71e18497
MN		 448 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
449 CPU_FTR_MMCRA | CPU_FTR_SMT | \
450 CPU_FTR_COHERENT_ICACHE | \
451 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
452 CPU_FTR_DSCR | CPU_FTR_SAO | \
453 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
c1807e3f 454 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
1de2bd4e 455 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
cf43d3b2 456 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_PKEY)
68f2f0d4 457#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
bd6ba351 458#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
c0d64cf9 459#define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
c3ab300e
MN		 460 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
461 CPU_FTR_MMCRA | CPU_FTR_SMT | \
462 CPU_FTR_COHERENT_ICACHE | \
463 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
464 CPU_FTR_DSCR | CPU_FTR_SAO | \
465 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
2384d2d7 466 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
c3ab300e 467 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
cf43d3b2
RP		 468 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | \
469 CPU_FTR_PKEY)
ca80d5d0
NP		 470#define CPU_FTRS_POWER9_DD1 ((CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) & \
471 (~CPU_FTR_SAO))
3ffa9d9e
ME		 472#define CPU_FTRS_POWER9_DD2_0 CPU_FTRS_POWER9
473#define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1)
b5af4f27
PM		 474#define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_P9_TM_HV_ASSIST | \
475 CPU_FTR_P9_TM_XER_SO_BUG)
c0d64cf9 476#define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
7c03d653 477 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 478 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 479 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
82a9f16a 480 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
c0d64cf9 481#define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
44ae3ab3 482 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
82a9f16a 483 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
c0d64cf9 484#define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
10b35d99 485
2406f606 486#ifdef __powerpc64__
11ed0db9 487#ifdef CONFIG_PPC_BOOK3E
90029640 488#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
11ed0db9 489#else
7c92943c 490#define CPU_FTRS_POSSIBLE \
468a3302
ME		 491 (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
492 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
3609e09f 493 CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
b6b3755e 494 CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9 | \
b5af4f27
PM		 495 CPU_FTRS_POWER9_DD1 | CPU_FTRS_POWER9_DD2_1 | \
496 CPU_FTRS_POWER9_DD2_2)
11ed0db9 497#endif
2406f606 498#else
7c92943c
SR		 499enum {
500 CPU_FTRS_POSSIBLE =
1e07a0a0 501#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 502 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
503 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
504 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
505 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
506 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
507 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
508 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 509 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
510 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 511#else
512 CPU_FTRS_GENERIC_32 |
513#endif
968159c0 514#ifdef CONFIG_PPC_8xx
10b35d99
KG		 515 CPU_FTRS_8XX |
516#endif
517#ifdef CONFIG_40x
518 CPU_FTRS_40X |
519#endif
520#ifdef CONFIG_44x
6d2170be 521 CPU_FTRS_44X | CPU_FTRS_440x6 |
10b35d99 522#endif
e7f75ad0 523#ifdef CONFIG_PPC_47x
c48d0dba 524 CPU_FTRS_47X | CPU_FTR_476_DD2 |
e7f75ad0 525#endif
10b35d99
KG		 526#ifdef CONFIG_E200
527 CPU_FTRS_E200 |
528#endif
529#ifdef CONFIG_E500
06aae867
SW		 530 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
531#endif
532#ifdef CONFIG_PPC_E500MC
533 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
10b35d99 534#endif
10b35d99 535 0,
7c92943c
SR		 536};
537#endif /* __powerpc64__ */
10b35d99 538
2406f606 539#ifdef __powerpc64__
11ed0db9 540#ifdef CONFIG_PPC_BOOK3E
90029640 541#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
11ed0db9 542#else
7c92943c 543#define CPU_FTRS_ALWAYS \
468a3302
ME		 544 (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
545 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
3609e09f 546 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
c3ab300e
MN		 547 CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
548 CPU_FTRS_POWER9)
11ed0db9 549#endif
2406f606 550#else
7c92943c
SR		 551enum {
552 CPU_FTRS_ALWAYS =
1e07a0a0 553#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 554 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
555 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
556 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
557 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
558 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
559 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
560 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 561 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
562 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 563#else
564 CPU_FTRS_GENERIC_32 &
565#endif
968159c0 566#ifdef CONFIG_PPC_8xx
10b35d99
KG		 567 CPU_FTRS_8XX &
568#endif
569#ifdef CONFIG_40x
570 CPU_FTRS_40X &
571#endif
572#ifdef CONFIG_44x
6d2170be 573 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99
KG		 574#endif
575#ifdef CONFIG_E200
576 CPU_FTRS_E200 &
577#endif
578#ifdef CONFIG_E500
06aae867
SW		 579 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
580#endif
581#ifdef CONFIG_PPC_E500MC
582 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
10b35d99 583#endif
73196cd3 584 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
10b35d99
KG		 585 CPU_FTRS_POSSIBLE,
586};
7c92943c 587#endif /* __powerpc64__ */
10b35d99 588
5aae8a53 589#define HBP_NUM 1
5aae8a53 590
10b35d99
KG		 591#endif /* !__ASSEMBLY__ */
592
10b35d99 593#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)