[linux-2.6-block.git] / include / asm-powerpc / cputable.h

#ifndef __ASM_POWERPC_CPUTABLE_H
#define __ASM_POWERPC_CPUTABLE_H

#include <asm/asm-compat.h>

#define PPC_FEATURE_32			0x80000000
#define PPC_FEATURE_64			0x40000000
#define PPC_FEATURE_601_INSTR		0x20000000
#define PPC_FEATURE_HAS_ALTIVEC		0x10000000
#define PPC_FEATURE_HAS_FPU		0x08000000
#define PPC_FEATURE_HAS_MMU		0x04000000
#define PPC_FEATURE_HAS_4xxMAC		0x02000000
#define PPC_FEATURE_UNIFIED_CACHE	0x01000000
#define PPC_FEATURE_HAS_SPE		0x00800000
#define PPC_FEATURE_HAS_EFP_SINGLE	0x00400000
#define PPC_FEATURE_HAS_EFP_DOUBLE	0x00200000
#define PPC_FEATURE_NO_TB		0x00100000
#define PPC_FEATURE_POWER4		0x00080000
#define PPC_FEATURE_POWER5		0x00040000
#define PPC_FEATURE_POWER5_PLUS		0x00020000
#define PPC_FEATURE_CELL		0x00010000
#define PPC_FEATURE_BOOKE		0x00008000
#define PPC_FEATURE_SMT			0x00004000
#define PPC_FEATURE_ICACHE_SNOOP	0x00002000
#define PPC_FEATURE_ARCH_2_05		0x00001000
#define PPC_FEATURE_PA6T		0x00000800

#define PPC_FEATURE_TRUE_LE		0x00000002
#define PPC_FEATURE_PPC_LE		0x00000001

#ifdef __KERNEL__
#ifndef __ASSEMBLY__

/* This structure can grow, it's real size is used by head.S code
 * via the mkdefs mechanism.
 */
struct cpu_spec;

typedef	void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
typedef	void (*cpu_restore_t)(void);

enum powerpc_oprofile_type {
	PPC_OPROFILE_INVALID = 0,
	PPC_OPROFILE_RS64 = 1,
	PPC_OPROFILE_POWER4 = 2,
	PPC_OPROFILE_G4 = 3,
	PPC_OPROFILE_BOOKE = 4,
};

struct cpu_spec {
	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
	unsigned int	pvr_mask;
	unsigned int	pvr_value;

	char		*cpu_name;
	unsigned long	cpu_features;		/* Kernel features */
	unsigned int	cpu_user_features;	/* Userland features */

	/* cache line sizes */
	unsigned int	icache_bsize;
	unsigned int	dcache_bsize;

	/* number of performance monitor counters */
	unsigned int	num_pmcs;

	/* this is called to initialize various CPU bits like L1 cache,
	 * BHT, SPD, etc... from head.S before branching to identify_machine
	 */
	cpu_setup_t	cpu_setup;
	/* Used to restore cpu setup on secondary processors and at resume */
	cpu_restore_t	cpu_restore;

	/* Used by oprofile userspace to select the right counters */
	char		*oprofile_cpu_type;

	/* Processor specific oprofile operations */
	enum powerpc_oprofile_type oprofile_type;

	/* Bit locations inside the mmcra change */
	unsigned long	oprofile_mmcra_sihv;
	unsigned long	oprofile_mmcra_sipr;

	/* Bits to clear during an oprofile exception */
	unsigned long	oprofile_mmcra_clear;

	/* Name of processor class, for the ELF AT_PLATFORM entry */
	char		*platform;
};

extern struct cpu_spec		*cur_cpu_spec;

extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;

extern struct cpu_spec *identify_cpu(unsigned long offset);
extern void do_feature_fixups(unsigned long value, void *fixup_start,
			      void *fixup_end);

#endif /* __ASSEMBLY__ */

/* CPU kernel features */

/* Retain the 32b definitions all use bottom half of word */
#define CPU_FTR_SPLIT_ID_CACHE		ASM_CONST(0x0000000000000001)
#define CPU_FTR_L2CR			ASM_CONST(0x0000000000000002)
#define CPU_FTR_SPEC7450		ASM_CONST(0x0000000000000004)
#define CPU_FTR_ALTIVEC			ASM_CONST(0x0000000000000008)
#define CPU_FTR_TAU			ASM_CONST(0x0000000000000010)
#define CPU_FTR_CAN_DOZE		ASM_CONST(0x0000000000000020)
#define CPU_FTR_USE_TB			ASM_CONST(0x0000000000000040)
#define CPU_FTR_604_PERF_MON		ASM_CONST(0x0000000000000080)
#define CPU_FTR_601			ASM_CONST(0x0000000000000100)
#define CPU_FTR_HPTE_TABLE		ASM_CONST(0x0000000000000200)
#define CPU_FTR_CAN_NAP			ASM_CONST(0x0000000000000400)
#define CPU_FTR_L3CR			ASM_CONST(0x0000000000000800)
#define CPU_FTR_L3_DISABLE_NAP		ASM_CONST(0x0000000000001000)
#define CPU_FTR_NAP_DISABLE_L2_PR	ASM_CONST(0x0000000000002000)
#define CPU_FTR_DUAL_PLL_750FX		ASM_CONST(0x0000000000004000)
#define CPU_FTR_NO_DPM			ASM_CONST(0x0000000000008000)
#define CPU_FTR_HAS_HIGH_BATS		ASM_CONST(0x0000000000010000)
#define CPU_FTR_NEED_COHERENT		ASM_CONST(0x0000000000020000)
#define CPU_FTR_NO_BTIC			ASM_CONST(0x0000000000040000)
#define CPU_FTR_BIG_PHYS		ASM_CONST(0x0000000000080000)
#define CPU_FTR_NODSISRALIGN		ASM_CONST(0x0000000000100000)
#define CPU_FTR_PPC_LE			ASM_CONST(0x0000000000200000)
#define CPU_FTR_REAL_LE			ASM_CONST(0x0000000000400000)

/*
 * Add the 64-bit processor unique features in the top half of the word;
 * on 32-bit, make the names available but defined to be 0.
 */
#ifdef __powerpc64__
#define LONG_ASM_CONST(x)		ASM_CONST(x)
#else
#define LONG_ASM_CONST(x)		0
#endif

#define CPU_FTR_SLB			LONG_ASM_CONST(0x0000000100000000)
#define CPU_FTR_16M_PAGE		LONG_ASM_CONST(0x0000000200000000)
#define CPU_FTR_TLBIEL			LONG_ASM_CONST(0x0000000400000000)
#define CPU_FTR_NOEXECUTE		LONG_ASM_CONST(0x0000000800000000)
#define CPU_FTR_IABR			LONG_ASM_CONST(0x0000002000000000)
#define CPU_FTR_MMCRA			LONG_ASM_CONST(0x0000004000000000)
#define CPU_FTR_CTRL			LONG_ASM_CONST(0x0000008000000000)
#define CPU_FTR_SMT			LONG_ASM_CONST(0x0000010000000000)
#define CPU_FTR_COHERENT_ICACHE		LONG_ASM_CONST(0x0000020000000000)
#define CPU_FTR_LOCKLESS_TLBIE		LONG_ASM_CONST(0x0000040000000000)
#define CPU_FTR_CI_LARGE_PAGE		LONG_ASM_CONST(0x0000100000000000)
#define CPU_FTR_PAUSE_ZERO		LONG_ASM_CONST(0x0000200000000000)
#define CPU_FTR_PURR			LONG_ASM_CONST(0x0000400000000000)
#define CPU_FTR_CELL_TB_BUG		LONG_ASM_CONST(0x0000800000000000)

#ifndef __ASSEMBLY__

#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
					CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
					CPU_FTR_NODSISRALIGN)

/* iSeries doesn't support large pages */
#ifdef CONFIG_PPC_ISERIES
#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_PPCAS_ARCH_V2_BASE)
#else
#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
#endif /* CONFIG_PPC_ISERIES */

/* We only set the altivec features if the kernel was compiled with altivec
 * support
 */
#ifdef CONFIG_ALTIVEC
#define CPU_FTR_ALTIVEC_COMP	CPU_FTR_ALTIVEC
#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
#else
#define CPU_FTR_ALTIVEC_COMP	0
#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
#endif

/* We need to mark all pages as being coherent if we're SMP or we
 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
 * it for PCI "streaming/prefetch" to work properly.
 */
#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
	|| defined(CONFIG_PPC_83xx)
#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
#else
#define CPU_FTR_COMMON                  0
#endif

/* The powersave features NAP & DOZE seems to confuse BDI when
   debugging. So if a BDI is used, disable theses
 */
#ifndef CONFIG_BDI_SWITCH
#define CPU_FTR_MAYBE_CAN_DOZE	CPU_FTR_CAN_DOZE
#define CPU_FTR_MAYBE_CAN_NAP	CPU_FTR_CAN_NAP
#else
#define CPU_FTR_MAYBE_CAN_DOZE	0
#define CPU_FTR_MAYBE_CAN_NAP	0
#endif

#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
		     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
		     !defined(CONFIG_BOOKE))

#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
#define CPU_FTRS_603	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
#define CPU_FTRS_604	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
	    CPU_FTR_PPC_LE)
#define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
#define CPU_FTRS_740	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_PPC_LE)
#define CPU_FTRS_750	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_PPC_LE)
#define CPU_FTRS_750FX1	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
#define CPU_FTRS_750FX2	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
#define CPU_FTRS_750FX	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
#define CPU_FTRS_750GX	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
#define CPU_FTRS_7400_NOTAU	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
#define CPU_FTRS_7400	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
#define CPU_FTRS_7450_20	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7450_21	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7450_23	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7455_1	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7455_20	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
#define CPU_FTRS_7455	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7447_10	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
#define CPU_FTRS_7447	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_7447A	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
#define CPU_FTRS_82XX	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
#define CPU_FTRS_G2_LE	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
#define CPU_FTRS_E300	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_COMMON)
#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
#define CPU_FTRS_8XX	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
#define CPU_FTRS_40X	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_44X	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_E500	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_E500_2	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
#ifdef __powerpc64__
#define CPU_FTRS_POWER3	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
#define CPU_FTRS_RS64	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
	    CPU_FTR_MMCRA | CPU_FTR_CTRL)
#define CPU_FTRS_POWER4	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
	    CPU_FTR_MMCRA)
#define CPU_FTRS_PPC970	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
#define CPU_FTRS_POWER5	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
	    CPU_FTR_PURR)
#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
	    CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
#define CPU_FTRS_CELL	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
	    CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
	    CPU_FTR_PURR | CPU_FTR_REAL_LE)
#define CPU_FTRS_COMPATIBLE	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
#endif

#ifdef __powerpc64__
#define CPU_FTRS_POSSIBLE	\
	    (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |	\
	    CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |	\
	    CPU_FTRS_CELL | CPU_FTRS_PA6T)
#else
enum {
	CPU_FTRS_POSSIBLE =
#if CLASSIC_PPC
	    CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
	    CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
	    CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
	    CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
	    CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
	    CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
	    CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
	    CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
#else
	    CPU_FTRS_GENERIC_32 |
#endif
#ifdef CONFIG_8xx
	    CPU_FTRS_8XX |
#endif
#ifdef CONFIG_40x
	    CPU_FTRS_40X |
#endif
#ifdef CONFIG_44x
	    CPU_FTRS_44X |
#endif
#ifdef CONFIG_E200
	    CPU_FTRS_E200 |
#endif
#ifdef CONFIG_E500
	    CPU_FTRS_E500 | CPU_FTRS_E500_2 |
#endif
	    0,
};
#endif /* __powerpc64__ */

#ifdef __powerpc64__
#define CPU_FTRS_ALWAYS		\
	    (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &	\
	    CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &	\
	    CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
#else
enum {
	CPU_FTRS_ALWAYS =
#if CLASSIC_PPC
	    CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
	    CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
	    CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
	    CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
	    CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
	    CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
	    CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
	    CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
#else
	    CPU_FTRS_GENERIC_32 &
#endif
#ifdef CONFIG_8xx
	    CPU_FTRS_8XX &
#endif
#ifdef CONFIG_40x
	    CPU_FTRS_40X &
#endif
#ifdef CONFIG_44x
	    CPU_FTRS_44X &
#endif
#ifdef CONFIG_E200
	    CPU_FTRS_E200 &
#endif
#ifdef CONFIG_E500
	    CPU_FTRS_E500 & CPU_FTRS_E500_2 &
#endif
	    CPU_FTRS_POSSIBLE,
};
#endif /* __powerpc64__ */

static inline int cpu_has_feature(unsigned long feature)
{
	return (CPU_FTRS_ALWAYS & feature) ||
	       (CPU_FTRS_POSSIBLE
		& cur_cpu_spec->cpu_features
		& feature);
}

#endif /* !__ASSEMBLY__ */

#ifdef __ASSEMBLY__

#define BEGIN_FTR_SECTION_NESTED(label)	label:
#define BEGIN_FTR_SECTION		BEGIN_FTR_SECTION_NESTED(97)
#define END_FTR_SECTION_NESTED(msk, val, label) \
	MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
#define END_FTR_SECTION(msk, val)		\
	END_FTR_SECTION_NESTED(msk, val, 97)

#define END_FTR_SECTION_IFSET(msk)	END_FTR_SECTION((msk), (msk))
#define END_FTR_SECTION_IFCLR(msk)	END_FTR_SECTION((msk), 0)
#endif /* __ASSEMBLY__ */

#endif /* __KERNEL__ */
#endif /* __ASM_POWERPC_CPUTABLE_H */
Commit	Line	Data
10b35d99 KG	1	#ifndef __ASM_POWERPC_CPUTABLE_H
	2	#define __ASM_POWERPC_CPUTABLE_H
	3
3ddfbcf1	4	#include <asm/asm-compat.h>
10b35d99 KG	5
	6	#define PPC_FEATURE_32 0x80000000
	7	#define PPC_FEATURE_64 0x40000000
	8	#define PPC_FEATURE_601_INSTR 0x20000000
	9	#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
	10	#define PPC_FEATURE_HAS_FPU 0x08000000
	11	#define PPC_FEATURE_HAS_MMU 0x04000000
	12	#define PPC_FEATURE_HAS_4xxMAC 0x02000000
	13	#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
	14	#define PPC_FEATURE_HAS_SPE 0x00800000
	15	#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
	16	#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
98599013	17	#define PPC_FEATURE_NO_TB 0x00100000
a7ddc5e8 PM	18	#define PPC_FEATURE_POWER4 0x00080000
	19	#define PPC_FEATURE_POWER5 0x00040000
	20	#define PPC_FEATURE_POWER5_PLUS 0x00020000
	21	#define PPC_FEATURE_CELL 0x00010000
80f15dc7	22	#define PPC_FEATURE_BOOKE 0x00008000
aa5cb021 BH	23	#define PPC_FEATURE_SMT 0x00004000
aa5cb021 BH	24	#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
03054d51	25	#define PPC_FEATURE_ARCH_2_05 0x00001000
b3ebd1d8	26	#define PPC_FEATURE_PA6T 0x00000800
10b35d99	27
fab5db97 PM	28	#define PPC_FEATURE_TRUE_LE 0x00000002
	29	#define PPC_FEATURE_PPC_LE 0x00000001
	30
10b35d99 KG	31	#ifdef __KERNEL__
	32	#ifndef __ASSEMBLY__
	33
	34	/* This structure can grow, it's real size is used by head.S code
	35	* via the mkdefs mechanism.
	36	*/
	37	struct cpu_spec;
10b35d99	38
10b35d99	39	typedef void (cpu_setup_t)(unsigned long offset, struct cpu_spec spec);
f39b7a55	40	typedef void (*cpu_restore_t)(void);
10b35d99	41
32a33994	42	enum powerpc_oprofile_type {
7a45fb19 AW	43	PPC_OPROFILE_INVALID = 0,
	44	PPC_OPROFILE_RS64 = 1,
	45	PPC_OPROFILE_POWER4 = 2,
	46	PPC_OPROFILE_G4 = 3,
	47	PPC_OPROFILE_BOOKE = 4,
32a33994 AB	48	};
32a33994 AB	49
10b35d99 KG	50	struct cpu_spec {
	51	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
	52	unsigned int pvr_mask;
	53	unsigned int pvr_value;
	54
	55	char *cpu_name;
	56	unsigned long cpu_features; /* Kernel features */
	57	unsigned int cpu_user_features; /* Userland features */
	58
	59	/* cache line sizes */
	60	unsigned int icache_bsize;
	61	unsigned int dcache_bsize;
	62
	63	/* number of performance monitor counters */
	64	unsigned int num_pmcs;
	65
	66	/* this is called to initialize various CPU bits like L1 cache,
	67	* BHT, SPD, etc... from head.S before branching to identify_machine
	68	*/
	69	cpu_setup_t cpu_setup;
f39b7a55 OJ	70	/* Used to restore cpu setup on secondary processors and at resume */
f39b7a55 OJ	71	cpu_restore_t cpu_restore;
10b35d99 KG	72
	73	/* Used by oprofile userspace to select the right counters */
	74	char *oprofile_cpu_type;
	75
	76	/* Processor specific oprofile operations */
32a33994	77	enum powerpc_oprofile_type oprofile_type;
80f15dc7	78
e78dbc80 MN	79	/* Bit locations inside the mmcra change */
	80	unsigned long oprofile_mmcra_sihv;
	81	unsigned long oprofile_mmcra_sipr;
	82
	83	/* Bits to clear during an oprofile exception */
	84	unsigned long oprofile_mmcra_clear;
	85
80f15dc7 PM	86	/* Name of processor class, for the ELF AT_PLATFORM entry */
80f15dc7 PM	87	char *platform;
10b35d99 KG	88	};
10b35d99 KG	89
10b35d99	90	extern struct cpu_spec *cur_cpu_spec;
10b35d99	91
42c4aaad BH	92	extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
	93
	94	extern struct cpu_spec *identify_cpu(unsigned long offset);
0909c8c2 BH	95	extern void do_feature_fixups(unsigned long value, void *fixup_start,
0909c8c2 BH	96	void *fixup_end);
9b6b563c	97
10b35d99 KG	98	#endif /* __ASSEMBLY__ */
	99
	100	/* CPU kernel features */
	101
	102	/* Retain the 32b definitions all use bottom half of word */
	103	#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
	104	#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
	105	#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
	106	#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
	107	#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
	108	#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
	109	#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
	110	#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
	111	#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
	112	#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
	113	#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
	114	#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
	115	#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
	116	#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
	117	#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
	118	#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
	119	#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
	120	#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
	121	#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
	122	#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
3d15910b	123	#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
fab5db97 PM	124	#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
fab5db97 PM	125	#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
10b35d99	126
3965f8c5 PM	127	/*
	128	* Add the 64-bit processor unique features in the top half of the word;
	129	* on 32-bit, make the names available but defined to be 0.
	130	*/
10b35d99	131	#ifdef __powerpc64__
3965f8c5	132	#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99	133	#else
3965f8c5	134	#define LONG_ASM_CONST(x) 0
10b35d99 KG	135	#endif
10b35d99 KG	136
3965f8c5 PM	137	#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
	138	#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
	139	#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
	140	#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
	141	#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
	142	#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
	143	#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
	144	#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
	145	#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
	146	#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
	147	#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
	148	#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
	149	#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
859deea9	150	#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
3965f8c5	151
10b35d99 KG	152	#ifndef __ASSEMBLY__
10b35d99 KG	153
10b35d99 KG	154	#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB \| \
10b35d99 KG	155	CPU_FTR_TLBIEL \| CPU_FTR_NOEXECUTE \| \
00243000	156	CPU_FTR_NODSISRALIGN)
10b35d99 KG	157
	158	/* iSeries doesn't support large pages */
	159	#ifdef CONFIG_PPC_ISERIES
	160	#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
	161	#else
	162	#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE \| CPU_FTR_16M_PAGE)
	163	#endif /* CONFIG_PPC_ISERIES */
	164
	165	/* We only set the altivec features if the kernel was compiled with altivec
	166	* support
	167	*/
	168	#ifdef CONFIG_ALTIVEC
	169	#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
	170	#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
	171	#else
	172	#define CPU_FTR_ALTIVEC_COMP 0
	173	#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
	174	#endif
	175
	176	/* We need to mark all pages as being coherent if we're SMP or we
1775dbbc KG	177	* have a 74[45]x and an MPC107 host bridge. Also 83xx requires
1775dbbc KG	178	* it for PCI "streaming/prefetch" to work properly.
10b35d99	179	*/
1775dbbc KG	180	#if defined(CONFIG_SMP) \|\| defined(CONFIG_MPC10X_BRIDGE) \
1775dbbc KG	181	\|\| defined(CONFIG_PPC_83xx)
10b35d99 KG	182	#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
	183	#else
	184	#define CPU_FTR_COMMON 0
	185	#endif
	186
	187	/* The powersave features NAP & DOZE seems to confuse BDI when
	188	debugging. So if a BDI is used, disable theses
	189	*/
	190	#ifndef CONFIG_BDI_SWITCH
	191	#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
	192	#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
	193	#else
	194	#define CPU_FTR_MAYBE_CAN_DOZE 0
	195	#define CPU_FTR_MAYBE_CAN_NAP 0
	196	#endif
	197
	198	#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
	199	!defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
	200	!defined(CONFIG_BOOKE))
	201
7c92943c SR	202	#define CPU_FTRS_PPC601 (CPU_FTR_COMMON \| CPU_FTR_601 \| CPU_FTR_HPTE_TABLE)
	203	#define CPU_FTRS_603 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	204	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
fab5db97	205	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
7c92943c	206	#define CPU_FTRS_604 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
fab5db97 PM	207	CPU_FTR_USE_TB \| CPU_FTR_604_PERF_MON \| CPU_FTR_HPTE_TABLE \| \
fab5db97 PM	208	CPU_FTR_PPC_LE)
7c92943c SR	209	#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
7c92943c SR	210	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
fab5db97	211	CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
7c92943c SR	212	#define CPU_FTRS_740 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
7c92943c SR	213	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
fab5db97 PM	214	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
fab5db97 PM	215	CPU_FTR_PPC_LE)
7c92943c SR	216	#define CPU_FTRS_750 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
7c92943c SR	217	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
fab5db97 PM	218	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
fab5db97 PM	219	CPU_FTR_PPC_LE)
7c92943c SR	220	#define CPU_FTRS_750FX1 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	221	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	222	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
fab5db97	223	CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_NO_DPM \| CPU_FTR_PPC_LE)
7c92943c SR	224	#define CPU_FTRS_750FX2 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	225	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	226	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
fab5db97	227	CPU_FTR_NO_DPM \| CPU_FTR_PPC_LE)
7c92943c SR	228	#define CPU_FTRS_750FX (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	229	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	230	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
fab5db97	231	CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_HAS_HIGH_BATS \| CPU_FTR_PPC_LE)
7c92943c SR	232	#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_MAYBE_CAN_DOZE \| \
	233	CPU_FTR_USE_TB \| CPU_FTR_L2CR \| CPU_FTR_TAU \| \
	234	CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
fab5db97	235	CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_HAS_HIGH_BATS \| CPU_FTR_PPC_LE)
7c92943c SR	236	#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	237	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	238	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_HPTE_TABLE \| \
fab5db97	239	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
7c92943c SR	240	#define CPU_FTRS_7400 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	241	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	242	CPU_FTR_TAU \| CPU_FTR_ALTIVEC_COMP \| CPU_FTR_HPTE_TABLE \| \
fab5db97	243	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
7c92943c SR	244	#define CPU_FTRS_7450_20 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	245	CPU_FTR_USE_TB \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	246	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
fab5db97	247	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
7c92943c SR	248	#define CPU_FTRS_7450_21 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	249	CPU_FTR_USE_TB \| \
	250	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	251	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
	252	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
fab5db97	253	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
7c92943c SR	254	#define CPU_FTRS_7450_23 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	255	CPU_FTR_USE_TB \| \
	256	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	257	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
fab5db97	258	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
7c92943c SR	259	#define CPU_FTRS_7455_1 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	260	CPU_FTR_USE_TB \| \
	261	CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| CPU_FTR_L3CR \| \
	262	CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| CPU_FTR_HAS_HIGH_BATS \| \
fab5db97	263	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
7c92943c SR	264	#define CPU_FTRS_7455_20 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	265	CPU_FTR_USE_TB \| \
	266	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	267	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
	268	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
fab5db97	269	CPU_FTR_NEED_COHERENT \| CPU_FTR_HAS_HIGH_BATS \| CPU_FTR_PPC_LE)
7c92943c SR	270	#define CPU_FTRS_7455 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	271	CPU_FTR_USE_TB \| \
	272	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	273	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
	274	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
fab5db97	275	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
7c92943c SR	276	#define CPU_FTRS_7447_10 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	277	CPU_FTR_USE_TB \| \
	278	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	279	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
	280	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
fab5db97	281	CPU_FTR_NEED_COHERENT \| CPU_FTR_NO_BTIC \| CPU_FTR_PPC_LE)
7c92943c SR	282	#define CPU_FTRS_7447 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	283	CPU_FTR_USE_TB \| \
	284	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	285	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
	286	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
fab5db97	287	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
7c92943c SR	288	#define CPU_FTRS_7447A (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	289	CPU_FTR_USE_TB \| \
	290	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	291	CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
	292	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
fab5db97	293	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
7c92943c SR	294	#define CPU_FTRS_82XX (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	295	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB)
	296	#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_MAYBE_CAN_DOZE \| \
	297	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_HAS_HIGH_BATS)
	298	#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_MAYBE_CAN_DOZE \| \
	299	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_HAS_HIGH_BATS \| \
	300	CPU_FTR_COMMON)
	301	#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	302	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE)
7c92943c SR	303	#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB)
	304	#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	305	CPU_FTR_NODSISRALIGN)
	306	#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	307	CPU_FTR_NODSISRALIGN)
	308	#define CPU_FTRS_E200 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN)
	309	#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	310	CPU_FTR_NODSISRALIGN)
	311	#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	312	CPU_FTR_BIG_PHYS \| CPU_FTR_NODSISRALIGN)
	313	#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON \| CPU_FTR_NODSISRALIGN)
10b35d99	314	#ifdef __powerpc64__
7c92943c	315	#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
fab5db97	316	CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \| CPU_FTR_PPC_LE)
7c92943c SR	317	#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	318	CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \| \
	319	CPU_FTR_MMCRA \| CPU_FTR_CTRL)
	320	#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
00243000 OJ	321	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
00243000 OJ	322	CPU_FTR_MMCRA)
7c92943c	323	#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
00243000	324	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
7c92943c SR	325	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_CAN_NAP \| CPU_FTR_MMCRA)
7c92943c SR	326	#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
00243000	327	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
7c92943c SR	328	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
7c92943c SR	329	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \| \
e78dbc80	330	CPU_FTR_PURR)
03054d51	331	#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
00243000	332	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
03054d51 AB	333	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
03054d51 AB	334	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \| \
fab5db97	335	CPU_FTR_PURR \| CPU_FTR_CI_LARGE_PAGE \| CPU_FTR_REAL_LE)
7c92943c	336	#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
00243000	337	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
7c92943c	338	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
859deea9	339	CPU_FTR_PAUSE_ZERO \| CPU_FTR_CI_LARGE_PAGE \| CPU_FTR_CELL_TB_BUG)
b3ebd1d8 OJ	340	#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	341	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| \
	342	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_CI_LARGE_PAGE \| \
	343	CPU_FTR_PURR \| CPU_FTR_REAL_LE)
7c92943c SR	344	#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
7c92943c SR	345	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2)
10b35d99 KG	346	#endif
10b35d99 KG	347
2406f606	348	#ifdef __powerpc64__
7c92943c SR	349	#define CPU_FTRS_POSSIBLE \
7c92943c SR	350	(CPU_FTRS_POWER3 \| CPU_FTRS_RS64 \| CPU_FTRS_POWER4 \| \
03054d51	351	CPU_FTRS_PPC970 \| CPU_FTRS_POWER5 \| CPU_FTRS_POWER6 \| \
b3ebd1d8	352	CPU_FTRS_CELL \| CPU_FTRS_PA6T)
2406f606	353	#else
7c92943c SR	354	enum {
7c92943c SR	355	CPU_FTRS_POSSIBLE =
10b35d99 KG	356	#if CLASSIC_PPC
	357	CPU_FTRS_PPC601 \| CPU_FTRS_603 \| CPU_FTRS_604 \| CPU_FTRS_740_NOTAU \|
	358	CPU_FTRS_740 \| CPU_FTRS_750 \| CPU_FTRS_750FX1 \|
	359	CPU_FTRS_750FX2 \| CPU_FTRS_750FX \| CPU_FTRS_750GX \|
	360	CPU_FTRS_7400_NOTAU \| CPU_FTRS_7400 \| CPU_FTRS_7450_20 \|
	361	CPU_FTRS_7450_21 \| CPU_FTRS_7450_23 \| CPU_FTRS_7455_1 \|
	362	CPU_FTRS_7455_20 \| CPU_FTRS_7455 \| CPU_FTRS_7447_10 \|
	363	CPU_FTRS_7447 \| CPU_FTRS_7447A \| CPU_FTRS_82XX \|
	364	CPU_FTRS_G2_LE \| CPU_FTRS_E300 \| CPU_FTRS_CLASSIC32 \|
	365	#else
	366	CPU_FTRS_GENERIC_32 \|
	367	#endif
10b35d99 KG	368	#ifdef CONFIG_8xx
	369	CPU_FTRS_8XX \|
	370	#endif
	371	#ifdef CONFIG_40x
	372	CPU_FTRS_40X \|
	373	#endif
	374	#ifdef CONFIG_44x
	375	CPU_FTRS_44X \|
	376	#endif
	377	#ifdef CONFIG_E200
	378	CPU_FTRS_E200 \|
	379	#endif
	380	#ifdef CONFIG_E500
	381	CPU_FTRS_E500 \| CPU_FTRS_E500_2 \|
	382	#endif
10b35d99	383	0,
7c92943c SR	384	};
7c92943c SR	385	#endif /* __powerpc64__ */
10b35d99	386
2406f606	387	#ifdef __powerpc64__
7c92943c SR	388	#define CPU_FTRS_ALWAYS \
7c92943c SR	389	(CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51	390	CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
b3ebd1d8	391	CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
2406f606	392	#else
7c92943c SR	393	enum {
7c92943c SR	394	CPU_FTRS_ALWAYS =
10b35d99 KG	395	#if CLASSIC_PPC
	396	CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
	397	CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
	398	CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
	399	CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
	400	CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
	401	CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
	402	CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
	403	CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
	404	#else
	405	CPU_FTRS_GENERIC_32 &
	406	#endif
10b35d99 KG	407	#ifdef CONFIG_8xx
	408	CPU_FTRS_8XX &
	409	#endif
	410	#ifdef CONFIG_40x
	411	CPU_FTRS_40X &
	412	#endif
	413	#ifdef CONFIG_44x
	414	CPU_FTRS_44X &
	415	#endif
	416	#ifdef CONFIG_E200
	417	CPU_FTRS_E200 &
	418	#endif
	419	#ifdef CONFIG_E500
	420	CPU_FTRS_E500 & CPU_FTRS_E500_2 &
	421	#endif
10b35d99 KG	422	CPU_FTRS_POSSIBLE,
10b35d99 KG	423	};
7c92943c	424	#endif /* __powerpc64__ */
10b35d99 KG	425
	426	static inline int cpu_has_feature(unsigned long feature)
	427	{
	428	return (CPU_FTRS_ALWAYS & feature) \|\|
	429	(CPU_FTRS_POSSIBLE
10b35d99	430	& cur_cpu_spec->cpu_features
10b35d99 KG	431	& feature);
	432	}
	433
	434	#endif /* !__ASSEMBLY__ */
	435
	436	#ifdef __ASSEMBLY__
	437
7aeb7324	438	#define BEGIN_FTR_SECTION_NESTED(label) label:
0909c8c2	439	#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
7aeb7324	440	#define END_FTR_SECTION_NESTED(msk, val, label) \
0909c8c2	441	MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
7aeb7324	442	#define END_FTR_SECTION(msk, val) \
0909c8c2	443	END_FTR_SECTION_NESTED(msk, val, 97)
7aeb7324	444
10b35d99 KG	445	#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
	446	#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
	447	#endif /* __ASSEMBLY__ */
	448
	449	#endif /* __KERNEL__ */
	450	#endif /* __ASM_POWERPC_CPUTABLE_H */