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10b35d99 KG |
1 | #ifndef __ASM_POWERPC_CPUTABLE_H |
2 | #define __ASM_POWERPC_CPUTABLE_H | |
3 | ||
3ddfbcf1 | 4 | #include <asm/asm-compat.h> |
10b35d99 KG |
5 | |
6 | #define PPC_FEATURE_32 0x80000000 | |
7 | #define PPC_FEATURE_64 0x40000000 | |
8 | #define PPC_FEATURE_601_INSTR 0x20000000 | |
9 | #define PPC_FEATURE_HAS_ALTIVEC 0x10000000 | |
10 | #define PPC_FEATURE_HAS_FPU 0x08000000 | |
11 | #define PPC_FEATURE_HAS_MMU 0x04000000 | |
12 | #define PPC_FEATURE_HAS_4xxMAC 0x02000000 | |
13 | #define PPC_FEATURE_UNIFIED_CACHE 0x01000000 | |
14 | #define PPC_FEATURE_HAS_SPE 0x00800000 | |
15 | #define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 | |
16 | #define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 | |
98599013 | 17 | #define PPC_FEATURE_NO_TB 0x00100000 |
a7ddc5e8 PM |
18 | #define PPC_FEATURE_POWER4 0x00080000 |
19 | #define PPC_FEATURE_POWER5 0x00040000 | |
20 | #define PPC_FEATURE_POWER5_PLUS 0x00020000 | |
21 | #define PPC_FEATURE_CELL 0x00010000 | |
80f15dc7 | 22 | #define PPC_FEATURE_BOOKE 0x00008000 |
aa5cb021 BH |
23 | #define PPC_FEATURE_SMT 0x00004000 |
24 | #define PPC_FEATURE_ICACHE_SNOOP 0x00002000 | |
03054d51 | 25 | #define PPC_FEATURE_ARCH_2_05 0x00001000 |
10b35d99 | 26 | |
fab5db97 PM |
27 | #define PPC_FEATURE_TRUE_LE 0x00000002 |
28 | #define PPC_FEATURE_PPC_LE 0x00000001 | |
29 | ||
10b35d99 KG |
30 | #ifdef __KERNEL__ |
31 | #ifndef __ASSEMBLY__ | |
32 | ||
33 | /* This structure can grow, it's real size is used by head.S code | |
34 | * via the mkdefs mechanism. | |
35 | */ | |
36 | struct cpu_spec; | |
10b35d99 | 37 | |
10b35d99 | 38 | typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec); |
10b35d99 | 39 | |
32a33994 | 40 | enum powerpc_oprofile_type { |
7a45fb19 AW |
41 | PPC_OPROFILE_INVALID = 0, |
42 | PPC_OPROFILE_RS64 = 1, | |
43 | PPC_OPROFILE_POWER4 = 2, | |
44 | PPC_OPROFILE_G4 = 3, | |
45 | PPC_OPROFILE_BOOKE = 4, | |
32a33994 AB |
46 | }; |
47 | ||
10b35d99 KG |
48 | struct cpu_spec { |
49 | /* CPU is matched via (PVR & pvr_mask) == pvr_value */ | |
50 | unsigned int pvr_mask; | |
51 | unsigned int pvr_value; | |
52 | ||
53 | char *cpu_name; | |
54 | unsigned long cpu_features; /* Kernel features */ | |
55 | unsigned int cpu_user_features; /* Userland features */ | |
56 | ||
57 | /* cache line sizes */ | |
58 | unsigned int icache_bsize; | |
59 | unsigned int dcache_bsize; | |
60 | ||
61 | /* number of performance monitor counters */ | |
62 | unsigned int num_pmcs; | |
63 | ||
64 | /* this is called to initialize various CPU bits like L1 cache, | |
65 | * BHT, SPD, etc... from head.S before branching to identify_machine | |
66 | */ | |
67 | cpu_setup_t cpu_setup; | |
10b35d99 KG |
68 | |
69 | /* Used by oprofile userspace to select the right counters */ | |
70 | char *oprofile_cpu_type; | |
71 | ||
72 | /* Processor specific oprofile operations */ | |
32a33994 | 73 | enum powerpc_oprofile_type oprofile_type; |
80f15dc7 | 74 | |
e78dbc80 MN |
75 | /* Bit locations inside the mmcra change */ |
76 | unsigned long oprofile_mmcra_sihv; | |
77 | unsigned long oprofile_mmcra_sipr; | |
78 | ||
79 | /* Bits to clear during an oprofile exception */ | |
80 | unsigned long oprofile_mmcra_clear; | |
81 | ||
80f15dc7 PM |
82 | /* Name of processor class, for the ELF AT_PLATFORM entry */ |
83 | char *platform; | |
10b35d99 KG |
84 | }; |
85 | ||
10b35d99 | 86 | extern struct cpu_spec *cur_cpu_spec; |
10b35d99 | 87 | |
9b6b563c PM |
88 | extern void identify_cpu(unsigned long offset, unsigned long cpu); |
89 | extern void do_cpu_ftr_fixups(unsigned long offset); | |
90 | ||
10b35d99 KG |
91 | #endif /* __ASSEMBLY__ */ |
92 | ||
93 | /* CPU kernel features */ | |
94 | ||
95 | /* Retain the 32b definitions all use bottom half of word */ | |
96 | #define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001) | |
97 | #define CPU_FTR_L2CR ASM_CONST(0x0000000000000002) | |
98 | #define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004) | |
99 | #define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008) | |
100 | #define CPU_FTR_TAU ASM_CONST(0x0000000000000010) | |
101 | #define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020) | |
102 | #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) | |
103 | #define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080) | |
104 | #define CPU_FTR_601 ASM_CONST(0x0000000000000100) | |
105 | #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200) | |
106 | #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) | |
107 | #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800) | |
108 | #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000) | |
109 | #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) | |
110 | #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) | |
111 | #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) | |
112 | #define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000) | |
113 | #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) | |
114 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) | |
115 | #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) | |
3d15910b | 116 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) |
fab5db97 PM |
117 | #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) |
118 | #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) | |
10b35d99 | 119 | |
3965f8c5 PM |
120 | /* |
121 | * Add the 64-bit processor unique features in the top half of the word; | |
122 | * on 32-bit, make the names available but defined to be 0. | |
123 | */ | |
10b35d99 | 124 | #ifdef __powerpc64__ |
3965f8c5 | 125 | #define LONG_ASM_CONST(x) ASM_CONST(x) |
10b35d99 | 126 | #else |
3965f8c5 | 127 | #define LONG_ASM_CONST(x) 0 |
10b35d99 KG |
128 | #endif |
129 | ||
3965f8c5 PM |
130 | #define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000) |
131 | #define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000) | |
132 | #define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000) | |
133 | #define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000) | |
134 | #define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000) | |
135 | #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000) | |
136 | #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000) | |
137 | #define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000) | |
138 | #define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000) | |
139 | #define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000) | |
140 | #define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000) | |
141 | #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000) | |
142 | #define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000) | |
143 | ||
10b35d99 KG |
144 | #ifndef __ASSEMBLY__ |
145 | ||
10b35d99 KG |
146 | #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ |
147 | CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ | |
148 | CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL) | |
149 | ||
150 | /* iSeries doesn't support large pages */ | |
151 | #ifdef CONFIG_PPC_ISERIES | |
152 | #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE) | |
153 | #else | |
154 | #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE) | |
155 | #endif /* CONFIG_PPC_ISERIES */ | |
156 | ||
157 | /* We only set the altivec features if the kernel was compiled with altivec | |
158 | * support | |
159 | */ | |
160 | #ifdef CONFIG_ALTIVEC | |
161 | #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC | |
162 | #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC | |
163 | #else | |
164 | #define CPU_FTR_ALTIVEC_COMP 0 | |
165 | #define PPC_FEATURE_HAS_ALTIVEC_COMP 0 | |
166 | #endif | |
167 | ||
168 | /* We need to mark all pages as being coherent if we're SMP or we | |
1775dbbc KG |
169 | * have a 74[45]x and an MPC107 host bridge. Also 83xx requires |
170 | * it for PCI "streaming/prefetch" to work properly. | |
10b35d99 | 171 | */ |
1775dbbc KG |
172 | #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ |
173 | || defined(CONFIG_PPC_83xx) | |
10b35d99 KG |
174 | #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT |
175 | #else | |
176 | #define CPU_FTR_COMMON 0 | |
177 | #endif | |
178 | ||
179 | /* The powersave features NAP & DOZE seems to confuse BDI when | |
180 | debugging. So if a BDI is used, disable theses | |
181 | */ | |
182 | #ifndef CONFIG_BDI_SWITCH | |
183 | #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE | |
184 | #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP | |
185 | #else | |
186 | #define CPU_FTR_MAYBE_CAN_DOZE 0 | |
187 | #define CPU_FTR_MAYBE_CAN_NAP 0 | |
188 | #endif | |
189 | ||
190 | #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \ | |
191 | !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ | |
192 | !defined(CONFIG_BOOKE)) | |
193 | ||
7c92943c SR |
194 | #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE) |
195 | #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | |
196 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ | |
fab5db97 | 197 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
7c92943c | 198 | #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
fab5db97 PM |
199 | CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \ |
200 | CPU_FTR_PPC_LE) | |
7c92943c SR |
201 | #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
202 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | |
fab5db97 | 203 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
7c92943c SR |
204 | #define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
205 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | |
fab5db97 PM |
206 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
207 | CPU_FTR_PPC_LE) | |
7c92943c SR |
208 | #define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
209 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | |
fab5db97 PM |
210 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ |
211 | CPU_FTR_PPC_LE) | |
7c92943c SR |
212 | #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
213 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | |
214 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | |
fab5db97 | 215 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE) |
7c92943c SR |
216 | #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
217 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | |
218 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | |
fab5db97 | 219 | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE) |
7c92943c SR |
220 | #define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
221 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | |
222 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | |
fab5db97 | 223 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) |
7c92943c SR |
224 | #define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ |
225 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \ | |
226 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | |
fab5db97 | 227 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) |
7c92943c SR |
228 | #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
229 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | |
230 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | |
fab5db97 | 231 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
7c92943c SR |
232 | #define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
233 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | |
234 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | |
fab5db97 | 235 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
7c92943c SR |
236 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
237 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
238 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | |
fab5db97 | 239 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
7c92943c SR |
240 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
241 | CPU_FTR_USE_TB | \ | |
242 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
243 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | |
244 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | |
fab5db97 | 245 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
7c92943c SR |
246 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
247 | CPU_FTR_USE_TB | \ | |
248 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
249 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | |
fab5db97 | 250 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
7c92943c SR |
251 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
252 | CPU_FTR_USE_TB | \ | |
253 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ | |
254 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ | |
fab5db97 | 255 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
7c92943c SR |
256 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
257 | CPU_FTR_USE_TB | \ | |
258 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
259 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | |
260 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | |
fab5db97 | 261 | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) |
7c92943c SR |
262 | #define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
263 | CPU_FTR_USE_TB | \ | |
264 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
265 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | |
266 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | |
fab5db97 | 267 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
7c92943c SR |
268 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
269 | CPU_FTR_USE_TB | \ | |
270 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
271 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | |
272 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | |
fab5db97 | 273 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE) |
7c92943c SR |
274 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
275 | CPU_FTR_USE_TB | \ | |
276 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
277 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | |
278 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | |
fab5db97 | 279 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
7c92943c SR |
280 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
281 | CPU_FTR_USE_TB | \ | |
282 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | |
283 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | |
284 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | |
fab5db97 | 285 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
7c92943c SR |
286 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ |
287 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) | |
288 | #define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ | |
289 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS) | |
290 | #define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \ | |
291 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ | |
292 | CPU_FTR_COMMON) | |
293 | #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \ | |
294 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) | |
7c92943c SR |
295 | #define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB) |
296 | #define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | |
297 | CPU_FTR_NODSISRALIGN) | |
298 | #define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | |
299 | CPU_FTR_NODSISRALIGN) | |
300 | #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN) | |
301 | #define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | |
302 | CPU_FTR_NODSISRALIGN) | |
303 | #define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | |
304 | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN) | |
305 | #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) | |
10b35d99 | 306 | #ifdef __powerpc64__ |
7c92943c | 307 | #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
fab5db97 | 308 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE) |
7c92943c SR |
309 | #define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
310 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ | |
311 | CPU_FTR_MMCRA | CPU_FTR_CTRL) | |
312 | #define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | |
313 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA) | |
314 | #define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | |
315 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | |
316 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA) | |
317 | #define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ | |
318 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | |
319 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | |
320 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | |
e78dbc80 | 321 | CPU_FTR_PURR) |
03054d51 AB |
322 | #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
323 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | |
324 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | |
325 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | |
fab5db97 | 326 | CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE) |
7c92943c SR |
327 | #define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
328 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | |
329 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | |
ce221982 | 330 | CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE) |
7c92943c SR |
331 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \ |
332 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) | |
10b35d99 KG |
333 | #endif |
334 | ||
2406f606 | 335 | #ifdef __powerpc64__ |
7c92943c SR |
336 | #define CPU_FTRS_POSSIBLE \ |
337 | (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \ | |
03054d51 AB |
338 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \ |
339 | CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE) | |
2406f606 | 340 | #else |
7c92943c SR |
341 | enum { |
342 | CPU_FTRS_POSSIBLE = | |
10b35d99 KG |
343 | #if CLASSIC_PPC |
344 | CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU | | |
345 | CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 | | |
346 | CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX | | |
347 | CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 | | |
348 | CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 | | |
349 | CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 | | |
350 | CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX | | |
351 | CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 | | |
352 | #else | |
353 | CPU_FTRS_GENERIC_32 | | |
354 | #endif | |
10b35d99 KG |
355 | #ifdef CONFIG_8xx |
356 | CPU_FTRS_8XX | | |
357 | #endif | |
358 | #ifdef CONFIG_40x | |
359 | CPU_FTRS_40X | | |
360 | #endif | |
361 | #ifdef CONFIG_44x | |
362 | CPU_FTRS_44X | | |
363 | #endif | |
364 | #ifdef CONFIG_E200 | |
365 | CPU_FTRS_E200 | | |
366 | #endif | |
367 | #ifdef CONFIG_E500 | |
368 | CPU_FTRS_E500 | CPU_FTRS_E500_2 | | |
369 | #endif | |
10b35d99 | 370 | 0, |
7c92943c SR |
371 | }; |
372 | #endif /* __powerpc64__ */ | |
10b35d99 | 373 | |
2406f606 | 374 | #ifdef __powerpc64__ |
7c92943c SR |
375 | #define CPU_FTRS_ALWAYS \ |
376 | (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \ | |
03054d51 AB |
377 | CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \ |
378 | CPU_FTRS_CELL & CPU_FTRS_POSSIBLE) | |
2406f606 | 379 | #else |
7c92943c SR |
380 | enum { |
381 | CPU_FTRS_ALWAYS = | |
10b35d99 KG |
382 | #if CLASSIC_PPC |
383 | CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU & | |
384 | CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 & | |
385 | CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX & | |
386 | CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 & | |
387 | CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 & | |
388 | CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 & | |
389 | CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX & | |
390 | CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 & | |
391 | #else | |
392 | CPU_FTRS_GENERIC_32 & | |
393 | #endif | |
10b35d99 KG |
394 | #ifdef CONFIG_8xx |
395 | CPU_FTRS_8XX & | |
396 | #endif | |
397 | #ifdef CONFIG_40x | |
398 | CPU_FTRS_40X & | |
399 | #endif | |
400 | #ifdef CONFIG_44x | |
401 | CPU_FTRS_44X & | |
402 | #endif | |
403 | #ifdef CONFIG_E200 | |
404 | CPU_FTRS_E200 & | |
405 | #endif | |
406 | #ifdef CONFIG_E500 | |
407 | CPU_FTRS_E500 & CPU_FTRS_E500_2 & | |
408 | #endif | |
10b35d99 KG |
409 | CPU_FTRS_POSSIBLE, |
410 | }; | |
7c92943c | 411 | #endif /* __powerpc64__ */ |
10b35d99 KG |
412 | |
413 | static inline int cpu_has_feature(unsigned long feature) | |
414 | { | |
415 | return (CPU_FTRS_ALWAYS & feature) || | |
416 | (CPU_FTRS_POSSIBLE | |
10b35d99 | 417 | & cur_cpu_spec->cpu_features |
10b35d99 KG |
418 | & feature); |
419 | } | |
420 | ||
421 | #endif /* !__ASSEMBLY__ */ | |
422 | ||
423 | #ifdef __ASSEMBLY__ | |
424 | ||
425 | #define BEGIN_FTR_SECTION 98: | |
426 | ||
427 | #ifndef __powerpc64__ | |
428 | #define END_FTR_SECTION(msk, val) \ | |
429 | 99: \ | |
430 | .section __ftr_fixup,"a"; \ | |
431 | .align 2; \ | |
432 | .long msk; \ | |
433 | .long val; \ | |
434 | .long 98b; \ | |
435 | .long 99b; \ | |
436 | .previous | |
437 | #else /* __powerpc64__ */ | |
438 | #define END_FTR_SECTION(msk, val) \ | |
439 | 99: \ | |
440 | .section __ftr_fixup,"a"; \ | |
441 | .align 3; \ | |
442 | .llong msk; \ | |
443 | .llong val; \ | |
444 | .llong 98b; \ | |
445 | .llong 99b; \ | |
446 | .previous | |
447 | #endif /* __powerpc64__ */ | |
448 | ||
449 | #define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk)) | |
450 | #define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0) | |
451 | #endif /* __ASSEMBLY__ */ | |
452 | ||
453 | #endif /* __KERNEL__ */ | |
454 | #endif /* __ASM_POWERPC_CPUTABLE_H */ |