[linux-2.6-block.git] / include / asm-powerpc / cputable.h

#ifndef __ASM_POWERPC_CPUTABLE_H
#define __ASM_POWERPC_CPUTABLE_H

#include <asm/asm-compat.h>

#define PPC_FEATURE_32			0x80000000
#define PPC_FEATURE_64			0x40000000
#define PPC_FEATURE_601_INSTR		0x20000000
#define PPC_FEATURE_HAS_ALTIVEC		0x10000000
#define PPC_FEATURE_HAS_FPU		0x08000000
#define PPC_FEATURE_HAS_MMU		0x04000000
#define PPC_FEATURE_HAS_4xxMAC		0x02000000
#define PPC_FEATURE_UNIFIED_CACHE	0x01000000
#define PPC_FEATURE_HAS_SPE		0x00800000
#define PPC_FEATURE_HAS_EFP_SINGLE	0x00400000
#define PPC_FEATURE_HAS_EFP_DOUBLE	0x00200000
#define PPC_FEATURE_NO_TB		0x00100000
#define PPC_FEATURE_POWER4		0x00080000
#define PPC_FEATURE_POWER5		0x00040000
#define PPC_FEATURE_POWER5_PLUS		0x00020000
#define PPC_FEATURE_CELL		0x00010000
#define PPC_FEATURE_BOOKE		0x00008000
#define PPC_FEATURE_SMT			0x00004000
#define PPC_FEATURE_ICACHE_SNOOP	0x00002000

#ifdef __KERNEL__
#ifndef __ASSEMBLY__

/* This structure can grow, it's real size is used by head.S code
 * via the mkdefs mechanism.
 */
struct cpu_spec;

typedef	void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);

enum powerpc_oprofile_type {
	PPC_OPROFILE_INVALID = 0,
	PPC_OPROFILE_RS64 = 1,
	PPC_OPROFILE_POWER4 = 2,
	PPC_OPROFILE_G4 = 3,
	PPC_OPROFILE_BOOKE = 4,
};

struct cpu_spec {
	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
	unsigned int	pvr_mask;
	unsigned int	pvr_value;

	char		*cpu_name;
	unsigned long	cpu_features;		/* Kernel features */
	unsigned int	cpu_user_features;	/* Userland features */

	/* cache line sizes */
	unsigned int	icache_bsize;
	unsigned int	dcache_bsize;

	/* number of performance monitor counters */
	unsigned int	num_pmcs;

	/* this is called to initialize various CPU bits like L1 cache,
	 * BHT, SPD, etc... from head.S before branching to identify_machine
	 */
	cpu_setup_t	cpu_setup;

	/* Used by oprofile userspace to select the right counters */
	char		*oprofile_cpu_type;

	/* Processor specific oprofile operations */
	enum powerpc_oprofile_type oprofile_type;

	/* Name of processor class, for the ELF AT_PLATFORM entry */
	char		*platform;
};

extern struct cpu_spec		*cur_cpu_spec;

extern void identify_cpu(unsigned long offset, unsigned long cpu);
extern void do_cpu_ftr_fixups(unsigned long offset);

#endif /* __ASSEMBLY__ */

/* CPU kernel features */

/* Retain the 32b definitions all use bottom half of word */
#define CPU_FTR_SPLIT_ID_CACHE		ASM_CONST(0x0000000000000001)
#define CPU_FTR_L2CR			ASM_CONST(0x0000000000000002)
#define CPU_FTR_SPEC7450		ASM_CONST(0x0000000000000004)
#define CPU_FTR_ALTIVEC			ASM_CONST(0x0000000000000008)
#define CPU_FTR_TAU			ASM_CONST(0x0000000000000010)
#define CPU_FTR_CAN_DOZE		ASM_CONST(0x0000000000000020)
#define CPU_FTR_USE_TB			ASM_CONST(0x0000000000000040)
#define CPU_FTR_604_PERF_MON		ASM_CONST(0x0000000000000080)
#define CPU_FTR_601			ASM_CONST(0x0000000000000100)
#define CPU_FTR_HPTE_TABLE		ASM_CONST(0x0000000000000200)
#define CPU_FTR_CAN_NAP			ASM_CONST(0x0000000000000400)
#define CPU_FTR_L3CR			ASM_CONST(0x0000000000000800)
#define CPU_FTR_L3_DISABLE_NAP		ASM_CONST(0x0000000000001000)
#define CPU_FTR_NAP_DISABLE_L2_PR	ASM_CONST(0x0000000000002000)
#define CPU_FTR_DUAL_PLL_750FX		ASM_CONST(0x0000000000004000)
#define CPU_FTR_NO_DPM			ASM_CONST(0x0000000000008000)
#define CPU_FTR_HAS_HIGH_BATS		ASM_CONST(0x0000000000010000)
#define CPU_FTR_NEED_COHERENT		ASM_CONST(0x0000000000020000)
#define CPU_FTR_NO_BTIC			ASM_CONST(0x0000000000040000)
#define CPU_FTR_BIG_PHYS		ASM_CONST(0x0000000000080000)
#define CPU_FTR_NODSISRALIGN		ASM_CONST(0x0000000000100000)

#ifdef __powerpc64__
/* Add the 64b processor unique features in the top half of the word */
#define CPU_FTR_SLB			ASM_CONST(0x0000000100000000)
#define CPU_FTR_16M_PAGE		ASM_CONST(0x0000000200000000)
#define CPU_FTR_TLBIEL			ASM_CONST(0x0000000400000000)
#define CPU_FTR_NOEXECUTE		ASM_CONST(0x0000000800000000)
#define CPU_FTR_IABR			ASM_CONST(0x0000002000000000)
#define CPU_FTR_MMCRA			ASM_CONST(0x0000004000000000)
#define CPU_FTR_CTRL			ASM_CONST(0x0000008000000000)
#define CPU_FTR_SMT			ASM_CONST(0x0000010000000000)
#define CPU_FTR_COHERENT_ICACHE		ASM_CONST(0x0000020000000000)
#define CPU_FTR_LOCKLESS_TLBIE		ASM_CONST(0x0000040000000000)
#define CPU_FTR_MMCRA_SIHV		ASM_CONST(0x0000080000000000)
#define CPU_FTR_CI_LARGE_PAGE		ASM_CONST(0x0000100000000000)
#define CPU_FTR_PAUSE_ZERO		ASM_CONST(0x0000200000000000)
#define CPU_FTR_PURR			ASM_CONST(0x0000400000000000)
#else
/* ensure on 32b processors the flags are available for compiling but
 * don't do anything */
#define CPU_FTR_SLB			ASM_CONST(0x0)
#define CPU_FTR_16M_PAGE		ASM_CONST(0x0)
#define CPU_FTR_TLBIEL			ASM_CONST(0x0)
#define CPU_FTR_NOEXECUTE		ASM_CONST(0x0)
#define CPU_FTR_IABR			ASM_CONST(0x0)
#define CPU_FTR_MMCRA			ASM_CONST(0x0)
#define CPU_FTR_CTRL			ASM_CONST(0x0)
#define CPU_FTR_SMT			ASM_CONST(0x0)
#define CPU_FTR_COHERENT_ICACHE		ASM_CONST(0x0)
#define CPU_FTR_LOCKLESS_TLBIE		ASM_CONST(0x0)
#define CPU_FTR_MMCRA_SIHV		ASM_CONST(0x0)
#define CPU_FTR_CI_LARGE_PAGE		ASM_CONST(0x0)
#define CPU_FTR_PURR			ASM_CONST(0x0)
#endif

#ifndef __ASSEMBLY__

#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
					CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
					CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)

/* iSeries doesn't support large pages */
#ifdef CONFIG_PPC_ISERIES
#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_PPCAS_ARCH_V2_BASE)
#else
#define CPU_FTR_PPCAS_ARCH_V2	(CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
#endif /* CONFIG_PPC_ISERIES */

/* We only set the altivec features if the kernel was compiled with altivec
 * support
 */
#ifdef CONFIG_ALTIVEC
#define CPU_FTR_ALTIVEC_COMP	CPU_FTR_ALTIVEC
#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
#else
#define CPU_FTR_ALTIVEC_COMP	0
#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
#endif

/* We need to mark all pages as being coherent if we're SMP or we
 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
 * it for PCI "streaming/prefetch" to work properly.
 */
#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
	|| defined(CONFIG_PPC_83xx)
#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
#else
#define CPU_FTR_COMMON                  0
#endif

/* The powersave features NAP & DOZE seems to confuse BDI when
   debugging. So if a BDI is used, disable theses
 */
#ifndef CONFIG_BDI_SWITCH
#define CPU_FTR_MAYBE_CAN_DOZE	CPU_FTR_CAN_DOZE
#define CPU_FTR_MAYBE_CAN_NAP	CPU_FTR_CAN_NAP
#else
#define CPU_FTR_MAYBE_CAN_DOZE	0
#define CPU_FTR_MAYBE_CAN_NAP	0
#endif

#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
		     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
		     !defined(CONFIG_BOOKE))

#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
#define CPU_FTRS_603	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP)
#define CPU_FTRS_604	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE)
#define CPU_FTRS_740_NOTAU	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
#define CPU_FTRS_740	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
#define CPU_FTRS_750	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
#define CPU_FTRS_750FX1	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
#define CPU_FTRS_750FX2	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_NO_DPM)
#define CPU_FTRS_750FX	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS)
#define CPU_FTRS_750GX	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
	    CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS)
#define CPU_FTRS_7400_NOTAU	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
	    CPU_FTR_MAYBE_CAN_NAP)
#define CPU_FTRS_7400	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
	    CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
	    CPU_FTR_MAYBE_CAN_NAP)
#define CPU_FTRS_7450_20	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NEED_COHERENT)
#define CPU_FTRS_7450_21	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
	    CPU_FTR_NEED_COHERENT)
#define CPU_FTRS_7450_23	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT)
#define CPU_FTRS_7455_1	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_NEED_COHERENT)
#define CPU_FTRS_7455_20	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS)
#define CPU_FTRS_7455	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_NEED_COHERENT)
#define CPU_FTRS_7447_10	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC)
#define CPU_FTRS_7447	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_NEED_COHERENT)
#define CPU_FTRS_7447A	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_NEED_COHERENT)
#define CPU_FTRS_82XX	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
#define CPU_FTRS_G2_LE	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
#define CPU_FTRS_E300	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
	    CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
	    CPU_FTR_COMMON)
#define CPU_FTRS_CLASSIC32	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
#define CPU_FTRS_POWER3_32	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
#define CPU_FTRS_POWER4_32	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_970_32	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
	    CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | \
	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_8XX	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
#define CPU_FTRS_40X	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_44X	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_E200	(CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_E500	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_E500_2	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
#define CPU_FTRS_GENERIC_32	(CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
#ifdef __powerpc64__
#define CPU_FTRS_POWER3	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_IABR)
#define CPU_FTRS_RS64	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
	    CPU_FTR_MMCRA | CPU_FTR_CTRL)
#define CPU_FTRS_POWER4	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA)
#define CPU_FTRS_PPC970	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
#define CPU_FTRS_POWER5	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
	    CPU_FTR_MMCRA | CPU_FTR_SMT | \
	    CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
	    CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR)
#define CPU_FTRS_CELL	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
	    CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
	    CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO)
#define CPU_FTRS_COMPATIBLE	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
	    CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
#endif

#ifdef __powerpc64__
#define CPU_FTRS_POSSIBLE	\
	    (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |	\
	    CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |	\
            CPU_FTR_CI_LARGE_PAGE)
#else
enum {
	CPU_FTRS_POSSIBLE =
#if CLASSIC_PPC
	    CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
	    CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
	    CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
	    CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
	    CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
	    CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
	    CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
	    CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
#else
	    CPU_FTRS_GENERIC_32 |
#endif
#ifdef CONFIG_PPC64BRIDGE
	    CPU_FTRS_POWER3_32 |
#endif
#ifdef CONFIG_POWER4
	    CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
#endif
#ifdef CONFIG_8xx
	    CPU_FTRS_8XX |
#endif
#ifdef CONFIG_40x
	    CPU_FTRS_40X |
#endif
#ifdef CONFIG_44x
	    CPU_FTRS_44X |
#endif
#ifdef CONFIG_E200
	    CPU_FTRS_E200 |
#endif
#ifdef CONFIG_E500
	    CPU_FTRS_E500 | CPU_FTRS_E500_2 |
#endif
	    0,
};
#endif /* __powerpc64__ */

#ifdef __powerpc64__
#define CPU_FTRS_ALWAYS		\
	    (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &	\
	    CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &	\
	    CPU_FTRS_POSSIBLE)
#else
enum {
	CPU_FTRS_ALWAYS =
#if CLASSIC_PPC
	    CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
	    CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
	    CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
	    CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
	    CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
	    CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
	    CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
	    CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
#else
	    CPU_FTRS_GENERIC_32 &
#endif
#ifdef CONFIG_PPC64BRIDGE
	    CPU_FTRS_POWER3_32 &
#endif
#ifdef CONFIG_POWER4
	    CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
#endif
#ifdef CONFIG_8xx
	    CPU_FTRS_8XX &
#endif
#ifdef CONFIG_40x
	    CPU_FTRS_40X &
#endif
#ifdef CONFIG_44x
	    CPU_FTRS_44X &
#endif
#ifdef CONFIG_E200
	    CPU_FTRS_E200 &
#endif
#ifdef CONFIG_E500
	    CPU_FTRS_E500 & CPU_FTRS_E500_2 &
#endif
	    CPU_FTRS_POSSIBLE,
};
#endif /* __powerpc64__ */

static inline int cpu_has_feature(unsigned long feature)
{
	return (CPU_FTRS_ALWAYS & feature) ||
	       (CPU_FTRS_POSSIBLE
		& cur_cpu_spec->cpu_features
		& feature);
}

#endif /* !__ASSEMBLY__ */

#ifdef __ASSEMBLY__

#define BEGIN_FTR_SECTION		98:

#ifndef __powerpc64__
#define END_FTR_SECTION(msk, val)		\
99:						\
	.section __ftr_fixup,"a";		\
	.align 2;				\
	.long msk;				\
	.long val;				\
	.long 98b;				\
	.long 99b;				\
	.previous
#else /* __powerpc64__ */
#define END_FTR_SECTION(msk, val)		\
99:						\
	.section __ftr_fixup,"a";		\
	.align 3;				\
	.llong msk;				\
	.llong val;				\
	.llong 98b;				\
	.llong 99b;	 			\
	.previous
#endif /* __powerpc64__ */

#define END_FTR_SECTION_IFSET(msk)	END_FTR_SECTION((msk), (msk))
#define END_FTR_SECTION_IFCLR(msk)	END_FTR_SECTION((msk), 0)
#endif /* __ASSEMBLY__ */

#endif /* __KERNEL__ */
#endif /* __ASM_POWERPC_CPUTABLE_H */
Commit	Line	Data
10b35d99 KG	1	#ifndef __ASM_POWERPC_CPUTABLE_H
	2	#define __ASM_POWERPC_CPUTABLE_H
	3
3ddfbcf1	4	#include <asm/asm-compat.h>
10b35d99 KG	5
	6	#define PPC_FEATURE_32 0x80000000
	7	#define PPC_FEATURE_64 0x40000000
	8	#define PPC_FEATURE_601_INSTR 0x20000000
	9	#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
	10	#define PPC_FEATURE_HAS_FPU 0x08000000
	11	#define PPC_FEATURE_HAS_MMU 0x04000000
	12	#define PPC_FEATURE_HAS_4xxMAC 0x02000000
	13	#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
	14	#define PPC_FEATURE_HAS_SPE 0x00800000
	15	#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
	16	#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
98599013	17	#define PPC_FEATURE_NO_TB 0x00100000
a7ddc5e8 PM	18	#define PPC_FEATURE_POWER4 0x00080000
	19	#define PPC_FEATURE_POWER5 0x00040000
	20	#define PPC_FEATURE_POWER5_PLUS 0x00020000
	21	#define PPC_FEATURE_CELL 0x00010000
80f15dc7	22	#define PPC_FEATURE_BOOKE 0x00008000
aa5cb021 BH	23	#define PPC_FEATURE_SMT 0x00004000
aa5cb021 BH	24	#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
10b35d99 KG	25
	26	#ifdef __KERNEL__
	27	#ifndef __ASSEMBLY__
	28
	29	/* This structure can grow, it's real size is used by head.S code
	30	* via the mkdefs mechanism.
	31	*/
	32	struct cpu_spec;
10b35d99	33
10b35d99	34	typedef void (cpu_setup_t)(unsigned long offset, struct cpu_spec spec);
10b35d99	35
32a33994	36	enum powerpc_oprofile_type {
7a45fb19 AW	37	PPC_OPROFILE_INVALID = 0,
	38	PPC_OPROFILE_RS64 = 1,
	39	PPC_OPROFILE_POWER4 = 2,
	40	PPC_OPROFILE_G4 = 3,
	41	PPC_OPROFILE_BOOKE = 4,
32a33994 AB	42	};
32a33994 AB	43
10b35d99 KG	44	struct cpu_spec {
	45	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
	46	unsigned int pvr_mask;
	47	unsigned int pvr_value;
	48
	49	char *cpu_name;
	50	unsigned long cpu_features; /* Kernel features */
	51	unsigned int cpu_user_features; /* Userland features */
	52
	53	/* cache line sizes */
	54	unsigned int icache_bsize;
	55	unsigned int dcache_bsize;
	56
	57	/* number of performance monitor counters */
	58	unsigned int num_pmcs;
	59
	60	/* this is called to initialize various CPU bits like L1 cache,
	61	* BHT, SPD, etc... from head.S before branching to identify_machine
	62	*/
	63	cpu_setup_t cpu_setup;
10b35d99 KG	64
	65	/* Used by oprofile userspace to select the right counters */
	66	char *oprofile_cpu_type;
	67
	68	/* Processor specific oprofile operations */
32a33994	69	enum powerpc_oprofile_type oprofile_type;
80f15dc7 PM	70
	71	/* Name of processor class, for the ELF AT_PLATFORM entry */
	72	char *platform;
10b35d99 KG	73	};
10b35d99 KG	74
10b35d99	75	extern struct cpu_spec *cur_cpu_spec;
10b35d99	76
9b6b563c PM	77	extern void identify_cpu(unsigned long offset, unsigned long cpu);
	78	extern void do_cpu_ftr_fixups(unsigned long offset);
	79
10b35d99 KG	80	#endif /* __ASSEMBLY__ */
	81
	82	/* CPU kernel features */
	83
	84	/* Retain the 32b definitions all use bottom half of word */
	85	#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
	86	#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
	87	#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
	88	#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
	89	#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
	90	#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
	91	#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
	92	#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
	93	#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
	94	#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
	95	#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
	96	#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
	97	#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
	98	#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
	99	#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
	100	#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
	101	#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
	102	#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
	103	#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
	104	#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
3d15910b	105	#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
10b35d99 KG	106
	107	#ifdef __powerpc64__
	108	/* Add the 64b processor unique features in the top half of the word */
3d15910b ME	109	#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
	110	#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
	111	#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
	112	#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
	113	#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
	114	#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
10b35d99	115	#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
3d15910b ME	116	#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
3d15910b ME	117	#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
10b35d99 KG	118	#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
10b35d99 KG	119	#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
3c726f8d	120	#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
c902be71	121	#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
c6622f63	122	#define CPU_FTR_PURR ASM_CONST(0x0000400000000000)
10b35d99 KG	123	#else
	124	/* ensure on 32b processors the flags are available for compiling but
	125	* don't do anything */
3d15910b ME	126	#define CPU_FTR_SLB ASM_CONST(0x0)
	127	#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
	128	#define CPU_FTR_TLBIEL ASM_CONST(0x0)
	129	#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
	130	#define CPU_FTR_IABR ASM_CONST(0x0)
	131	#define CPU_FTR_MMCRA ASM_CONST(0x0)
10b35d99	132	#define CPU_FTR_CTRL ASM_CONST(0x0)
3d15910b ME	133	#define CPU_FTR_SMT ASM_CONST(0x0)
3d15910b ME	134	#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
10b35d99 KG	135	#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
10b35d99 KG	136	#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
3c726f8d	137	#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
c6622f63	138	#define CPU_FTR_PURR ASM_CONST(0x0)
10b35d99 KG	139	#endif
	140
	141	#ifndef __ASSEMBLY__
	142
10b35d99 KG	143	#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB \| \
	144	CPU_FTR_TLBIEL \| CPU_FTR_NOEXECUTE \| \
	145	CPU_FTR_NODSISRALIGN \| CPU_FTR_CTRL)
	146
	147	/* iSeries doesn't support large pages */
	148	#ifdef CONFIG_PPC_ISERIES
	149	#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
	150	#else
	151	#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE \| CPU_FTR_16M_PAGE)
	152	#endif /* CONFIG_PPC_ISERIES */
	153
	154	/* We only set the altivec features if the kernel was compiled with altivec
	155	* support
	156	*/
	157	#ifdef CONFIG_ALTIVEC
	158	#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
	159	#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
	160	#else
	161	#define CPU_FTR_ALTIVEC_COMP 0
	162	#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
	163	#endif
	164
	165	/* We need to mark all pages as being coherent if we're SMP or we
1775dbbc KG	166	* have a 74[45]x and an MPC107 host bridge. Also 83xx requires
1775dbbc KG	167	* it for PCI "streaming/prefetch" to work properly.
10b35d99	168	*/
1775dbbc KG	169	#if defined(CONFIG_SMP) \|\| defined(CONFIG_MPC10X_BRIDGE) \
1775dbbc KG	170	\|\| defined(CONFIG_PPC_83xx)
10b35d99 KG	171	#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
	172	#else
	173	#define CPU_FTR_COMMON 0
	174	#endif
	175
	176	/* The powersave features NAP & DOZE seems to confuse BDI when
	177	debugging. So if a BDI is used, disable theses
	178	*/
	179	#ifndef CONFIG_BDI_SWITCH
	180	#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
	181	#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
	182	#else
	183	#define CPU_FTR_MAYBE_CAN_DOZE 0
	184	#define CPU_FTR_MAYBE_CAN_NAP 0
	185	#endif
	186
	187	#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
	188	!defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
	189	!defined(CONFIG_BOOKE))
	190
7c92943c SR	191	#define CPU_FTRS_PPC601 (CPU_FTR_COMMON \| CPU_FTR_601 \| CPU_FTR_HPTE_TABLE)
	192	#define CPU_FTRS_603 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	193	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
	194	CPU_FTR_MAYBE_CAN_NAP)
	195	#define CPU_FTRS_604 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	196	CPU_FTR_USE_TB \| CPU_FTR_604_PERF_MON \| CPU_FTR_HPTE_TABLE)
	197	#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	198	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	199	CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP)
	200	#define CPU_FTRS_740 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	201	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	202	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP)
	203	#define CPU_FTRS_750 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	204	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	205	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP)
	206	#define CPU_FTRS_750FX1 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	207	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	208	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
	209	CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_NO_DPM)
	210	#define CPU_FTRS_750FX2 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	211	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	212	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
	213	CPU_FTR_NO_DPM)
	214	#define CPU_FTRS_750FX (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	215	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	216	CPU_FTR_TAU \| CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
	217	CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_HAS_HIGH_BATS)
	218	#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_MAYBE_CAN_DOZE \| \
	219	CPU_FTR_USE_TB \| CPU_FTR_L2CR \| CPU_FTR_TAU \| \
	220	CPU_FTR_HPTE_TABLE \| CPU_FTR_MAYBE_CAN_NAP \| \
	221	CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_HAS_HIGH_BATS)
	222	#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	223	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	224	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_HPTE_TABLE \| \
	225	CPU_FTR_MAYBE_CAN_NAP)
	226	#define CPU_FTRS_7400 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	227	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
	228	CPU_FTR_TAU \| CPU_FTR_ALTIVEC_COMP \| CPU_FTR_HPTE_TABLE \| \
	229	CPU_FTR_MAYBE_CAN_NAP)
	230	#define CPU_FTRS_7450_20 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	231	CPU_FTR_USE_TB \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	232	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
	233	CPU_FTR_NEED_COHERENT)
	234	#define CPU_FTRS_7450_21 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	235	CPU_FTR_USE_TB \| \
	236	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	237	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
	238	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
	239	CPU_FTR_NEED_COHERENT)
	240	#define CPU_FTRS_7450_23 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	241	CPU_FTR_USE_TB \| \
	242	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	243	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
	244	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_NEED_COHERENT)
	245	#define CPU_FTRS_7455_1 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	246	CPU_FTR_USE_TB \| \
	247	CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| CPU_FTR_L3CR \| \
	248	CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| CPU_FTR_HAS_HIGH_BATS \| \
	249	CPU_FTR_NEED_COHERENT)
	250	#define CPU_FTRS_7455_20 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
	251	CPU_FTR_USE_TB \| \
	252	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
	253	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
	254	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
255	CPU_FTR_NEED_COHERENT \| CPU_FTR_HAS_HIGH_BATS)
256	#define CPU_FTRS_7455 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
257	CPU_FTR_USE_TB \| \
258	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
259	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
260	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
261	CPU_FTR_NEED_COHERENT)
262	#define CPU_FTRS_7447_10 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
263	CPU_FTR_USE_TB \| \
264	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
265	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
266	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
267	CPU_FTR_NEED_COHERENT \| CPU_FTR_NO_BTIC)
268	#define CPU_FTRS_7447 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
269	CPU_FTR_USE_TB \| \
270	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
271	CPU_FTR_L3CR \| CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
272	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
273	CPU_FTR_NEED_COHERENT)
274	#define CPU_FTRS_7447A (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
275	CPU_FTR_USE_TB \| \
276	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
277	CPU_FTR_HPTE_TABLE \| CPU_FTR_SPEC7450 \| \
278	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_HAS_HIGH_BATS \| \
279	CPU_FTR_NEED_COHERENT)
280	#define CPU_FTRS_82XX (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
281	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB)
282	#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_MAYBE_CAN_DOZE \| \
283	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_HAS_HIGH_BATS)
284	#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_MAYBE_CAN_DOZE \| \
285	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_HAS_HIGH_BATS \| \
286	CPU_FTR_COMMON)
287	#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
288	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE)
289	#define CPU_FTRS_POWER3_32 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
290	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE)
291	#define CPU_FTRS_POWER4_32 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
292	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_NODSISRALIGN)
293	#define CPU_FTRS_970_32 (CPU_FTR_COMMON \| CPU_FTR_SPLIT_ID_CACHE \| \
294	CPU_FTR_USE_TB \| CPU_FTR_HPTE_TABLE \| CPU_FTR_ALTIVEC_COMP \| \
295	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_NODSISRALIGN)
296	#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB)
297	#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
298	CPU_FTR_NODSISRALIGN)
299	#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
300	CPU_FTR_NODSISRALIGN)
301	#define CPU_FTRS_E200 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN)
302	#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
303	CPU_FTR_NODSISRALIGN)
304	#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
305	CPU_FTR_BIG_PHYS \| CPU_FTR_NODSISRALIGN)
306	#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON \| CPU_FTR_NODSISRALIGN)
10b35d99	307	#ifdef __powerpc64__
7c92943c SR	308	#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	309	CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR)
	310	#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	311	CPU_FTR_HPTE_TABLE \| CPU_FTR_IABR \| \
	312	CPU_FTR_MMCRA \| CPU_FTR_CTRL)
	313	#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	314	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_MMCRA)
	315	#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	316	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| \
	317	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_CAN_NAP \| CPU_FTR_MMCRA)
	318	#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	319	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| \
	320	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
	321	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_LOCKLESS_TLBIE \| \
	322	CPU_FTR_MMCRA_SIHV \| CPU_FTR_PURR)
	323	#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	324	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2 \| \
	325	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
	326	CPU_FTR_CTRL \| CPU_FTR_PAUSE_ZERO)
	327	#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE \| CPU_FTR_USE_TB \| \
	328	CPU_FTR_HPTE_TABLE \| CPU_FTR_PPCAS_ARCH_V2)
10b35d99 KG	329	#endif
10b35d99 KG	330
2406f606	331	#ifdef __powerpc64__
7c92943c SR	332	#define CPU_FTRS_POSSIBLE \
	333	(CPU_FTRS_POWER3 \| CPU_FTRS_RS64 \| CPU_FTRS_POWER4 \| \
	334	CPU_FTRS_PPC970 \| CPU_FTRS_POWER5 \| CPU_FTRS_CELL \| \
	335	CPU_FTR_CI_LARGE_PAGE)
2406f606	336	#else
7c92943c SR	337	enum {
7c92943c SR	338	CPU_FTRS_POSSIBLE =
10b35d99 KG	339	#if CLASSIC_PPC
	340	CPU_FTRS_PPC601 \| CPU_FTRS_603 \| CPU_FTRS_604 \| CPU_FTRS_740_NOTAU \|
	341	CPU_FTRS_740 \| CPU_FTRS_750 \| CPU_FTRS_750FX1 \|
	342	CPU_FTRS_750FX2 \| CPU_FTRS_750FX \| CPU_FTRS_750GX \|
	343	CPU_FTRS_7400_NOTAU \| CPU_FTRS_7400 \| CPU_FTRS_7450_20 \|
	344	CPU_FTRS_7450_21 \| CPU_FTRS_7450_23 \| CPU_FTRS_7455_1 \|
	345	CPU_FTRS_7455_20 \| CPU_FTRS_7455 \| CPU_FTRS_7447_10 \|
	346	CPU_FTRS_7447 \| CPU_FTRS_7447A \| CPU_FTRS_82XX \|
	347	CPU_FTRS_G2_LE \| CPU_FTRS_E300 \| CPU_FTRS_CLASSIC32 \|
	348	#else
	349	CPU_FTRS_GENERIC_32 \|
	350	#endif
	351	#ifdef CONFIG_PPC64BRIDGE
	352	CPU_FTRS_POWER3_32 \|
	353	#endif
	354	#ifdef CONFIG_POWER4
	355	CPU_FTRS_POWER4_32 \| CPU_FTRS_970_32 \|
	356	#endif
	357	#ifdef CONFIG_8xx
	358	CPU_FTRS_8XX \|
	359	#endif
	360	#ifdef CONFIG_40x
	361	CPU_FTRS_40X \|
	362	#endif
	363	#ifdef CONFIG_44x
	364	CPU_FTRS_44X \|
	365	#endif
	366	#ifdef CONFIG_E200
	367	CPU_FTRS_E200 \|
	368	#endif
	369	#ifdef CONFIG_E500
	370	CPU_FTRS_E500 \| CPU_FTRS_E500_2 \|
	371	#endif
10b35d99	372	0,
7c92943c SR	373	};
7c92943c SR	374	#endif /* __powerpc64__ */
10b35d99	375
2406f606	376	#ifdef __powerpc64__
7c92943c SR	377	#define CPU_FTRS_ALWAYS \
	378	(CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
	379	CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL & \
	380	CPU_FTRS_POSSIBLE)
2406f606	381	#else
7c92943c SR	382	enum {
7c92943c SR	383	CPU_FTRS_ALWAYS =
10b35d99 KG	384	#if CLASSIC_PPC
	385	CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
	386	CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
	387	CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
	388	CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
	389	CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
	390	CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
	391	CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
	392	CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
	393	#else
	394	CPU_FTRS_GENERIC_32 &
	395	#endif
	396	#ifdef CONFIG_PPC64BRIDGE
	397	CPU_FTRS_POWER3_32 &
	398	#endif
	399	#ifdef CONFIG_POWER4
	400	CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
	401	#endif
	402	#ifdef CONFIG_8xx
	403	CPU_FTRS_8XX &
	404	#endif
	405	#ifdef CONFIG_40x
	406	CPU_FTRS_40X &
	407	#endif
	408	#ifdef CONFIG_44x
	409	CPU_FTRS_44X &
	410	#endif
	411	#ifdef CONFIG_E200
	412	CPU_FTRS_E200 &
	413	#endif
	414	#ifdef CONFIG_E500
	415	CPU_FTRS_E500 & CPU_FTRS_E500_2 &
	416	#endif
10b35d99 KG	417	CPU_FTRS_POSSIBLE,
10b35d99 KG	418	};
7c92943c	419	#endif /* __powerpc64__ */
10b35d99 KG	420
	421	static inline int cpu_has_feature(unsigned long feature)
	422	{
	423	return (CPU_FTRS_ALWAYS & feature) \|\|
	424	(CPU_FTRS_POSSIBLE
10b35d99	425	& cur_cpu_spec->cpu_features
10b35d99 KG	426	& feature);
	427	}
	428
	429	#endif /* !__ASSEMBLY__ */
	430
	431	#ifdef __ASSEMBLY__
	432
	433	#define BEGIN_FTR_SECTION 98:
	434
	435	#ifndef __powerpc64__
	436	#define END_FTR_SECTION(msk, val) \
	437	99: \
	438	.section __ftr_fixup,"a"; \
	439	.align 2; \
	440	.long msk; \
	441	.long val; \
	442	.long 98b; \
	443	.long 99b; \
	444	.previous
	445	#else /* __powerpc64__ */
	446	#define END_FTR_SECTION(msk, val) \
	447	99: \
	448	.section __ftr_fixup,"a"; \
	449	.align 3; \
	450	.llong msk; \
	451	.llong val; \
	452	.llong 98b; \
	453	.llong 99b; \
	454	.previous
	455	#endif /* __powerpc64__ */
	456
	457	#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
	458	#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
	459	#endif /* __ASSEMBLY__ */
	460
	461	#endif /* __KERNEL__ */
	462	#endif /* __ASM_POWERPC_CPUTABLE_H */