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[POWERPC] Support nested cpu feature sections
[linux-2.6-block.git] / include / asm-powerpc / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
3ddfbcf1 4#include <asm/asm-compat.h>
10b35d99
KG		 5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
98599013 17#define PPC_FEATURE_NO_TB 0x00100000
a7ddc5e8
PM		 18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
80f15dc7 22#define PPC_FEATURE_BOOKE 0x00008000
aa5cb021
BH		 23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
03054d51 25#define PPC_FEATURE_ARCH_2_05 0x00001000
b3ebd1d8 26#define PPC_FEATURE_PA6T 0x00000800
10b35d99 27
fab5db97
PM		 28#define PPC_FEATURE_TRUE_LE 0x00000002
29#define PPC_FEATURE_PPC_LE 0x00000001
30
10b35d99
KG		 31#ifdef __KERNEL__
32#ifndef __ASSEMBLY__
33
34/* This structure can grow, it's real size is used by head.S code
35 * via the mkdefs mechanism.
36 */
37struct cpu_spec;
10b35d99 38
10b35d99 39typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 40typedef void (*cpu_restore_t)(void);
10b35d99 41
32a33994 42enum powerpc_oprofile_type {
7a45fb19
AW		 43 PPC_OPROFILE_INVALID = 0,
44 PPC_OPROFILE_RS64 = 1,
45 PPC_OPROFILE_POWER4 = 2,
46 PPC_OPROFILE_G4 = 3,
47 PPC_OPROFILE_BOOKE = 4,
32a33994
AB		 48};
49
10b35d99
KG		 50struct cpu_spec {
51 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
52 unsigned int pvr_mask;
53 unsigned int pvr_value;
54
55 char *cpu_name;
56 unsigned long cpu_features; /* Kernel features */
57 unsigned int cpu_user_features; /* Userland features */
58
59 /* cache line sizes */
60 unsigned int icache_bsize;
61 unsigned int dcache_bsize;
62
63 /* number of performance monitor counters */
64 unsigned int num_pmcs;
65
66 /* this is called to initialize various CPU bits like L1 cache,
67 * BHT, SPD, etc... from head.S before branching to identify_machine
68 */
69 cpu_setup_t cpu_setup;
f39b7a55
OJ		 70 /* Used to restore cpu setup on secondary processors and at resume */
71 cpu_restore_t cpu_restore;
10b35d99
KG		 72
73 /* Used by oprofile userspace to select the right counters */
74 char *oprofile_cpu_type;
75
76 /* Processor specific oprofile operations */
32a33994 77 enum powerpc_oprofile_type oprofile_type;
80f15dc7 78
e78dbc80
MN		 79 /* Bit locations inside the mmcra change */
80 unsigned long oprofile_mmcra_sihv;
81 unsigned long oprofile_mmcra_sipr;
82
83 /* Bits to clear during an oprofile exception */
84 unsigned long oprofile_mmcra_clear;
85
80f15dc7
PM		 86 /* Name of processor class, for the ELF AT_PLATFORM entry */
87 char *platform;
10b35d99
KG		 88};
89
10b35d99 90extern struct cpu_spec *cur_cpu_spec;
10b35d99 91
42c4aaad
BH		 92extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
93
94extern struct cpu_spec *identify_cpu(unsigned long offset);
95extern void do_feature_fixups(unsigned long offset, unsigned long value,
96 void *fixup_start, void *fixup_end);
9b6b563c 97
10b35d99
KG		 98#endif /* __ASSEMBLY__ */
99
100/* CPU kernel features */
101
102/* Retain the 32b definitions all use bottom half of word */
103#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
104#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
105#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
106#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
107#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
108#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
109#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
110#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
111#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
112#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
113#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
114#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
115#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
116#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
117#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
118#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
119#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
120#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
121#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
122#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
3d15910b 123#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
fab5db97
PM		 124#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
125#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
10b35d99 126
3965f8c5
PM		 127/*
128 * Add the 64-bit processor unique features in the top half of the word;
129 * on 32-bit, make the names available but defined to be 0.
130 */
10b35d99 131#ifdef __powerpc64__
3965f8c5 132#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 133#else
3965f8c5 134#define LONG_ASM_CONST(x) 0
10b35d99
KG		 135#endif
136
3965f8c5
PM		 137#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
138#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
139#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
140#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
141#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
142#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
143#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
144#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
145#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
146#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
147#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
148#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
149#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
150
10b35d99
KG		 151#ifndef __ASSEMBLY__
152
10b35d99
KG		 153#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
154 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
00243000 155 CPU_FTR_NODSISRALIGN)
10b35d99
KG		 156
157/* iSeries doesn't support large pages */
158#ifdef CONFIG_PPC_ISERIES
159#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
160#else
161#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
162#endif /* CONFIG_PPC_ISERIES */
163
164/* We only set the altivec features if the kernel was compiled with altivec
165 * support
166 */
167#ifdef CONFIG_ALTIVEC
168#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
169#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
170#else
171#define CPU_FTR_ALTIVEC_COMP 0
172#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
173#endif
174
175/* We need to mark all pages as being coherent if we're SMP or we
1775dbbc
KG		 176 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
177 * it for PCI "streaming/prefetch" to work properly.
10b35d99 178 */
1775dbbc
KG		 179#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
180 || defined(CONFIG_PPC_83xx)
10b35d99
KG		 181#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
182#else
183#define CPU_FTR_COMMON 0
184#endif
185
186/* The powersave features NAP & DOZE seems to confuse BDI when
187 debugging. So if a BDI is used, disable theses
188 */
189#ifndef CONFIG_BDI_SWITCH
190#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
191#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
192#else
193#define CPU_FTR_MAYBE_CAN_DOZE 0
194#define CPU_FTR_MAYBE_CAN_NAP 0
195#endif
196
197#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
198 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
199 !defined(CONFIG_BOOKE))
200
7c92943c
SR		 201#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
202#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
203 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 204 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
7c92943c 205#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
fab5db97
PM		 206 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
207 CPU_FTR_PPC_LE)
7c92943c
SR		 208#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
209 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97 210 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
7c92943c
SR		 211#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
212 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 213 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
214 CPU_FTR_PPC_LE)
7c92943c
SR		 215#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
216 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 217 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
218 CPU_FTR_PPC_LE)
7c92943c
SR		 219#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
220 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
221 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 222 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
7c92943c
SR		 223#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
224 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
225 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 226 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
7c92943c
SR		 227#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
228 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
229 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 230 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
7c92943c
SR		 231#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
232 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
233 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 234 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
7c92943c
SR		 235#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
236 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
237 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 238 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
7c92943c
SR		 239#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
240 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
241 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 242 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
7c92943c
SR		 243#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
244 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
245 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
fab5db97 246 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 247#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
248 CPU_FTR_USE_TB | \
249 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
250 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
251 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
fab5db97 252 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 253#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
254 CPU_FTR_USE_TB | \
255 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
256 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
fab5db97 257 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 258#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
259 CPU_FTR_USE_TB | \
260 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
261 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 262 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 263#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
264 CPU_FTR_USE_TB | \
265 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
266 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
267 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
fab5db97 268 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
7c92943c
SR		 269#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
270 CPU_FTR_USE_TB | \
271 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
272 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
273 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 274 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 275#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
276 CPU_FTR_USE_TB | \
277 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
278 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
279 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 280 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
7c92943c
SR		 281#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
282 CPU_FTR_USE_TB | \
283 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
284 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
285 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 286 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 287#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
288 CPU_FTR_USE_TB | \
289 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
290 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
291 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 292 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
7c92943c
SR		 293#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
294 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
295#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
296 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
297#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
298 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
299 CPU_FTR_COMMON)
300#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
301 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
7c92943c
SR		 302#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
303#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
304 CPU_FTR_NODSISRALIGN)
305#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
306 CPU_FTR_NODSISRALIGN)
307#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
308#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
309 CPU_FTR_NODSISRALIGN)
310#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
311 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
312#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
10b35d99 313#ifdef __powerpc64__
7c92943c 314#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
fab5db97 315 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
7c92943c
SR		 316#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
317 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
318 CPU_FTR_MMCRA | CPU_FTR_CTRL)
319#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
00243000
OJ		 320 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
321 CPU_FTR_MMCRA)
7c92943c 322#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
00243000 323 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c
SR		 324 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
325#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
00243000 326 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c
SR		 327 CPU_FTR_MMCRA | CPU_FTR_SMT | \
328 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
e78dbc80 329 CPU_FTR_PURR)
03054d51 330#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
00243000 331 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51
AB		 332 CPU_FTR_MMCRA | CPU_FTR_SMT | \
333 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
fab5db97 334 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
7c92943c 335#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
00243000 336 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 337 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
00243000 338 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)
b3ebd1d8
OJ		 339#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
340 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
341 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
342 CPU_FTR_PURR | CPU_FTR_REAL_LE)
7c92943c
SR		 343#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
344 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
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KG		 345#endif
346
2406f606 347#ifdef __powerpc64__
7c92943c
SR		 348#define CPU_FTRS_POSSIBLE \
349 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
03054d51 350 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
b3ebd1d8 351 CPU_FTRS_CELL | CPU_FTRS_PA6T)
2406f606 352#else
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SR		 353enum {
354 CPU_FTRS_POSSIBLE =
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KG		 355#if CLASSIC_PPC
356 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
357 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
358 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
359 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
360 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
361 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
362 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
363 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
364#else
365 CPU_FTRS_GENERIC_32 |
366#endif
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KG		 367#ifdef CONFIG_8xx
368 CPU_FTRS_8XX |
369#endif
370#ifdef CONFIG_40x
371 CPU_FTRS_40X |
372#endif
373#ifdef CONFIG_44x
374 CPU_FTRS_44X |
375#endif
376#ifdef CONFIG_E200
377 CPU_FTRS_E200 |
378#endif
379#ifdef CONFIG_E500
380 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
381#endif
10b35d99 382 0,
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SR		 383};
384#endif /* __powerpc64__ */
10b35d99 385
2406f606 386#ifdef __powerpc64__
7c92943c
SR		 387#define CPU_FTRS_ALWAYS \
388 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51 389 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
b3ebd1d8 390 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
2406f606 391#else
7c92943c
SR		 392enum {
393 CPU_FTRS_ALWAYS =
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KG		 394#if CLASSIC_PPC
395 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
396 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
397 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
398 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
399 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
400 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
401 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
402 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
403#else
404 CPU_FTRS_GENERIC_32 &
405#endif
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KG		 406#ifdef CONFIG_8xx
407 CPU_FTRS_8XX &
408#endif
409#ifdef CONFIG_40x
410 CPU_FTRS_40X &
411#endif
412#ifdef CONFIG_44x
413 CPU_FTRS_44X &
414#endif
415#ifdef CONFIG_E200
416 CPU_FTRS_E200 &
417#endif
418#ifdef CONFIG_E500
419 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
420#endif
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KG		 421 CPU_FTRS_POSSIBLE,
422};
7c92943c 423#endif /* __powerpc64__ */
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KG		 424
425static inline int cpu_has_feature(unsigned long feature)
426{
427 return (CPU_FTRS_ALWAYS & feature) ||
428 (CPU_FTRS_POSSIBLE
10b35d99 429 & cur_cpu_spec->cpu_features
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KG		 430 & feature);
431}
432
433#endif /* !__ASSEMBLY__ */
434
435#ifdef __ASSEMBLY__
436
7aeb7324
BH		 437#define BEGIN_FTR_SECTION_NESTED(label) label:
438#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(98)
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KG		 439
440#ifndef __powerpc64__
7aeb7324 441#define END_FTR_SECTION_NESTED(msk, val, label) \
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KG		 44299: \
443 .section __ftr_fixup,"a"; \
444 .align 2; \
445 .long msk; \
446 .long val; \
7aeb7324 447 .long label##b; \
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KG		 448 .long 99b; \
449 .previous
450#else /* __powerpc64__ */
7aeb7324 451#define END_FTR_SECTION_NESTED(msk, val, label) \
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KG		 45299: \
453 .section __ftr_fixup,"a"; \
454 .align 3; \
455 .llong msk; \
456 .llong val; \
7aeb7324 457 .llong label##b; \
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KG		 458 .llong 99b; \
459 .previous
460#endif /* __powerpc64__ */
461
7aeb7324
BH		 462#define END_FTR_SECTION(msk, val) \
463 END_FTR_SECTION_NESTED(msk, val, 98)
464
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KG		 465#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
466#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
467#endif /* __ASSEMBLY__ */
468
469#endif /* __KERNEL__ */
470#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)