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powerpc/iommu/ioda2: Enable compile with IOV=on and IOMMU_API=off
[linux-2.6-block.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
d1cdcf22
AB		 4
5#include <asm/asm-compat.h>
c5157e58 6#include <asm/feature-fixups.h>
c3617f72 7#include <uapi/asm/cputable.h>
d1cdcf22 8
10b35d99
KG		 9#ifndef __ASSEMBLY__
10
11/* This structure can grow, it's real size is used by head.S code
12 * via the mkdefs mechanism.
13 */
14struct cpu_spec;
10b35d99 15
10b35d99 16typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 17typedef void (*cpu_restore_t)(void);
10b35d99 18
32a33994 19enum powerpc_oprofile_type {
7a45fb19
AW		 20 PPC_OPROFILE_INVALID = 0,
21 PPC_OPROFILE_RS64 = 1,
22 PPC_OPROFILE_POWER4 = 2,
23 PPC_OPROFILE_G4 = 3,
39aef685 24 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 25 PPC_OPROFILE_CELL = 5,
25fc530e 26 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 27};
28
1bd2e5ae
OJ		 29enum powerpc_pmc_type {
30 PPC_PMC_DEFAULT = 0,
31 PPC_PMC_IBM = 1,
32 PPC_PMC_PA6T = 2,
b950bdd0 33 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 34};
35
47c0bd1a
BH		 36struct pt_regs;
37
38extern int machine_check_generic(struct pt_regs *regs);
39extern int machine_check_4xx(struct pt_regs *regs);
40extern int machine_check_440A(struct pt_regs *regs);
fe04b112 41extern int machine_check_e500mc(struct pt_regs *regs);
47c0bd1a
BH		 42extern int machine_check_e500(struct pt_regs *regs);
43extern int machine_check_e200(struct pt_regs *regs);
fc5e7097 44extern int machine_check_47x(struct pt_regs *regs);
47c0bd1a 45
87a72f9e 46/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 47struct cpu_spec {
48 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
49 unsigned int pvr_mask;
50 unsigned int pvr_value;
51
52 char *cpu_name;
53 unsigned long cpu_features; /* Kernel features */
54 unsigned int cpu_user_features; /* Userland features */
2171364d 55 unsigned int cpu_user_features2; /* Userland features v2 */
7c03d653 56 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 57
58 /* cache line sizes */
59 unsigned int icache_bsize;
60 unsigned int dcache_bsize;
61
62 /* number of performance monitor counters */
63 unsigned int num_pmcs;
1bd2e5ae 64 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 65
66 /* this is called to initialize various CPU bits like L1 cache,
67 * BHT, SPD, etc... from head.S before branching to identify_machine
68 */
69 cpu_setup_t cpu_setup;
f39b7a55
OJ		 70 /* Used to restore cpu setup on secondary processors and at resume */
71 cpu_restore_t cpu_restore;
10b35d99
KG		 72
73 /* Used by oprofile userspace to select the right counters */
74 char *oprofile_cpu_type;
75
76 /* Processor specific oprofile operations */
32a33994 77 enum powerpc_oprofile_type oprofile_type;
80f15dc7 78
e78dbc80
MN		 79 /* Bit locations inside the mmcra change */
80 unsigned long oprofile_mmcra_sihv;
81 unsigned long oprofile_mmcra_sipr;
82
83 /* Bits to clear during an oprofile exception */
84 unsigned long oprofile_mmcra_clear;
85
80f15dc7
PM		 86 /* Name of processor class, for the ELF AT_PLATFORM entry */
87 char *platform;
47c0bd1a
BH		 88
89 /* Processor specific machine check handling. Return negative
90 * if the error is fatal, 1 if it was fully recovered and 0 to
91 * pass up (not CPU originated) */
92 int (*machine_check)(struct pt_regs *regs);
4c703416
MS		 93
94 /*
95 * Processor specific early machine check handler which is
96 * called in real mode to handle SLB and TLB errors.
97 */
98 long (*machine_check_early)(struct pt_regs *regs);
99
04407050
MS		 100 /*
101 * Processor specific routine to flush tlbs.
102 */
45706bb5 103 void (*flush_tlb)(unsigned int action);
04407050 104
10b35d99
KG		 105};
106
10b35d99 107extern struct cpu_spec *cur_cpu_spec;
10b35d99 108
42c4aaad
BH		 109extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
110
974a76f5 111extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 112extern void do_feature_fixups(unsigned long value, void *fixup_start,
113 void *fixup_end);
9b6b563c 114
9115d134
NL		 115extern const char *powerpc_base_platform;
116
45706bb5
MS		 117/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
118enum {
119 TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */
120 TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */
121};
122
10b35d99
KG		 123#endif /* __ASSEMBLY__ */
124
125/* CPU kernel features */
126
127/* Retain the 32b definitions all use bottom half of word */
cde4d494
MN		 128#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
129#define CPU_FTR_L2CR ASM_CONST(0x00000002)
130#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
131#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
132#define CPU_FTR_TAU ASM_CONST(0x00000010)
133#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
134#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
135#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
136#define CPU_FTR_601 ASM_CONST(0x00000100)
137#define CPU_FTR_DBELL ASM_CONST(0x00000200)
138#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
139#define CPU_FTR_L3CR ASM_CONST(0x00000800)
140#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
141#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
142#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
143#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
144#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
145#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
146#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
147#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
148#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
149#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
150#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
151#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
152#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
153#define CPU_FTR_SPE ASM_CONST(0x02000000)
154#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
155#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
156#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
157#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
158#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
10b35d99 159
3965f8c5
PM		 160/*
161 * Add the 64-bit processor unique features in the top half of the word;
162 * on 32-bit, make the names available but defined to be 0.
163 */
10b35d99 164#ifdef __powerpc64__
3965f8c5 165#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 166#else
3965f8c5 167#define LONG_ASM_CONST(x) 0
10b35d99
KG		 168#endif
169
1580b3b8
MN		 170#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
171#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
172#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
1de2bd4e 173#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
ed77d418 174/* Free LONG_ASM_CONST(0x0000001000000000) */
1580b3b8
MN		 175#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
176#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
177#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
178#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
179#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
180#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
181#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
182#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
183#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
184#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
185#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
186#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
187#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
188#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
189#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
190#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
191#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
192#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
193#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
1de2bd4e 194#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
1580b3b8 195#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
79879c17 196#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
82a9f16a 197#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
68f2f0d4 198#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
3965f8c5 199
10b35d99
KG		 200#ifndef __ASSEMBLY__
201
44ae3ab3
ME		 202#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
203
13b3d13b 204#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
10b35d99
KG		 205
206/* We only set the altivec features if the kernel was compiled with altivec
207 * support
208 */
209#ifdef CONFIG_ALTIVEC
210#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
211#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
212#else
213#define CPU_FTR_ALTIVEC_COMP 0
214#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
215#endif
216
b962ce9d
MN		 217/* We only set the VSX features if the kernel was compiled with VSX
218 * support
219 */
220#ifdef CONFIG_VSX
221#define CPU_FTR_VSX_COMP CPU_FTR_VSX
222#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
223#else
224#define CPU_FTR_VSX_COMP 0
225#define PPC_FEATURE_HAS_VSX_COMP 0
226#endif
227
5e14d21e
KG		 228/* We only set the spe features if the kernel was compiled with spe
229 * support
230 */
231#ifdef CONFIG_SPE
232#define CPU_FTR_SPE_COMP CPU_FTR_SPE
233#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
234#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
235#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
236#else
237#define CPU_FTR_SPE_COMP 0
238#define PPC_FEATURE_HAS_SPE_COMP 0
239#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
240#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
241#endif
242
6a6d541f
MN		 243/* We only set the TM feature if the kernel was compiled with TM supprt */
244#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
245#define CPU_FTR_TM_COMP CPU_FTR_TM
cbbc6f1b 246#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
6a6d541f
MN		 247#else
248#define CPU_FTR_TM_COMP 0
cbbc6f1b 249#define PPC_FEATURE2_HTM_COMP 0
6a6d541f
MN		 250#endif
251
11af1192
SW		 252/* We need to mark all pages as being coherent if we're SMP or we have a
253 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
254 * require it for PCI "streaming/prefetch" to work properly.
c9310920 255 * This is also required by 52xx family.
10b35d99 256 */
1775dbbc 257#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
c9310920
PZ		 258 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
259 || defined(CONFIG_PPC_MPC52xx)
10b35d99
KG		 260#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
261#else
262#define CPU_FTR_COMMON 0
263#endif
264
265/* The powersave features NAP & DOZE seems to confuse BDI when
266 debugging. So if a BDI is used, disable theses
267 */
268#ifndef CONFIG_BDI_SWITCH
269#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
270#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
271#else
272#define CPU_FTR_MAYBE_CAN_DOZE 0
273#define CPU_FTR_MAYBE_CAN_NAP 0
274#endif
275
7c03d653 276#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
4508dc21
DG		 277 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
278#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 279 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 280 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 281#define CPU_FTRS_604 (CPU_FTR_COMMON | \
7c03d653 282 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
4508dc21 283#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 284 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 285 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 286#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 287 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 288 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 289 CPU_FTR_PPC_LE)
4508dc21 290#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 291 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 292 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 293 CPU_FTR_PPC_LE)
7c03d653 294#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 295#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
296#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 297#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 298#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 299#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c 300 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 301 CPU_FTR_ALTIVEC_COMP | \
fab5db97 302 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 303#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c 304 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 305 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 306 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 307#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c 308 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 309 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 310 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 311#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 312 CPU_FTR_USE_TB | \
313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 314 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 315 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 316 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 317#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 318 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 319 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 320 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 321 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 322#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 323 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 324 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 325 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 326#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 327 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 328 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 329 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 330 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 331 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 332#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 333 CPU_FTR_USE_TB | \
334 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 335 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 336 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 337#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 338 CPU_FTR_USE_TB | \
339 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 340 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 341 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
342 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 343#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 344 CPU_FTR_USE_TB | \
345 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 346 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 347 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 348#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 349 CPU_FTR_USE_TB | \
350 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 351 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 352 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 353#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 354 CPU_FTR_USE_TB | \
355 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 356 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 357 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 358#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 359 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 360#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 361 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
4508dc21 362#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 363 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
7c92943c 364 CPU_FTR_COMMON)
4508dc21 365#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 366 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
aa42c69c 367 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
7c03d653 368#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
4508dc21 369#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
8309ce72
BH		 370#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
371#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
6d2170be
BH		 372#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
373 CPU_FTR_INDEXED_DCR)
e7f75ad0 374#define CPU_FTRS_47X (CPU_FTRS_440x6)
5e14d21e
KG		 375#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
376 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
52b066fa
SW		 377 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
378 CPU_FTR_DEBUG_LVL_EXC)
fc4033b2 379#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
8309ce72
BH		 380 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
381 CPU_FTR_NOEXECUTE)
fc4033b2 382#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
7c03d653 383 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 384 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
d51ad915 385#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
620165f9 386 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
73196cd3 387 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
d52459ca
SW		 388/*
389 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
390 * same workaround as CPU_FTR_CELL_TB_BUG.
391 */
11ed0db9
KG		 392#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
393 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
d36b4c4f 394 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 395 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
10241842
KG		 396#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
397 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
398 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 399 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
e16c8765 400 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
7c92943c 401#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 402
403/* 64-bit CPUs */
2d1b2027 404#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 405 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
f89451fb
AB		 406 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
407 CPU_FTR_STCX_CHECKS_ADDRESS)
2d1b2027 408#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 409 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
2a929436 410 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
969391c5 411 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
82a9f16a 412 CPU_FTR_HVMODE | CPU_FTR_DABRX)
2d1b2027 413#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 414 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 415 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 416 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
82a9f16a 417 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
2d1b2027 418#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 419 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51 420 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 421 CPU_FTR_COHERENT_ICACHE | \
4c198557 422 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 423 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
82a9f16a
MN		 424 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
425 CPU_FTR_DABRX)
2d1b2027 426#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 427 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
e952e6c4 428 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 429 CPU_FTR_COHERENT_ICACHE | \
e952e6c4 430 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 431 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
851d2e2f 432 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d2613868 433 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
82a9f16a 434 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
71e18497
MN		 435#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
436 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
437 CPU_FTR_MMCRA | CPU_FTR_SMT | \
438 CPU_FTR_COHERENT_ICACHE | \
439 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
440 CPU_FTR_DSCR | CPU_FTR_SAO | \
441 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
e5e84f0a 442 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
1de2bd4e
ME		 443 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
444 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
68f2f0d4 445#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
bd6ba351 446#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
2d1b2027 447#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 448 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 449 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 450 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
82a9f16a 451 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
2d1b2027 452#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
44ae3ab3 453 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
82a9f16a 454 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
7c03d653 455#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 456
2406f606 457#ifdef __powerpc64__
11ed0db9 458#ifdef CONFIG_PPC_BOOK3E
90029640 459#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
11ed0db9 460#else
7c92943c 461#define CPU_FTRS_POSSIBLE \
468a3302
ME		 462 (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
463 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
3609e09f
ME		 464 CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
465 CPU_FTRS_PA6T | CPU_FTR_VSX)
11ed0db9 466#endif
2406f606 467#else
7c92943c
SR		 468enum {
469 CPU_FTRS_POSSIBLE =
1e07a0a0 470#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 471 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
472 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
473 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
474 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
475 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
476 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
477 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 478 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
479 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 480#else
481 CPU_FTRS_GENERIC_32 |
482#endif
10b35d99
KG		 483#ifdef CONFIG_8xx
484 CPU_FTRS_8XX |
485#endif
486#ifdef CONFIG_40x
487 CPU_FTRS_40X |
488#endif
489#ifdef CONFIG_44x
6d2170be 490 CPU_FTRS_44X | CPU_FTRS_440x6 |
10b35d99 491#endif
e7f75ad0 492#ifdef CONFIG_PPC_47x
c48d0dba 493 CPU_FTRS_47X | CPU_FTR_476_DD2 |
e7f75ad0 494#endif
10b35d99
KG		 495#ifdef CONFIG_E200
496 CPU_FTRS_E200 |
497#endif
498#ifdef CONFIG_E500
06aae867
SW		 499 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
500#endif
501#ifdef CONFIG_PPC_E500MC
502 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
10b35d99 503#endif
10b35d99 504 0,
7c92943c
SR		 505};
506#endif /* __powerpc64__ */
10b35d99 507
2406f606 508#ifdef __powerpc64__
11ed0db9 509#ifdef CONFIG_PPC_BOOK3E
90029640 510#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
11ed0db9 511#else
7c92943c 512#define CPU_FTRS_ALWAYS \
468a3302
ME		 513 (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
514 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
3609e09f 515 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
66f3d4fe 516 CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE)
11ed0db9 517#endif
2406f606 518#else
7c92943c
SR		 519enum {
520 CPU_FTRS_ALWAYS =
1e07a0a0 521#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 522 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
523 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
524 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
525 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
526 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
527 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
528 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 529 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
530 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 531#else
532 CPU_FTRS_GENERIC_32 &
533#endif
10b35d99
KG		 534#ifdef CONFIG_8xx
535 CPU_FTRS_8XX &
536#endif
537#ifdef CONFIG_40x
538 CPU_FTRS_40X &
539#endif
540#ifdef CONFIG_44x
6d2170be 541 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99
KG		 542#endif
543#ifdef CONFIG_E200
544 CPU_FTRS_E200 &
545#endif
546#ifdef CONFIG_E500
06aae867
SW		 547 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
548#endif
549#ifdef CONFIG_PPC_E500MC
550 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
10b35d99 551#endif
73196cd3 552 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
10b35d99
KG		 553 CPU_FTRS_POSSIBLE,
554};
7c92943c 555#endif /* __powerpc64__ */
10b35d99
KG		 556
557static inline int cpu_has_feature(unsigned long feature)
558{
559 return (CPU_FTRS_ALWAYS & feature) ||
560 (CPU_FTRS_POSSIBLE
10b35d99 561 & cur_cpu_spec->cpu_features
10b35d99
KG		 562 & feature);
563}
564
5aae8a53 565#define HBP_NUM 1
5aae8a53 566
10b35d99
KG		 567#endif /* !__ASSEMBLY__ */
568
10b35d99 569#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)