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ELF loader support for auxvec base platform string
[linux-2.6-block.git] / include / asm-powerpc / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
10b35d99
KG		 4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000
9#define PPC_FEATURE_HAS_MMU 0x04000000
10#define PPC_FEATURE_HAS_4xxMAC 0x02000000
11#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
12#define PPC_FEATURE_HAS_SPE 0x00800000
13#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
14#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
98599013 15#define PPC_FEATURE_NO_TB 0x00100000
a7ddc5e8
PM		 16#define PPC_FEATURE_POWER4 0x00080000
17#define PPC_FEATURE_POWER5 0x00040000
18#define PPC_FEATURE_POWER5_PLUS 0x00020000
19#define PPC_FEATURE_CELL 0x00010000
80f15dc7 20#define PPC_FEATURE_BOOKE 0x00008000
aa5cb021
BH		 21#define PPC_FEATURE_SMT 0x00004000
22#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
03054d51 23#define PPC_FEATURE_ARCH_2_05 0x00001000
b3ebd1d8 24#define PPC_FEATURE_PA6T 0x00000800
974a76f5
PM		 25#define PPC_FEATURE_HAS_DFP 0x00000400
26#define PPC_FEATURE_POWER6_EXT 0x00000200
e952e6c4 27#define PPC_FEATURE_ARCH_2_06 0x00000100
b962ce9d 28#define PPC_FEATURE_HAS_VSX 0x00000080
10b35d99 29
0f473314
NL		 30#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
31 0x00000040
32
fab5db97
PM		 33#define PPC_FEATURE_TRUE_LE 0x00000002
34#define PPC_FEATURE_PPC_LE 0x00000001
35
10b35d99 36#ifdef __KERNEL__
d1cdcf22
AB		 37
38#include <asm/asm-compat.h>
c5157e58 39#include <asm/feature-fixups.h>
d1cdcf22 40
10b35d99
KG		 41#ifndef __ASSEMBLY__
42
43/* This structure can grow, it's real size is used by head.S code
44 * via the mkdefs mechanism.
45 */
46struct cpu_spec;
10b35d99 47
10b35d99 48typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 49typedef void (*cpu_restore_t)(void);
10b35d99 50
32a33994 51enum powerpc_oprofile_type {
7a45fb19
AW		 52 PPC_OPROFILE_INVALID = 0,
53 PPC_OPROFILE_RS64 = 1,
54 PPC_OPROFILE_POWER4 = 2,
55 PPC_OPROFILE_G4 = 3,
39aef685 56 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 57 PPC_OPROFILE_CELL = 5,
25fc530e 58 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 59};
60
1bd2e5ae
OJ		 61enum powerpc_pmc_type {
62 PPC_PMC_DEFAULT = 0,
63 PPC_PMC_IBM = 1,
64 PPC_PMC_PA6T = 2,
65};
66
47c0bd1a
BH		 67struct pt_regs;
68
69extern int machine_check_generic(struct pt_regs *regs);
70extern int machine_check_4xx(struct pt_regs *regs);
71extern int machine_check_440A(struct pt_regs *regs);
72extern int machine_check_e500(struct pt_regs *regs);
73extern int machine_check_e200(struct pt_regs *regs);
74
87a72f9e 75/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 76struct cpu_spec {
77 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
78 unsigned int pvr_mask;
79 unsigned int pvr_value;
80
81 char *cpu_name;
82 unsigned long cpu_features; /* Kernel features */
83 unsigned int cpu_user_features; /* Userland features */
84
85 /* cache line sizes */
86 unsigned int icache_bsize;
87 unsigned int dcache_bsize;
88
89 /* number of performance monitor counters */
90 unsigned int num_pmcs;
1bd2e5ae 91 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 92
93 /* this is called to initialize various CPU bits like L1 cache,
94 * BHT, SPD, etc... from head.S before branching to identify_machine
95 */
96 cpu_setup_t cpu_setup;
f39b7a55
OJ		 97 /* Used to restore cpu setup on secondary processors and at resume */
98 cpu_restore_t cpu_restore;
10b35d99
KG		 99
100 /* Used by oprofile userspace to select the right counters */
101 char *oprofile_cpu_type;
102
103 /* Processor specific oprofile operations */
32a33994 104 enum powerpc_oprofile_type oprofile_type;
80f15dc7 105
e78dbc80
MN		 106 /* Bit locations inside the mmcra change */
107 unsigned long oprofile_mmcra_sihv;
108 unsigned long oprofile_mmcra_sipr;
109
110 /* Bits to clear during an oprofile exception */
111 unsigned long oprofile_mmcra_clear;
112
80f15dc7
PM		 113 /* Name of processor class, for the ELF AT_PLATFORM entry */
114 char *platform;
47c0bd1a
BH		 115
116 /* Processor specific machine check handling. Return negative
117 * if the error is fatal, 1 if it was fully recovered and 0 to
118 * pass up (not CPU originated) */
119 int (*machine_check)(struct pt_regs *regs);
10b35d99
KG		 120};
121
10b35d99 122extern struct cpu_spec *cur_cpu_spec;
10b35d99 123
42c4aaad
BH		 124extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
125
974a76f5 126extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 127extern void do_feature_fixups(unsigned long value, void *fixup_start,
128 void *fixup_end);
9b6b563c 129
10b35d99
KG		 130#endif /* __ASSEMBLY__ */
131
132/* CPU kernel features */
133
134/* Retain the 32b definitions all use bottom half of word */
4508dc21 135#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
10b35d99
KG		 136#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
137#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
138#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
139#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
140#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
141#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
aba11fc5 142#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
10b35d99
KG		 143#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
144#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
145#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
146#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
147#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
148#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
149#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
150#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
151#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
152#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
153#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
154#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
3d15910b 155#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
fab5db97
PM		 156#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
157#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
aa42c69c 158#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
4508dc21 159#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
5e14d21e 160#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
b64f87c1 161#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
2d1b2027 162#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
10b35d99 163
3965f8c5
PM		 164/*
165 * Add the 64-bit processor unique features in the top half of the word;
166 * on 32-bit, make the names available but defined to be 0.
167 */
10b35d99 168#ifdef __powerpc64__
3965f8c5 169#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 170#else
3965f8c5 171#define LONG_ASM_CONST(x) 0
10b35d99
KG		 172#endif
173
3965f8c5
PM		 174#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
175#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
176#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
177#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
178#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
179#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
180#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
181#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
3965f8c5
PM		 182#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
183#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
184#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
185#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
859deea9 186#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
974a76f5 187#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
4c198557 188#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
1189be65 189#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
f66bce5e 190#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
b962ce9d 191#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
37907049 192#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
3965f8c5 193
10b35d99
KG		 194#ifndef __ASSEMBLY__
195
0470466d
SR		 196#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
197 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
198 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
10b35d99
KG		 199
200/* We only set the altivec features if the kernel was compiled with altivec
201 * support
202 */
203#ifdef CONFIG_ALTIVEC
204#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
205#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
206#else
207#define CPU_FTR_ALTIVEC_COMP 0
208#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
209#endif
210
b962ce9d
MN		 211/* We only set the VSX features if the kernel was compiled with VSX
212 * support
213 */
214#ifdef CONFIG_VSX
215#define CPU_FTR_VSX_COMP CPU_FTR_VSX
216#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
217#else
218#define CPU_FTR_VSX_COMP 0
219#define PPC_FEATURE_HAS_VSX_COMP 0
220#endif
221
5e14d21e
KG		 222/* We only set the spe features if the kernel was compiled with spe
223 * support
224 */
225#ifdef CONFIG_SPE
226#define CPU_FTR_SPE_COMP CPU_FTR_SPE
227#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
228#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
229#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
230#else
231#define CPU_FTR_SPE_COMP 0
232#define PPC_FEATURE_HAS_SPE_COMP 0
233#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
234#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
235#endif
236
11af1192
SW		 237/* We need to mark all pages as being coherent if we're SMP or we have a
238 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
239 * require it for PCI "streaming/prefetch" to work properly.
10b35d99 240 */
1775dbbc 241#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
11af1192 242 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
10b35d99
KG		 243#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
244#else
245#define CPU_FTR_COMMON 0
246#endif
247
248/* The powersave features NAP & DOZE seems to confuse BDI when
249 debugging. So if a BDI is used, disable theses
250 */
251#ifndef CONFIG_BDI_SWITCH
252#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
253#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
254#else
255#define CPU_FTR_MAYBE_CAN_DOZE 0
256#define CPU_FTR_MAYBE_CAN_NAP 0
257#endif
258
259#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
260 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
261 !defined(CONFIG_BOOKE))
262
4508dc21
DG		 263#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
264 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
265#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 266 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 267 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 268#define CPU_FTRS_604 (CPU_FTR_COMMON | \
aba11fc5 269 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
4508dc21 270#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 271 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97 272 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 273#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 274 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 275 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
276 CPU_FTR_PPC_LE)
4508dc21 277#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 278 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 279 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
280 CPU_FTR_PPC_LE)
b6f41cc8
JB		 281#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
282#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
283#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
284#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
285 CPU_FTR_HAS_HIGH_BATS)
286#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 287#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c
SR		 288 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
289 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 290 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 291#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c
SR		 292 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
293 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 294 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 295#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c
SR		 296 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
297 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
b64f87c1 298 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 299#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 300 CPU_FTR_USE_TB | \
301 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
302 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
303 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 304 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 305#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 306 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c
SR		 307 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
308 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
fab5db97 309 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 310#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 311 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c
SR		 312 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
313 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 314 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 315#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 316 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c
SR		 317 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
318 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
319 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
fab5db97 320 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
4508dc21 321#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 322 CPU_FTR_USE_TB | \
323 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
324 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
325 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 326 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 327#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 328 CPU_FTR_USE_TB | \
329 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
330 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
331 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1
BB		 332 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
333 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 334#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 335 CPU_FTR_USE_TB | \
336 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
337 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
338 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 339 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 340#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 341 CPU_FTR_USE_TB | \
342 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
343 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
344 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 345 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 346#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 347 CPU_FTR_USE_TB | \
348 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
349 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
350 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
b64f87c1 351 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 352#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 353 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 354#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c92943c 355 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
4508dc21 356#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c92943c
SR		 357 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
358 CPU_FTR_COMMON)
4508dc21 359#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
aa42c69c
KP		 360 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
361 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
4508dc21 362#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
7c92943c 363 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
4508dc21
DG		 364#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
365#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
366#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
5e14d21e
KG		 367#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
368 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
369 CPU_FTR_UNIFIED_ID_CACHE)
fc4033b2
KG		 370#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
371 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
372#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
373 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
3dfa8773 374 CPU_FTR_NODSISRALIGN)
fc4033b2 375#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
aba11fc5 376 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
2d1b2027 377 CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
7c92943c 378#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 379
380/* 64-bit CPUs */
2d1b2027 381#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
fab5db97 382 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
2d1b2027 383#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c92943c
SR		 384 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
385 CPU_FTR_MMCRA | CPU_FTR_CTRL)
2d1b2027 386#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
00243000
OJ		 387 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
388 CPU_FTR_MMCRA)
2d1b2027 389#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
00243000 390 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 391 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
2d1b2027 392#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
00243000 393 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c
SR		 394 CPU_FTR_MMCRA | CPU_FTR_SMT | \
395 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
e78dbc80 396 CPU_FTR_PURR)
2d1b2027 397#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
00243000 398 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51
AB		 399 CPU_FTR_MMCRA | CPU_FTR_SMT | \
400 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
4c198557
AB		 401 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
402 CPU_FTR_DSCR)
2d1b2027 403#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
e952e6c4
MN		 404 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
405 CPU_FTR_MMCRA | CPU_FTR_SMT | \
406 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
407 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
37907049 408 CPU_FTR_DSCR | CPU_FTR_SAO)
2d1b2027 409#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
00243000 410 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 411 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
859deea9 412 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
2d1b2027 413#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
b3ebd1d8
OJ		 414 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
415 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
f66bce5e 416 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
4508dc21 417#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
7c92943c 418 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 419
2406f606 420#ifdef __powerpc64__
7c92943c
SR		 421#define CPU_FTRS_POSSIBLE \
422 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
03054d51 423 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
e952e6c4 424 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
b962ce9d 425 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
2406f606 426#else
7c92943c
SR		 427enum {
428 CPU_FTRS_POSSIBLE =
10b35d99
KG		 429#if CLASSIC_PPC
430 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
431 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
432 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
433 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
434 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
435 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
436 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 437 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
438 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 439#else
440 CPU_FTRS_GENERIC_32 |
441#endif
10b35d99
KG		 442#ifdef CONFIG_8xx
443 CPU_FTRS_8XX |
444#endif
445#ifdef CONFIG_40x
446 CPU_FTRS_40X |
447#endif
448#ifdef CONFIG_44x
449 CPU_FTRS_44X |
450#endif
451#ifdef CONFIG_E200
452 CPU_FTRS_E200 |
453#endif
454#ifdef CONFIG_E500
3dfa8773 455 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
10b35d99 456#endif
10b35d99 457 0,
7c92943c
SR		 458};
459#endif /* __powerpc64__ */
10b35d99 460
2406f606 461#ifdef __powerpc64__
7c92943c
SR		 462#define CPU_FTRS_ALWAYS \
463 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51 464 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
e952e6c4 465 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
2406f606 466#else
7c92943c
SR		 467enum {
468 CPU_FTRS_ALWAYS =
10b35d99
KG		 469#if CLASSIC_PPC
470 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
471 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
472 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
473 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
474 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
475 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
476 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 477 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
478 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 479#else
480 CPU_FTRS_GENERIC_32 &
481#endif
10b35d99
KG		 482#ifdef CONFIG_8xx
483 CPU_FTRS_8XX &
484#endif
485#ifdef CONFIG_40x
486 CPU_FTRS_40X &
487#endif
488#ifdef CONFIG_44x
489 CPU_FTRS_44X &
490#endif
491#ifdef CONFIG_E200
492 CPU_FTRS_E200 &
493#endif
494#ifdef CONFIG_E500
3dfa8773 495 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
10b35d99 496#endif
10b35d99
KG		 497 CPU_FTRS_POSSIBLE,
498};
7c92943c 499#endif /* __powerpc64__ */
10b35d99
KG		 500
501static inline int cpu_has_feature(unsigned long feature)
502{
503 return (CPU_FTRS_ALWAYS & feature) ||
504 (CPU_FTRS_POSSIBLE
10b35d99 505 & cur_cpu_spec->cpu_features
10b35d99
KG		 506 & feature);
507}
508
509#endif /* !__ASSEMBLY__ */
510
10b35d99
KG		 511#endif /* __KERNEL__ */
512#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)