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powerpc/64s: Fix masking of SRR1 bits on instruction fault
[linux-2.6-block.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
d1cdcf22 4
6574ba95 5#include <linux/types.h>
d1cdcf22 6#include <asm/asm-compat.h>
c5157e58 7#include <asm/feature-fixups.h>
c3617f72 8#include <uapi/asm/cputable.h>
d1cdcf22 9
10b35d99
KG		 10#ifndef __ASSEMBLY__
11
12/* This structure can grow, it's real size is used by head.S code
13 * via the mkdefs mechanism.
14 */
15struct cpu_spec;
10b35d99 16
10b35d99 17typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 18typedef void (*cpu_restore_t)(void);
10b35d99 19
32a33994 20enum powerpc_oprofile_type {
7a45fb19
AW		 21 PPC_OPROFILE_INVALID = 0,
22 PPC_OPROFILE_RS64 = 1,
23 PPC_OPROFILE_POWER4 = 2,
24 PPC_OPROFILE_G4 = 3,
39aef685 25 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 26 PPC_OPROFILE_CELL = 5,
25fc530e 27 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 28};
29
1bd2e5ae
OJ		 30enum powerpc_pmc_type {
31 PPC_PMC_DEFAULT = 0,
32 PPC_PMC_IBM = 1,
33 PPC_PMC_PA6T = 2,
b950bdd0 34 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 35};
36
47c0bd1a
BH		 37struct pt_regs;
38
39extern int machine_check_generic(struct pt_regs *regs);
40extern int machine_check_4xx(struct pt_regs *regs);
41extern int machine_check_440A(struct pt_regs *regs);
fe04b112 42extern int machine_check_e500mc(struct pt_regs *regs);
47c0bd1a
BH		 43extern int machine_check_e500(struct pt_regs *regs);
44extern int machine_check_e200(struct pt_regs *regs);
fc5e7097 45extern int machine_check_47x(struct pt_regs *regs);
e627f8dc 46int machine_check_8xx(struct pt_regs *regs);
47c0bd1a 47
e7affb1d 48extern void cpu_down_flush_e500v2(void);
49extern void cpu_down_flush_e500mc(void);
50extern void cpu_down_flush_e5500(void);
51extern void cpu_down_flush_e6500(void);
52
87a72f9e 53/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 54struct cpu_spec {
55 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
56 unsigned int pvr_mask;
57 unsigned int pvr_value;
58
59 char *cpu_name;
60 unsigned long cpu_features; /* Kernel features */
61 unsigned int cpu_user_features; /* Userland features */
2171364d 62 unsigned int cpu_user_features2; /* Userland features v2 */
7c03d653 63 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 64
65 /* cache line sizes */
66 unsigned int icache_bsize;
67 unsigned int dcache_bsize;
68
e7affb1d 69 /* flush caches inside the current cpu */
70 void (*cpu_down_flush)(void);
71
10b35d99
KG		 72 /* number of performance monitor counters */
73 unsigned int num_pmcs;
1bd2e5ae 74 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 75
76 /* this is called to initialize various CPU bits like L1 cache,
77 * BHT, SPD, etc... from head.S before branching to identify_machine
78 */
79 cpu_setup_t cpu_setup;
f39b7a55
OJ		 80 /* Used to restore cpu setup on secondary processors and at resume */
81 cpu_restore_t cpu_restore;
10b35d99
KG		 82
83 /* Used by oprofile userspace to select the right counters */
84 char *oprofile_cpu_type;
85
86 /* Processor specific oprofile operations */
32a33994 87 enum powerpc_oprofile_type oprofile_type;
80f15dc7 88
e78dbc80
MN		 89 /* Bit locations inside the mmcra change */
90 unsigned long oprofile_mmcra_sihv;
91 unsigned long oprofile_mmcra_sipr;
92
93 /* Bits to clear during an oprofile exception */
94 unsigned long oprofile_mmcra_clear;
95
80f15dc7
PM		 96 /* Name of processor class, for the ELF AT_PLATFORM entry */
97 char *platform;
47c0bd1a
BH		 98
99 /* Processor specific machine check handling. Return negative
100 * if the error is fatal, 1 if it was fully recovered and 0 to
101 * pass up (not CPU originated) */
102 int (*machine_check)(struct pt_regs *regs);
4c703416
MS		 103
104 /*
105 * Processor specific early machine check handler which is
106 * called in real mode to handle SLB and TLB errors.
107 */
108 long (*machine_check_early)(struct pt_regs *regs);
109
04407050
MS		 110 /*
111 * Processor specific routine to flush tlbs.
112 */
45706bb5 113 void (*flush_tlb)(unsigned int action);
04407050 114
10b35d99
KG		 115};
116
10b35d99 117extern struct cpu_spec *cur_cpu_spec;
10b35d99 118
42c4aaad
BH		 119extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
120
5a61ef74 121extern void set_cur_cpu_spec(struct cpu_spec *s);
974a76f5 122extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
5a61ef74 123extern void identify_cpu_name(unsigned int pvr);
0909c8c2
BH		 124extern void do_feature_fixups(unsigned long value, void *fixup_start,
125 void *fixup_end);
9b6b563c 126
9115d134
NL		 127extern const char *powerpc_base_platform;
128
4db73271
KH		 129#ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
130extern void cpu_feature_keys_init(void);
131#else
132static inline void cpu_feature_keys_init(void) { }
133#endif
134
45706bb5
MS		 135/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
136enum {
137 TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */
138 TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */
139};
140
10b35d99
KG		 141#endif /* __ASSEMBLY__ */
142
143/* CPU kernel features */
144
145/* Retain the 32b definitions all use bottom half of word */
cde4d494
MN		 146#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
147#define CPU_FTR_L2CR ASM_CONST(0x00000002)
148#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
149#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
150#define CPU_FTR_TAU ASM_CONST(0x00000010)
151#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
152#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
153#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
154#define CPU_FTR_601 ASM_CONST(0x00000100)
155#define CPU_FTR_DBELL ASM_CONST(0x00000200)
156#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
157#define CPU_FTR_L3CR ASM_CONST(0x00000800)
158#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
159#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
160#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
161#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
162#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
163#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
164#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
165#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
166#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
167#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
168#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
169#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
170#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
171#define CPU_FTR_SPE ASM_CONST(0x02000000)
172#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
173#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
174#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
175#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
176#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
10b35d99 177
3965f8c5
PM		 178/*
179 * Add the 64-bit processor unique features in the top half of the word;
180 * on 32-bit, make the names available but defined to be 0.
181 */
10b35d99 182#ifdef __powerpc64__
3965f8c5 183#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 184#else
3965f8c5 185#define LONG_ASM_CONST(x) 0
10b35d99
KG		 186#endif
187
1580b3b8
MN		 188#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
189#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
190#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
1de2bd4e 191#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
c3ab300e 192#define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000)
1580b3b8
MN		 193#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
194#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
195#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
196#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
197#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
198#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
199#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
200#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
201#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
202#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
203#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
204#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
205#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
206#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
207#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
208#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
c1807e3f 209/* Free LONG_ASM_CONST(0x0020000000000000) */
1580b3b8
MN		 210#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
211#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
1de2bd4e 212#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
1580b3b8 213#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
79879c17 214#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
82a9f16a 215#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
68f2f0d4 216#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
7dccfbc3 217#define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x4000000000000000)
b6b3755e 218#define CPU_FTR_POWER9_DD20 LONG_ASM_CONST(0x8000000000000000)
3965f8c5 219
10b35d99
KG		 220#ifndef __ASSEMBLY__
221
44ae3ab3
ME		 222#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
223
13b3d13b 224#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
10b35d99
KG		 225
226/* We only set the altivec features if the kernel was compiled with altivec
227 * support
228 */
229#ifdef CONFIG_ALTIVEC
230#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
231#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
232#else
233#define CPU_FTR_ALTIVEC_COMP 0
234#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
235#endif
236
b962ce9d
MN		 237/* We only set the VSX features if the kernel was compiled with VSX
238 * support
239 */
240#ifdef CONFIG_VSX
241#define CPU_FTR_VSX_COMP CPU_FTR_VSX
242#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
243#else
244#define CPU_FTR_VSX_COMP 0
245#define PPC_FEATURE_HAS_VSX_COMP 0
246#endif
247
5e14d21e
KG		 248/* We only set the spe features if the kernel was compiled with spe
249 * support
250 */
251#ifdef CONFIG_SPE
252#define CPU_FTR_SPE_COMP CPU_FTR_SPE
253#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
254#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
255#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
256#else
257#define CPU_FTR_SPE_COMP 0
258#define PPC_FEATURE_HAS_SPE_COMP 0
259#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
260#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
261#endif
262
6a6d541f
MN		 263/* We only set the TM feature if the kernel was compiled with TM supprt */
264#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
b4b56f9e
S		 265#define CPU_FTR_TM_COMP CPU_FTR_TM
266#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
267#define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
6a6d541f 268#else
b4b56f9e
S		 269#define CPU_FTR_TM_COMP 0
270#define PPC_FEATURE2_HTM_COMP 0
271#define PPC_FEATURE2_HTM_NOSC_COMP 0
6a6d541f
MN		 272#endif
273
11af1192
SW		 274/* We need to mark all pages as being coherent if we're SMP or we have a
275 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
276 * require it for PCI "streaming/prefetch" to work properly.
c9310920 277 * This is also required by 52xx family.
10b35d99 278 */
1775dbbc 279#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
c9310920
PZ		 280 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
281 || defined(CONFIG_PPC_MPC52xx)
10b35d99
KG		 282#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
283#else
284#define CPU_FTR_COMMON 0
285#endif
286
287/* The powersave features NAP & DOZE seems to confuse BDI when
288 debugging. So if a BDI is used, disable theses
289 */
290#ifndef CONFIG_BDI_SWITCH
291#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
292#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
293#else
294#define CPU_FTR_MAYBE_CAN_DOZE 0
295#define CPU_FTR_MAYBE_CAN_NAP 0
296#endif
297
7c03d653 298#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
4508dc21
DG		 299 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
300#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 301 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 302 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 303#define CPU_FTRS_604 (CPU_FTR_COMMON | \
7c03d653 304 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
4508dc21 305#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 306 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 307 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 308#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 309 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 310 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 311 CPU_FTR_PPC_LE)
4508dc21 312#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 313 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 314 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 315 CPU_FTR_PPC_LE)
7c03d653 316#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 317#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
318#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 319#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 320#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 321#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c 322 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 323 CPU_FTR_ALTIVEC_COMP | \
fab5db97 324 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 325#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c 326 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 327 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 328 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 329#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c 330 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 331 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 332 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 333#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 334 CPU_FTR_USE_TB | \
335 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 336 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 337 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 338 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 339#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 340 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 341 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 342 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 343 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 344#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 345 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 346 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 347 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 348#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 349 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 350 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 351 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 352 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 353 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 354#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 355 CPU_FTR_USE_TB | \
356 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 357 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 358 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 359#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 360 CPU_FTR_USE_TB | \
361 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 362 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 363 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
364 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 365#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 366 CPU_FTR_USE_TB | \
367 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 368 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 369 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 370#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 371 CPU_FTR_USE_TB | \
372 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 373 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 374 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 375#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 376 CPU_FTR_USE_TB | \
377 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 378 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 379 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 380#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 381 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 382#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 383 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
4508dc21 384#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 385 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
7c92943c 386 CPU_FTR_COMMON)
4508dc21 387#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 388 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
aa42c69c 389 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
7c03d653 390#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
5b2753fc 391#define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
8309ce72
BH		 392#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
393#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
6d2170be
BH		 394#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
395 CPU_FTR_INDEXED_DCR)
e7f75ad0 396#define CPU_FTRS_47X (CPU_FTRS_440x6)
5e14d21e
KG		 397#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
398 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
52b066fa
SW		 399 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
400 CPU_FTR_DEBUG_LVL_EXC)
fc4033b2 401#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
8309ce72
BH		 402 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
403 CPU_FTR_NOEXECUTE)
fc4033b2 404#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
7c03d653 405 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 406 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
d51ad915 407#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
620165f9 408 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
73196cd3 409 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
d52459ca
SW		 410/*
411 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
412 * same workaround as CPU_FTR_CELL_TB_BUG.
413 */
11ed0db9
KG		 414#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
415 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
d36b4c4f 416 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 417 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
10241842
KG		 418#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
419 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
420 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 421 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
e16c8765 422 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
7c92943c 423#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 424
425/* 64-bit CPUs */
2d1b2027 426#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 427 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
f89451fb
AB		 428 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
429 CPU_FTR_STCX_CHECKS_ADDRESS)
2d1b2027 430#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 431 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
2a929436 432 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
969391c5 433 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
82a9f16a 434 CPU_FTR_HVMODE | CPU_FTR_DABRX)
2d1b2027 435#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 436 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 437 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 438 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
82a9f16a 439 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
2d1b2027 440#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 441 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51 442 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 443 CPU_FTR_COHERENT_ICACHE | \
4c198557 444 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 445 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
82a9f16a
MN		 446 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
447 CPU_FTR_DABRX)
2d1b2027 448#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 449 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
e952e6c4 450 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 451 CPU_FTR_COHERENT_ICACHE | \
e952e6c4 452 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 453 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
851d2e2f 454 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
c1807e3f 455 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
82a9f16a 456 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
71e18497
MN		 457#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
458 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
459 CPU_FTR_MMCRA | CPU_FTR_SMT | \
460 CPU_FTR_COHERENT_ICACHE | \
461 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
462 CPU_FTR_DSCR | CPU_FTR_SAO | \
463 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
c1807e3f 464 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
1de2bd4e 465 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
0e5e7f5e 466 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
68f2f0d4 467#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
bd6ba351 468#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
c3ab300e
MN		 469#define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
470 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
471 CPU_FTR_MMCRA | CPU_FTR_SMT | \
472 CPU_FTR_COHERENT_ICACHE | \
473 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
474 CPU_FTR_DSCR | CPU_FTR_SAO | \
475 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
2384d2d7 476 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
c3ab300e
MN		 477 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
478 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300)
ca80d5d0
NP		 479#define CPU_FTRS_POWER9_DD1 ((CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) & \
480 (~CPU_FTR_SAO))
b6b3755e 481#define CPU_FTRS_POWER9_DD20 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD20)
2d1b2027 482#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 483 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 484 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 485 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
82a9f16a 486 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
2d1b2027 487#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
44ae3ab3 488 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
82a9f16a 489 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
7c03d653 490#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 491
2406f606 492#ifdef __powerpc64__
11ed0db9 493#ifdef CONFIG_PPC_BOOK3E
90029640 494#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
11ed0db9 495#else
7c92943c 496#define CPU_FTRS_POSSIBLE \
468a3302
ME		 497 (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
498 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
3609e09f 499 CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
b6b3755e
NP		 500 CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9 | \
501 CPU_FTRS_POWER9_DD1 | CPU_FTRS_POWER9_DD20)
11ed0db9 502#endif
2406f606 503#else
7c92943c
SR		 504enum {
505 CPU_FTRS_POSSIBLE =
1e07a0a0 506#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 507 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
508 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
509 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
510 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
511 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
512 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
513 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 514 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
515 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 516#else
517 CPU_FTRS_GENERIC_32 |
518#endif
968159c0 519#ifdef CONFIG_PPC_8xx
10b35d99
KG		 520 CPU_FTRS_8XX |
521#endif
522#ifdef CONFIG_40x
523 CPU_FTRS_40X |
524#endif
525#ifdef CONFIG_44x
6d2170be 526 CPU_FTRS_44X | CPU_FTRS_440x6 |
10b35d99 527#endif
e7f75ad0 528#ifdef CONFIG_PPC_47x
c48d0dba 529 CPU_FTRS_47X | CPU_FTR_476_DD2 |
e7f75ad0 530#endif
10b35d99
KG		 531#ifdef CONFIG_E200
532 CPU_FTRS_E200 |
533#endif
534#ifdef CONFIG_E500
06aae867
SW		 535 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
536#endif
537#ifdef CONFIG_PPC_E500MC
538 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
10b35d99 539#endif
10b35d99 540 0,
7c92943c
SR		 541};
542#endif /* __powerpc64__ */
10b35d99 543
2406f606 544#ifdef __powerpc64__
11ed0db9 545#ifdef CONFIG_PPC_BOOK3E
90029640 546#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
11ed0db9 547#else
7c92943c 548#define CPU_FTRS_ALWAYS \
468a3302
ME		 549 (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
550 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
3609e09f 551 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
c3ab300e
MN		 552 CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
553 CPU_FTRS_POWER9)
11ed0db9 554#endif
2406f606 555#else
7c92943c
SR		 556enum {
557 CPU_FTRS_ALWAYS =
1e07a0a0 558#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 559 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
560 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
561 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
562 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
563 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
564 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
565 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 566 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
567 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 568#else
569 CPU_FTRS_GENERIC_32 &
570#endif
968159c0 571#ifdef CONFIG_PPC_8xx
10b35d99
KG		 572 CPU_FTRS_8XX &
573#endif
574#ifdef CONFIG_40x
575 CPU_FTRS_40X &
576#endif
577#ifdef CONFIG_44x
6d2170be 578 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99
KG		 579#endif
580#ifdef CONFIG_E200
581 CPU_FTRS_E200 &
582#endif
583#ifdef CONFIG_E500
06aae867
SW		 584 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
585#endif
586#ifdef CONFIG_PPC_E500MC
587 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
10b35d99 588#endif
73196cd3 589 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
10b35d99
KG		 590 CPU_FTRS_POSSIBLE,
591};
7c92943c 592#endif /* __powerpc64__ */
10b35d99 593
5aae8a53 594#define HBP_NUM 1
5aae8a53 595
10b35d99
KG		 596#endif /* !__ASSEMBLY__ */
597
10b35d99 598#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)