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net/mlx4_core: Fix mpt_entry initialization in mlx4_mr_rereg_mem_write()
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 6] = "SRQ support",
88 [ 7] = "IPoIB checksum offload",
89 [ 8] = "P_Key violation counter",
90 [ 9] = "Q_Key violation counter",
4d531aa8 91 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 92 [15] = "Big LSO headers",
225c7b1f
RD		 93 [16] = "MW support",
94 [17] = "APM support",
95 [18] = "Atomic ops support",
96 [19] = "Raw multicast support",
97 [20] = "Address vector port checking support",
98 [21] = "UD multicast support",
ccf86321
OG		 99 [30] = "IBoE support",
100 [32] = "Unicast loopback support",
f3a9d1f2 101 [34] = "FCS header control",
cb2147a9
OG		 102 [37] = "Wake On LAN (port1) support",
103 [38] = "Wake On LAN (port2) support",
ccf86321
OG		 104 [40] = "UDP RSS support",
105 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 106 [42] = "Multicast VEP steering support",
107 [48] = "Counters support",
540b3a39 108 [53] = "Port ETS Scheduler support",
4d531aa8 109 [55] = "Port link type sensing support",
00f5ce99 110 [59] = "Port management change event support",
08ff3235
OG		 111 [61] = "64 byte EQE support",
112 [62] = "64 byte CQE support",
225c7b1f
RD		 113 };
114 int i;
115
116 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 117 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 118 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 119 mlx4_dbg(dev, " %s\n", fname[i]);
120}
121
b3416f44
SP		 122static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
123{
124 static const char * const fname[] = {
125 [0] = "RSS support",
126 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 127 [2] = "RSS XOR Hash Function support",
56cb4567 128 [3] = "Device managed flow steering support",
d998735f 129 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 130 [5] = "Time stamping support",
131 [6] = "VST (control vlan insertion/stripping) support",
b01978ca 132 [7] = "FSM (MAC anti-spoofing) support",
7ffdf726 133 [8] = "Dynamic QP updates support",
56cb4567 134 [9] = "Device managed flow steering IPoIB support",
114840c3 135 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
77507aa2
IS		 136 [11] = "MAD DEMUX (Secure-Host) support",
137 [12] = "Large cache line (>64B) CQE stride support",
adbc7ac5 138 [13] = "Large cache line (>64B) EQE stride support",
a53e3e8c 139 [14] = "Ethernet protocol control support",
d475c95b 140 [15] = "Ethernet Backplane autoneg support",
7ae0e400 141 [16] = "CONFIG DEV support",
de966c59 142 [17] = "Asymmetric EQs support",
7d077cd3 143 [18] = "More than 80 VFs support",
be6a6b43 144 [19] = "Performance optimized for limited rule configuration flow steering support",
59e14e32
MS		 145 [20] = "Recoverable error events support",
146 [21] = "Port Remap support"
b3416f44
SP		 147 };
148 int i;
149
150 for (i = 0; i < ARRAY_SIZE(fname); ++i)
151 if (fname[i] && (flags & (1LL << i)))
152 mlx4_dbg(dev, " %s\n", fname[i]);
153}
154
2d928651
VS		 155int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
156{
157 struct mlx4_cmd_mailbox *mailbox;
158 u32 *inbox;
159 int err = 0;
160
161#define MOD_STAT_CFG_IN_SIZE 0x100
162
163#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
164#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
165
166 mailbox = mlx4_alloc_cmd_mailbox(dev);
167 if (IS_ERR(mailbox))
168 return PTR_ERR(mailbox);
169 inbox = mailbox->buf;
170
2d928651
VS		 171 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
172 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
173
174 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 175 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 176
177 mlx4_free_cmd_mailbox(dev, mailbox);
178 return err;
179}
180
e8c4265b
MB		 181int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave)
182{
183 struct mlx4_cmd_mailbox *mailbox;
184 u32 *outbox;
185 u8 in_modifier;
186 u8 field;
187 u16 field16;
188 int err;
189
190#define QUERY_FUNC_BUS_OFFSET 0x00
191#define QUERY_FUNC_DEVICE_OFFSET 0x01
192#define QUERY_FUNC_FUNCTION_OFFSET 0x01
193#define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
194#define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
195#define QUERY_FUNC_MAX_EQ_OFFSET 0x06
196#define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
197
198 mailbox = mlx4_alloc_cmd_mailbox(dev);
199 if (IS_ERR(mailbox))
200 return PTR_ERR(mailbox);
201 outbox = mailbox->buf;
202
203 in_modifier = slave;
e8c4265b
MB		 204
205 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0,
206 MLX4_CMD_QUERY_FUNC,
207 MLX4_CMD_TIME_CLASS_A,
208 MLX4_CMD_NATIVE);
209 if (err)
210 goto out;
211
212 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
213 func->bus = field & 0xf;
214 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
215 func->device = field & 0xf1;
216 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
217 func->function = field & 0x7;
218 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
219 func->physical_function = field & 0xf;
220 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
221 func->rsvd_eqs = field16 & 0xffff;
222 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
223 func->max_eq = field16 & 0xffff;
224 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
225 func->rsvd_uars = field & 0x0f;
226
227 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
228 func->bus, func->device, func->function, func->physical_function,
229 func->max_eq, func->rsvd_eqs, func->rsvd_uars);
230
231out:
232 mlx4_free_cmd_mailbox(dev, mailbox);
233 return err;
234}
235
5cc914f1
MA		 236int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
237 struct mlx4_vhcr *vhcr,
238 struct mlx4_cmd_mailbox *inbox,
239 struct mlx4_cmd_mailbox *outbox,
240 struct mlx4_cmd_info *cmd)
241{
5a0d0a61 242 struct mlx4_priv *priv = mlx4_priv(dev);
99ec41d0
JM		 243 u8 field, port;
244 u32 size, proxy_qp, qkey;
5cc914f1 245 int err = 0;
7ae0e400 246 struct mlx4_func func;
5cc914f1
MA		 247
248#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
249#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 250#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 251#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 252#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
253#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
254#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
255#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
256#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
257#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 258#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 259#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
f0ce0615 260#define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48
5cc914f1 261
eb456a68
JM		 262#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
263#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
264#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
265#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
266#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
267#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
268
ddae0349
EE		 269#define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c
270
105c320f
JM		 271#define QUERY_FUNC_CAP_FMR_FLAG 0x80
272#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
273#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 274#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
f0ce0615 275#define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08
ddae0349
EE		 276#define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04
277
278#define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31)
d57febe1 279#define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30)
105c320f
JM		 280
281/* when opcode modifier = 1 */
5cc914f1 282#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
99ec41d0 283#define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
73e74ab4
HHZ		 284#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
285#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 286
47605df9
JM		 287#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
288#define QUERY_FUNC_CAP_QP0_PROXY 0x14
289#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
290#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
8e1a28e8 291#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
47605df9 292
73e74ab4
HHZ		 293#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
294#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
eb17711b 295#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
99ec41d0 296#define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
105c320f 297
73e74ab4 298#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
7ae0e400 299#define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
105c320f 300
5cc914f1 301 if (vhcr->op_modifier == 1) {
449fc488
MB		 302 struct mlx4_active_ports actv_ports =
303 mlx4_get_active_ports(dev, slave);
304 int converted_port = mlx4_slave_convert_port(
305 dev, slave, vhcr->in_modifier);
306
307 if (converted_port < 0)
308 return -EINVAL;
309
310 vhcr->in_modifier = converted_port;
449fc488
MB		 311 /* phys-port = logical-port */
312 field = vhcr->in_modifier -
313 find_first_bit(actv_ports.ports, dev->caps.num_ports);
47605df9
JM		 314 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
315
99ec41d0
JM		 316 port = vhcr->in_modifier;
317 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
318
319 /* Set nic_info bit to mark new fields support */
320 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
321
322 if (mlx4_vf_smi_enabled(dev, slave, port) &&
323 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
324 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
325 MLX4_PUT(outbox->buf, qkey,
326 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
327 }
328 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
329
47605df9 330 /* size is now the QP number */
99ec41d0 331 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
47605df9
JM		 332 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
333
334 size += 2;
335 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
336
99ec41d0
JM		 337 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
338 proxy_qp += 2;
339 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
47605df9 340
8e1a28e8
HHZ		 341 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
342 QUERY_FUNC_CAP_PHYS_PORT_ID);
343
5cc914f1 344 } else if (vhcr->op_modifier == 0) {
449fc488
MB		 345 struct mlx4_active_ports actv_ports =
346 mlx4_get_active_ports(dev, slave);
f0ce0615
JM		 347 /* enable rdma and ethernet interfaces, new quota locations,
348 * and reserved lkey
349 */
eb456a68 350 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
f0ce0615
JM		 351 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX |
352 QUERY_FUNC_CAP_FLAG_RESD_LKEY);
5cc914f1
MA		 353 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
354
449fc488
MB		 355 field = min(
356 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
357 dev->caps.num_ports);
5cc914f1
MA		 358 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
359
08ff3235 360 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 361 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
362
105c320f
JM		 363 field = 0; /* protected FMR support not available as yet */
364 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
365
5a0d0a61 366 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 367 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 368 size = dev->caps.num_qps;
369 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 370
5a0d0a61 371 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 372 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 373 size = dev->caps.num_srqs;
374 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 375
5a0d0a61 376 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 377 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 378 size = dev->caps.num_cqs;
379 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1 380
7ae0e400
MB		 381 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
382 mlx4_QUERY_FUNC(dev, &func, slave)) {
383 size = vhcr->in_modifier &
384 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
385 dev->caps.num_eqs :
386 rounddown_pow_of_two(dev->caps.num_eqs);
387 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
388 size = dev->caps.reserved_eqs;
389 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
390 } else {
391 size = vhcr->in_modifier &
392 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
393 func.max_eq :
394 rounddown_pow_of_two(func.max_eq);
395 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
396 size = func.rsvd_eqs;
397 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
398 }
5cc914f1 399
5a0d0a61 400 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 401 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 402 size = dev->caps.num_mpts;
403 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 404
5a0d0a61 405 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 406 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 407 size = dev->caps.num_mtts;
408 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 409
410 size = dev->caps.num_mgms + dev->caps.num_amgms;
411 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 412 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1 413
d57febe1
MB		 414 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG |
415 QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG;
ddae0349 416 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
f0ce0615
JM		 417
418 size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00);
419 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
5cc914f1
MA		 420 } else
421 err = -EINVAL;
422
423 return err;
424}
425
225c6c8c 426int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
47605df9 427 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 428{
429 struct mlx4_cmd_mailbox *mailbox;
430 u32 *outbox;
47605df9 431 u8 field, op_modifier;
99ec41d0 432 u32 size, qkey;
eb456a68 433 int err = 0, quotas = 0;
7ae0e400 434 u32 in_modifier;
5cc914f1 435
47605df9 436 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
7ae0e400
MB		 437 in_modifier = op_modifier ? gen_or_port :
438 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS;
5cc914f1
MA		 439
440 mailbox = mlx4_alloc_cmd_mailbox(dev);
441 if (IS_ERR(mailbox))
442 return PTR_ERR(mailbox);
443
7ae0e400 444 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier,
47605df9 445 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 446 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
447 if (err)
448 goto out;
449
450 outbox = mailbox->buf;
451
47605df9
JM		 452 if (!op_modifier) {
453 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
454 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
455 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
456 err = -EPROTONOSUPPORT;
457 goto out;
458 }
459 func_cap->flags = field;
eb456a68 460 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 461
47605df9
JM		 462 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
463 func_cap->num_ports = field;
5cc914f1 464
47605df9
JM		 465 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
466 func_cap->pf_context_behaviour = size;
5cc914f1 467
eb456a68
JM		 468 if (quotas) {
469 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
470 func_cap->qp_quota = size & 0xFFFFFF;
471
472 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
473 func_cap->srq_quota = size & 0xFFFFFF;
474
475 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
476 func_cap->cq_quota = size & 0xFFFFFF;
477
478 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
479 func_cap->mpt_quota = size & 0xFFFFFF;
480
481 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
482 func_cap->mtt_quota = size & 0xFFFFFF;
483
484 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
485 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 486
eb456a68
JM		 487 } else {
488 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
489 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 490
eb456a68
JM		 491 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
492 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 493
eb456a68
JM		 494 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
495 func_cap->cq_quota = size & 0xFFFFFF;
496
497 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
498 func_cap->mpt_quota = size & 0xFFFFFF;
499
500 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
501 func_cap->mtt_quota = size & 0xFFFFFF;
502
503 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
504 func_cap->mcg_quota = size & 0xFFFFFF;
505 }
47605df9
JM		 506 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
507 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 508
47605df9
JM		 509 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
510 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 511
f0ce0615
JM		 512 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) {
513 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
514 func_cap->reserved_lkey = size;
515 } else {
516 func_cap->reserved_lkey = 0;
517 }
518
ddae0349
EE		 519 func_cap->extra_flags = 0;
520
521 /* Mailbox data from 0x6c and onward should only be treated if
522 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags
523 */
524 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) {
525 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
526 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG)
527 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP;
d57febe1
MB		 528 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG)
529 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP;
ddae0349
EE		 530 }
531
47605df9
JM		 532 goto out;
533 }
5cc914f1 534
47605df9
JM		 535 /* logical port query */
536 if (gen_or_port > dev->caps.num_ports) {
537 err = -EINVAL;
538 goto out;
539 }
5cc914f1 540
eb17711b 541 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
47605df9 542 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
bc82878b 543 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
47605df9
JM		 544 mlx4_err(dev, "VLAN is enforced on this port\n");
545 err = -EPROTONOSUPPORT;
5cc914f1 546 goto out;
47605df9 547 }
5cc914f1 548
eb17711b 549 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 550 mlx4_err(dev, "Force mac is enabled on this port\n");
551 err = -EPROTONOSUPPORT;
552 goto out;
5cc914f1 553 }
47605df9 554 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 555 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
556 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
1a91de28 557 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
47605df9
JM		 558 err = -EPROTONOSUPPORT;
559 goto out;
560 }
561 }
5cc914f1 562
47605df9
JM		 563 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
564 func_cap->physical_port = field;
565 if (func_cap->physical_port != gen_or_port) {
566 err = -ENOSYS;
567 goto out;
5cc914f1
MA		 568 }
569
99ec41d0
JM		 570 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
571 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
572 func_cap->qp0_qkey = qkey;
573 } else {
574 func_cap->qp0_qkey = 0;
575 }
576
47605df9
JM		 577 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
578 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
579
580 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
581 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
582
583 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
584 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
585
586 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
587 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
588
8e1a28e8
HHZ		 589 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
590 MLX4_GET(func_cap->phys_port_id, outbox,
591 QUERY_FUNC_CAP_PHYS_PORT_ID);
592
5cc914f1
MA		 593 /* All other resources are allocated by the master, but we still report
594 * 'num' and 'reserved' capabilities as follows:
595 * - num remains the maximum resource index
596 * - 'num - reserved' is the total available objects of a resource, but
597 * resource indices may be less than 'reserved'
598 * TODO: set per-resource quotas */
599
600out:
601 mlx4_free_cmd_mailbox(dev, mailbox);
602
603 return err;
604}
605
225c7b1f
RD		 606int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
607{
608 struct mlx4_cmd_mailbox *mailbox;
609 u32 *outbox;
610 u8 field;
ccf86321 611 u32 field32, flags, ext_flags;
225c7b1f
RD		 612 u16 size;
613 u16 stat_rate;
614 int err;
5ae2a7a8 615 int i;
225c7b1f
RD		 616
617#define QUERY_DEV_CAP_OUT_SIZE 0x100
618#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
619#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
620#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
621#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
622#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
623#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
624#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
625#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
626#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
627#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
628#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
629#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
630#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
631#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
632#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
633#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
634#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
635#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
7ae0e400 636#define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
225c7b1f
RD		 637#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
638#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
639#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 640#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 641#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 642#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
643#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
644#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
645#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
646#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 647#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 648#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
649#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 650#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 651#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 652#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 653#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
654#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
655#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
656#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
657#define QUERY_DEV_CAP_BF_OFFSET 0x4c
658#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
659#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
660#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
661#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
662#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
663#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
664#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
665#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
666#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
667#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
668#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
669#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 670#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
671#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 672#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
3f7fb021 673#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
4de65803 674#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
0ff1fb65
HHZ		 675#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
676#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
77507aa2 677#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
adbc7ac5 678#define QUERY_DEV_CAP_ETH_PROT_CTRL_OFFSET 0x7a
225c7b1f
RD		 679#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
680#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
681#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
682#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
683#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
684#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
685#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
686#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
687#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
688#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 689#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
d475c95b 690#define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
225c7b1f
RD		 691#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
692#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
a53e3e8c 693#define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
955154fa 694#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
7ffdf726 695#define QUERY_DEV_CAP_VXLAN 0x9e
114840c3 696#define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
7d077cd3
MB		 697#define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8
698#define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac
225c7b1f 699
b3416f44 700 dev_cap->flags2 = 0;
225c7b1f
RD		 701 mailbox = mlx4_alloc_cmd_mailbox(dev);
702 if (IS_ERR(mailbox))
703 return PTR_ERR(mailbox);
704 outbox = mailbox->buf;
705
706 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 707 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 708 if (err)
709 goto out;
710
711 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
712 dev_cap->reserved_qps = 1 << (field & 0xf);
713 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
714 dev_cap->max_qps = 1 << (field & 0x1f);
715 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
716 dev_cap->reserved_srqs = 1 << (field >> 4);
717 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
718 dev_cap->max_srqs = 1 << (field & 0x1f);
719 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
720 dev_cap->max_cq_sz = 1 << field;
721 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
722 dev_cap->reserved_cqs = 1 << (field & 0xf);
723 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
724 dev_cap->max_cqs = 1 << (field & 0x1f);
725 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
726 dev_cap->max_mpts = 1 << (field & 0x3f);
727 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
7c68dd43 728 dev_cap->reserved_eqs = 1 << (field & 0xf);
225c7b1f 729 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 730 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 731 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
732 dev_cap->reserved_mtts = 1 << (field >> 4);
733 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
734 dev_cap->max_mrw_sz = 1 << field;
735 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
736 dev_cap->reserved_mrws = 1 << (field & 0xf);
737 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
738 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
7ae0e400
MB		 739 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
740 dev_cap->num_sys_eqs = size & 0xfff;
225c7b1f
RD		 741 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
742 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
743 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
744 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 745 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
746 field &= 0x1f;
747 if (!field)
748 dev_cap->max_gso_sz = 0;
749 else
750 dev_cap->max_gso_sz = 1 << field;
751
b3416f44
SP		 752 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
753 if (field & 0x20)
754 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
755 if (field & 0x10)
756 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
757 field &= 0xf;
758 if (field) {
759 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
760 dev_cap->max_rss_tbl_sz = 1 << field;
761 } else
762 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 763 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
764 dev_cap->max_rdma_global = 1 << (field & 0x3f);
765 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
766 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 767 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 768 dev_cap->num_ports = field & 0xf;
149983af
DB		 769 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
770 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 771 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
772 if (field & 0x80)
773 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
774 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
4de65803
MB		 775 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
776 if (field & 0x80)
777 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
0ff1fb65
HHZ		 778 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
779 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 780 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
781 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 782 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
783 if (field & 0x80)
784 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 785 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 786 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 787 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 788 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
789 dev_cap->reserved_uars = field >> 4;
790 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
791 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
792 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
793 dev_cap->min_page_sz = 1 << field;
794
795 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
796 if (field & 0x80) {
797 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
798 dev_cap->bf_reg_size = 1 << (field & 0x1f);
799 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 800 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 801 field = 3;
225c7b1f 802 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
225c7b1f
RD		 803 } else {
804 dev_cap->bf_reg_size = 0;
225c7b1f
RD		 805 }
806
807 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
808 dev_cap->max_sq_sg = field;
809 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
810 dev_cap->max_sq_desc_sz = size;
811
812 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
813 dev_cap->max_qp_per_mcg = 1 << field;
814 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
815 dev_cap->reserved_mgms = field & 0xf;
816 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
817 dev_cap->max_mcgs = 1 << field;
818 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
819 dev_cap->reserved_pds = field >> 4;
820 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
821 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 822 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
823 dev_cap->reserved_xrcds = field >> 4;
426dd00d 824 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 825 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 826
827 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
828 dev_cap->rdmarc_entry_sz = size;
829 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
830 dev_cap->qpc_entry_sz = size;
831 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
832 dev_cap->aux_entry_sz = size;
833 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
834 dev_cap->altc_entry_sz = size;
835 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
836 dev_cap->eqc_entry_sz = size;
837 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
838 dev_cap->cqc_entry_sz = size;
839 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
840 dev_cap->srq_entry_sz = size;
841 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
842 dev_cap->cmpt_entry_sz = size;
843 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
844 dev_cap->mtt_entry_sz = size;
845 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
846 dev_cap->dmpt_entry_sz = size;
847
848 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
849 dev_cap->max_srq_sz = 1 << field;
850 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
851 dev_cap->max_qp_sz = 1 << field;
852 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
853 dev_cap->resize_srq = field & 1;
854 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
855 dev_cap->max_rq_sg = field;
856 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
857 dev_cap->max_rq_desc_sz = size;
77507aa2 858 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
adbc7ac5
SM		 859 if (field & (1 << 5))
860 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
77507aa2
IS		 861 if (field & (1 << 6))
862 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
863 if (field & (1 << 7))
864 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
225c7b1f
RD		 865 MLX4_GET(dev_cap->bmme_flags, outbox,
866 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
59e14e32
MS		 867 if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP)
868 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP;
d475c95b
MB		 869 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
870 if (field & 0x20)
871 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
225c7b1f
RD		 872 MLX4_GET(dev_cap->reserved_lkey, outbox,
873 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
a53e3e8c
SM		 874 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
875 if (field32 & (1 << 0))
876 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
be6a6b43
JM		 877 if (field32 & (1 << 7))
878 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT;
955154fa
MB		 879 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
880 if (field & 1<<6)
5930e8d0 881 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
7ffdf726
OG		 882 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
883 if (field & 1<<3)
884 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
225c7b1f
RD		 885 MLX4_GET(dev_cap->max_icm_sz, outbox,
886 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 887 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
888 MLX4_GET(dev_cap->max_counters, outbox,
889 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 890
114840c3
JM		 891 MLX4_GET(field32, outbox,
892 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
893 if (field32 & (1 << 0))
894 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
895
7d077cd3
MB		 896 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox,
897 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET);
898 dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK;
899 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox,
900 QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET);
901 dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK;
902
3f7fb021 903 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 904 if (field32 & (1 << 16))
905 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
3f7fb021
RE		 906 if (field32 & (1 << 26))
907 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 908 if (field32 & (1 << 20))
909 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
de966c59
MB		 910 if (field32 & (1 << 21))
911 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
3f7fb021 912
431df8c7
MB		 913 for (i = 1; i <= dev_cap->num_ports; i++) {
914 err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i);
915 if (err)
916 goto out;
5ae2a7a8
RD		 917 }
918
225c7b1f
RD		 919 /*
920 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
921 * we can't use any EQs whose doorbell falls on that page,
922 * even if the EQ itself isn't reserved.
923 */
7ae0e400
MB		 924 if (dev_cap->num_sys_eqs == 0)
925 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
926 dev_cap->reserved_eqs);
927 else
928 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
225c7b1f 929
c78e25ed
OG		 930out:
931 mlx4_free_cmd_mailbox(dev, mailbox);
932 return err;
933}
934
935void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
936{
937 if (dev_cap->bf_reg_size > 0)
938 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
939 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
940 else
941 mlx4_dbg(dev, "BlueFlame not available\n");
942
943 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
944 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 945 mlx4_dbg(dev, "Max ICM size %lld MB\n",
946 (unsigned long long) dev_cap->max_icm_sz >> 20);
947 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
948 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
949 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
950 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
951 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
952 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
7ae0e400
MB		 953 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
954 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
955 dev_cap->eqc_entry_sz);
225c7b1f
RD		 956 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
957 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
958 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
959 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
960 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
961 dev_cap->max_pds, dev_cap->reserved_mgms);
962 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
963 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
964 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
431df8c7
MB		 965 dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu,
966 dev_cap->port_cap[1].max_port_width);
225c7b1f
RD		 967 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
968 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
969 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
970 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 971 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 972 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 973 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
7d077cd3
MB		 974 mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n",
975 dev_cap->dmfs_high_rate_qpn_base);
976 mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n",
977 dev_cap->dmfs_high_rate_qpn_range);
225c7b1f 978 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 979 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 980}
981
431df8c7
MB		 982int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap)
983{
984 struct mlx4_cmd_mailbox *mailbox;
985 u32 *outbox;
986 u8 field;
987 u32 field32;
988 int err;
989
990 mailbox = mlx4_alloc_cmd_mailbox(dev);
991 if (IS_ERR(mailbox))
992 return PTR_ERR(mailbox);
993 outbox = mailbox->buf;
994
995 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
996 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
997 MLX4_CMD_TIME_CLASS_A,
998 MLX4_CMD_NATIVE);
999
1000 if (err)
1001 goto out;
1002
1003 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
1004 port_cap->max_vl = field >> 4;
1005 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
1006 port_cap->ib_mtu = field >> 4;
1007 port_cap->max_port_width = field & 0xf;
1008 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
1009 port_cap->max_gids = 1 << (field & 0xf);
1010 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
1011 port_cap->max_pkeys = 1 << (field & 0xf);
1012 } else {
1013#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
1014#define QUERY_PORT_MTU_OFFSET 0x01
1015#define QUERY_PORT_ETH_MTU_OFFSET 0x02
1016#define QUERY_PORT_WIDTH_OFFSET 0x06
1017#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
1018#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
1019#define QUERY_PORT_MAX_VL_OFFSET 0x0b
1020#define QUERY_PORT_MAC_OFFSET 0x10
1021#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
1022#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
1023#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
1024
1025 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT,
1026 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1027 if (err)
1028 goto out;
1029
1030 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1031 port_cap->supported_port_types = field & 3;
1032 port_cap->suggested_type = (field >> 3) & 1;
1033 port_cap->default_sense = (field >> 4) & 1;
7d077cd3 1034 port_cap->dmfs_optimized_state = (field >> 5) & 1;
431df8c7
MB		 1035 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
1036 port_cap->ib_mtu = field & 0xf;
1037 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
1038 port_cap->max_port_width = field & 0xf;
1039 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
1040 port_cap->max_gids = 1 << (field >> 4);
1041 port_cap->max_pkeys = 1 << (field & 0xf);
1042 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
1043 port_cap->max_vl = field & 0xf;
1044 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
1045 port_cap->log_max_macs = field & 0xf;
1046 port_cap->log_max_vlans = field >> 4;
1047 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);
1048 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);
1049 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
1050 port_cap->trans_type = field32 >> 24;
1051 port_cap->vendor_oui = field32 & 0xffffff;
1052 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);
1053 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);
1054 }
1055
1056out:
1057 mlx4_free_cmd_mailbox(dev, mailbox);
1058 return err;
1059}
1060
383677da
OG		 1061#define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
1062#define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
1063#define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
1064
b91cb3eb
JM		 1065int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
1066 struct mlx4_vhcr *vhcr,
1067 struct mlx4_cmd_mailbox *inbox,
1068 struct mlx4_cmd_mailbox *outbox,
1069 struct mlx4_cmd_info *cmd)
1070{
2a4fae14 1071 u64 flags;
b91cb3eb
JM		 1072 int err = 0;
1073 u8 field;
383677da 1074 u32 bmme_flags, field32;
449fc488
MB		 1075 int real_port;
1076 int slave_port;
1077 int first_port;
1078 struct mlx4_active_ports actv_ports;
b91cb3eb
JM		 1079
1080 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1081 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1082 if (err)
1083 return err;
1084
cc1ade94
SM		 1085 /* add port mng change event capability and disable mw type 1
1086 * unconditionally to slaves
1087 */
2a4fae14
JM		 1088 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1089 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 1090 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
449fc488
MB		 1091 actv_ports = mlx4_get_active_ports(dev, slave);
1092 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
1093 for (slave_port = 0, real_port = first_port;
1094 real_port < first_port +
1095 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
1096 ++real_port, ++slave_port) {
1097 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
1098 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
1099 else
1100 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1101 }
1102 for (; slave_port < dev->caps.num_ports; ++slave_port)
1103 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
2a4fae14
JM		 1104 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1105
449fc488
MB		 1106 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1107 field &= ~0x0F;
1108 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1109 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1110
30b40c31
AV		 1111 /* For guests, disable timestamp */
1112 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1113 field &= 0x7f;
1114 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1115
7ffdf726 1116 /* For guests, disable vxlan tunneling */
57352ef4 1117 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
7ffdf726
OG		 1118 field &= 0xf7;
1119 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1120
b91cb3eb
JM		 1121 /* For guests, report Blueflame disabled */
1122 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1123 field &= 0x7f;
1124 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1125
59e14e32 1126 /* For guests, disable mw type 2 and port remap*/
57352ef4 1127 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
cc1ade94 1128 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
59e14e32 1129 bmme_flags &= ~MLX4_FLAG_PORT_REMAP;
cc1ade94
SM		 1130 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1131
0081c8f3
JM		 1132 /* turn off device-managed steering capability if not enabled */
1133 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1134 MLX4_GET(field, outbox->buf,
1135 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1136 field &= 0x7f;
1137 MLX4_PUT(outbox->buf, field,
1138 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1139 }
4de65803
MB		 1140
1141 /* turn off ipoib managed steering for guests */
57352ef4 1142 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
4de65803
MB		 1143 field &= ~0x80;
1144 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1145
383677da
OG		 1146 /* turn off host side virt features (VST, FSM, etc) for guests */
1147 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1148 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS |
1149 DEV_CAP_EXT_2_FLAG_FSM);
1150 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1151
b91cb3eb
JM		 1152 return 0;
1153}
1154
5cc914f1
MA		 1155int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1156 struct mlx4_vhcr *vhcr,
1157 struct mlx4_cmd_mailbox *inbox,
1158 struct mlx4_cmd_mailbox *outbox,
1159 struct mlx4_cmd_info *cmd)
1160{
0eb62b93 1161 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 1162 u64 def_mac;
1163 u8 port_type;
6634961c 1164 u16 short_field;
5cc914f1 1165 int err;
948e306d 1166 int admin_link_state;
449fc488
MB		 1167 int port = mlx4_slave_convert_port(dev, slave,
1168 vhcr->in_modifier & 0xFF);
5cc914f1 1169
105c320f 1170#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 1171#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 1172#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1173#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 1174
449fc488
MB		 1175 if (port < 0)
1176 return -EINVAL;
1177
a7401b9c
JM		 1178 /* Protect against untrusted guests: enforce that this is the
1179 * QUERY_PORT general query.
1180 */
1181 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
1182 return -EINVAL;
1183
1184 vhcr->in_modifier = port;
449fc488 1185
5cc914f1
MA		 1186 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1187 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1188 MLX4_CMD_NATIVE);
1189
1190 if (!err && dev->caps.function != slave) {
0508ad64 1191 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 1192 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1193
1194 /* get port type - currently only eth is enabled */
1195 MLX4_GET(port_type, outbox->buf,
1196 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1197
105c320f
JM		 1198 /* No link sensing allowed */
1199 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1200 /* set port type to currently operating port type */
1201 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 1202
948e306d
RE		 1203 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1204 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1205 port_type |= MLX4_PORT_LINK_UP_MASK;
1206 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1207 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1208
5cc914f1
MA		 1209 MLX4_PUT(outbox->buf, port_type,
1210 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c 1211
b6ffaeff 1212 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
449fc488 1213 short_field = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 1214 else
1215 short_field = 1; /* slave max gids */
6634961c
JM		 1216 MLX4_PUT(outbox->buf, short_field,
1217 QUERY_PORT_CUR_MAX_GID_OFFSET);
1218
1219 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1220 MLX4_PUT(outbox->buf, short_field,
1221 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 1222 }
1223
1224 return err;
1225}
1226
6634961c
JM		 1227int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1228 int *gid_tbl_len, int *pkey_tbl_len)
1229{
1230 struct mlx4_cmd_mailbox *mailbox;
1231 u32 *outbox;
1232 u16 field;
1233 int err;
1234
1235 mailbox = mlx4_alloc_cmd_mailbox(dev);
1236 if (IS_ERR(mailbox))
1237 return PTR_ERR(mailbox);
1238
1239 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1240 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1241 MLX4_CMD_WRAPPED);
1242 if (err)
1243 goto out;
1244
1245 outbox = mailbox->buf;
1246
1247 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1248 *gid_tbl_len = field;
1249
1250 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1251 *pkey_tbl_len = field;
1252
1253out:
1254 mlx4_free_cmd_mailbox(dev, mailbox);
1255 return err;
1256}
1257EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1258
225c7b1f
RD		 1259int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1260{
1261 struct mlx4_cmd_mailbox *mailbox;
1262 struct mlx4_icm_iter iter;
1263 __be64 *pages;
1264 int lg;
1265 int nent = 0;
1266 int i;
1267 int err = 0;
1268 int ts = 0, tc = 0;
1269
1270 mailbox = mlx4_alloc_cmd_mailbox(dev);
1271 if (IS_ERR(mailbox))
1272 return PTR_ERR(mailbox);
225c7b1f
RD		 1273 pages = mailbox->buf;
1274
1275 for (mlx4_icm_first(icm, &iter);
1276 !mlx4_icm_last(&iter);
1277 mlx4_icm_next(&iter)) {
1278 /*
1279 * We have to pass pages that are aligned to their
1280 * size, so find the least significant 1 in the
1281 * address or size and use that as our log2 size.
1282 */
1283 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1284 if (lg < MLX4_ICM_PAGE_SHIFT) {
1a91de28
JP		 1285 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1286 MLX4_ICM_PAGE_SIZE,
1287 (unsigned long long) mlx4_icm_addr(&iter),
1288 mlx4_icm_size(&iter));
225c7b1f
RD		 1289 err = -EINVAL;
1290 goto out;
1291 }
1292
1293 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1294 if (virt != -1) {
1295 pages[nent * 2] = cpu_to_be64(virt);
1296 virt += 1 << lg;
1297 }
1298
1299 pages[nent * 2 + 1] =
1300 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1301 (lg - MLX4_ICM_PAGE_SHIFT));
1302 ts += 1 << (lg - 10);
1303 ++tc;
1304
1305 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1306 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 1307 MLX4_CMD_TIME_CLASS_B,
1308 MLX4_CMD_NATIVE);
225c7b1f
RD		 1309 if (err)
1310 goto out;
1311 nent = 0;
1312 }
1313 }
1314 }
1315
1316 if (nent)
f9baff50
JM		 1317 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1318 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1319 if (err)
1320 goto out;
1321
1322 switch (op) {
1323 case MLX4_CMD_MAP_FA:
1a91de28 1324 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
225c7b1f
RD		 1325 break;
1326 case MLX4_CMD_MAP_ICM_AUX:
1a91de28 1327 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
225c7b1f
RD		 1328 break;
1329 case MLX4_CMD_MAP_ICM:
1a91de28
JP		 1330 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1331 tc, ts, (unsigned long long) virt - (ts << 10));
225c7b1f
RD		 1332 break;
1333 }
1334
1335out:
1336 mlx4_free_cmd_mailbox(dev, mailbox);
1337 return err;
1338}
1339
1340int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1341{
1342 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1343}
1344
1345int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1346{
f9baff50
JM		 1347 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1348 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1349}
1350
1351
1352int mlx4_RUN_FW(struct mlx4_dev *dev)
1353{
f9baff50
JM		 1354 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1355 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1356}
1357
1358int mlx4_QUERY_FW(struct mlx4_dev *dev)
1359{
1360 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1361 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1362 struct mlx4_cmd_mailbox *mailbox;
1363 u32 *outbox;
1364 int err = 0;
1365 u64 fw_ver;
fe40900f 1366 u16 cmd_if_rev;
225c7b1f
RD		 1367 u8 lg;
1368
1369#define QUERY_FW_OUT_SIZE 0x100
1370#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1371#define QUERY_FW_PPF_ID 0x09
fe40900f 1372#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1373#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1374#define QUERY_FW_ERR_START_OFFSET 0x30
1375#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1376#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1377
1378#define QUERY_FW_SIZE_OFFSET 0x00
1379#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1380#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1381
5cc914f1
MA		 1382#define QUERY_FW_COMM_BASE_OFFSET 0x40
1383#define QUERY_FW_COMM_BAR_OFFSET 0x48
1384
ddd8a6c1
EE		 1385#define QUERY_FW_CLOCK_OFFSET 0x50
1386#define QUERY_FW_CLOCK_BAR 0x58
1387
225c7b1f
RD		 1388 mailbox = mlx4_alloc_cmd_mailbox(dev);
1389 if (IS_ERR(mailbox))
1390 return PTR_ERR(mailbox);
1391 outbox = mailbox->buf;
1392
1393 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1394 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1395 if (err)
1396 goto out;
1397
1398 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1399 /*
3e1db334 1400 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1401 * version, so swap here.
1402 */
1403 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1404 ((fw_ver & 0xffff0000ull) >> 16) |
1405 ((fw_ver & 0x0000ffffull) << 16);
1406
752a50ca
JM		 1407 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1408 dev->caps.function = lg;
1409
b91cb3eb
JM		 1410 if (mlx4_is_slave(dev))
1411 goto out;
1412
5cc914f1 1413
fe40900f 1414 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1415 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1416 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1a91de28 1417 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
fe40900f
RD		 1418 cmd_if_rev);
1419 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1420 (int) (dev->caps.fw_ver >> 32),
1421 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1422 (int) dev->caps.fw_ver & 0xffff);
1a91de28 1423 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
5ae2a7a8 1424 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1425 err = -ENODEV;
1426 goto out;
1427 }
1428
5ae2a7a8
RD		 1429 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1430 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1431
225c7b1f
RD		 1432 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1433 cmd->max_cmds = 1 << lg;
1434
fe40900f 1435 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1436 (int) (dev->caps.fw_ver >> 32),
1437 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1438 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1439 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1440
1441 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1442 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1443 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1444 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1445
1446 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1447 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1448
1449 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1450 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1451 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1452 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1453
5cc914f1
MA		 1454 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1455 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1456 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1457 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1458 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1459 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1460
ddd8a6c1
EE		 1461 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1462 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1463 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1464 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1465 fw->clock_bar, fw->clock_offset);
1466
225c7b1f
RD		 1467 /*
1468 * Round up number of system pages needed in case
1469 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1470 */
1471 fw->fw_pages =
1472 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1473 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1474
1475 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1476 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1477
1478out:
1479 mlx4_free_cmd_mailbox(dev, mailbox);
1480 return err;
1481}
1482
b91cb3eb
JM		 1483int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1484 struct mlx4_vhcr *vhcr,
1485 struct mlx4_cmd_mailbox *inbox,
1486 struct mlx4_cmd_mailbox *outbox,
1487 struct mlx4_cmd_info *cmd)
1488{
1489 u8 *outbuf;
1490 int err;
1491
1492 outbuf = outbox->buf;
1493 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1494 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1495 if (err)
1496 return err;
1497
752a50ca
JM		 1498 /* for slaves, set pci PPF ID to invalid and zero out everything
1499 * else except FW version */
b91cb3eb
JM		 1500 outbuf[0] = outbuf[1] = 0;
1501 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1502 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1503
b91cb3eb
JM		 1504 return 0;
1505}
1506
225c7b1f
RD		 1507static void get_board_id(void *vsd, char *board_id)
1508{
1509 int i;
1510
1511#define VSD_OFFSET_SIG1 0x00
1512#define VSD_OFFSET_SIG2 0xde
1513#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1514#define VSD_OFFSET_TS_BOARD_ID 0x20
1515
1516#define VSD_SIGNATURE_TOPSPIN 0x5ad
1517
1518 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1519
1520 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1521 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1522 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1523 } else {
1524 /*
1525 * The board ID is a string but the firmware byte
1526 * swaps each 4-byte word before passing it back to
1527 * us. Therefore we need to swab it before printing.
1528 */
1529 for (i = 0; i < 4; ++i)
1530 ((u32 *) board_id)[i] =
1531 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1532 }
1533}
1534
1535int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1536{
1537 struct mlx4_cmd_mailbox *mailbox;
1538 u32 *outbox;
1539 int err;
1540
1541#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1542#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1543#define QUERY_ADAPTER_VSD_OFFSET 0x20
1544
1545 mailbox = mlx4_alloc_cmd_mailbox(dev);
1546 if (IS_ERR(mailbox))
1547 return PTR_ERR(mailbox);
1548 outbox = mailbox->buf;
1549
1550 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1551 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1552 if (err)
1553 goto out;
1554
225c7b1f
RD		 1555 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1556
1557 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1558 adapter->board_id);
1559
1560out:
1561 mlx4_free_cmd_mailbox(dev, mailbox);
1562 return err;
1563}
1564
1565int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1566{
1567 struct mlx4_cmd_mailbox *mailbox;
1568 __be32 *inbox;
1569 int err;
7d077cd3
MB		 1570 static const u8 a0_dmfs_hw_steering[] = {
1571 [MLX4_STEERING_DMFS_A0_DEFAULT] = 0,
1572 [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1,
1573 [MLX4_STEERING_DMFS_A0_STATIC] = 2,
1574 [MLX4_STEERING_DMFS_A0_DISABLE] = 3
1575 };
225c7b1f
RD		 1576
1577#define INIT_HCA_IN_SIZE 0x200
1578#define INIT_HCA_VERSION_OFFSET 0x000
1579#define INIT_HCA_VERSION 2
7ffdf726 1580#define INIT_HCA_VXLAN_OFFSET 0x0c
c57e20dc 1581#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f 1582#define INIT_HCA_FLAGS_OFFSET 0x014
be6a6b43 1583#define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018
225c7b1f
RD		 1584#define INIT_HCA_QPC_OFFSET 0x020
1585#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1586#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1587#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1588#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1589#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1590#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1591#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
77507aa2 1592#define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
225c7b1f
RD		 1593#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1594#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1595#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1596#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
7ae0e400 1597#define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
225c7b1f
RD		 1598#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1599#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1600#define INIT_HCA_MCAST_OFFSET 0x0c0
1601#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1602#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1603#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1604#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1605#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1606#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1607#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1608#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1609#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
7d077cd3 1610#define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18)
0ff1fb65
HHZ		 1611#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1612#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1613#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1614#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1615#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1616#define INIT_HCA_TPT_OFFSET 0x0f0
1617#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1618#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1619#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1620#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1621#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1622#define INIT_HCA_UAR_OFFSET 0x120
1623#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1624#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1625
1626 mailbox = mlx4_alloc_cmd_mailbox(dev);
1627 if (IS_ERR(mailbox))
1628 return PTR_ERR(mailbox);
1629 inbox = mailbox->buf;
1630
225c7b1f
RD		 1631 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1632
c57e20dc
EC		 1633 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1634 (ilog2(cache_line_size()) - 4) << 5;
1635
225c7b1f
RD		 1636#if defined(__LITTLE_ENDIAN)
1637 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1638#elif defined(__BIG_ENDIAN)
1639 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1640#else
1641#error Host endianness not defined
1642#endif
1643 /* Check port for UD address vector: */
1644 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1645
8ff095ec
EC		 1646 /* Enable IPoIB checksumming if we can: */
1647 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1648 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1649
51f5f0ee
JM		 1650 /* Enable QoS support if module parameter set */
1651 if (enable_qos)
1652 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1653
f2a3f6a3
OG		 1654 /* enable counters */
1655 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1656 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1657
08ff3235
OG		 1658 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1659 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1660 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1661 dev->caps.eqe_size = 64;
1662 dev->caps.eqe_factor = 1;
1663 } else {
1664 dev->caps.eqe_size = 32;
1665 dev->caps.eqe_factor = 0;
1666 }
1667
1668 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1669 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1670 dev->caps.cqe_size = 64;
77507aa2 1671 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1672 } else {
1673 dev->caps.cqe_size = 32;
1674 }
1675
77507aa2
IS		 1676 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1677 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1678 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1679 dev->caps.eqe_size = cache_line_size();
1680 dev->caps.cqe_size = cache_line_size();
1681 dev->caps.eqe_factor = 0;
1682 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1683 (ilog2(dev->caps.eqe_size) - 5)),
1684 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1685
1686 /* User still need to know to support CQE > 32B */
1687 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1688 }
1689
be6a6b43
JM		 1690 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT)
1691 *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31);
1692
225c7b1f
RD		 1693 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1694
1695 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1696 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1697 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1698 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1699 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1700 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1701 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1702 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1703 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1704 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1705 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
225c7b1f
RD		 1706 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1707 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1708
0ff1fb65
HHZ		 1709 /* steering attributes */
1710 if (dev->caps.steering_mode ==
1711 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1712 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1713 cpu_to_be32(1 <<
1714 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1715
1716 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1717 MLX4_PUT(inbox, param->log_mc_entry_sz,
1718 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1719 MLX4_PUT(inbox, param->log_mc_table_sz,
1720 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1721 /* Enable Ethernet flow steering
1722 * with udp unicast and tcp unicast
1723 */
7d077cd3
MB		 1724 if (dev->caps.dmfs_high_steer_mode !=
1725 MLX4_STEERING_DMFS_A0_STATIC)
1726 MLX4_PUT(inbox,
1727 (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
1728 INIT_HCA_FS_ETH_BITS_OFFSET);
0ff1fb65
HHZ		 1729 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1730 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1731 /* Enable IPoIB flow steering
1732 * with udp unicast and tcp unicast
1733 */
23537b73 1734 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1735 INIT_HCA_FS_IB_BITS_OFFSET);
1736 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1737 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
7d077cd3
MB		 1738
1739 if (dev->caps.dmfs_high_steer_mode !=
1740 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
1741 MLX4_PUT(inbox,
1742 ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode]
1743 << 6)),
1744 INIT_HCA_FS_A0_OFFSET);
0ff1fb65
HHZ		 1745 } else {
1746 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1747 MLX4_PUT(inbox, param->log_mc_entry_sz,
1748 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1749 MLX4_PUT(inbox, param->log_mc_hash_sz,
1750 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1751 MLX4_PUT(inbox, param->log_mc_table_sz,
1752 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1753 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1754 MLX4_PUT(inbox, (u8) (1 << 3),
1755 INIT_HCA_UC_STEERING_OFFSET);
1756 }
225c7b1f
RD		 1757
1758 /* TPT attributes */
1759
1760 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1761 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1762 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1763 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1764 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1765
1766 /* UAR attributes */
1767
ab9c17a0 1768 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1769 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1770
7ffdf726
OG		 1771 /* set parser VXLAN attributes */
1772 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1773 u8 parser_params = 0;
1774 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1775 }
1776
5a031086
JM		 1777 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA,
1778 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
225c7b1f
RD		 1779
1780 if (err)
1781 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1782
1783 mlx4_free_cmd_mailbox(dev, mailbox);
1784 return err;
1785}
1786
ab9c17a0
JM		 1787int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1788 struct mlx4_init_hca_param *param)
1789{
1790 struct mlx4_cmd_mailbox *mailbox;
1791 __be32 *outbox;
7b8157be 1792 u32 dword_field;
ab9c17a0 1793 int err;
08ff3235 1794 u8 byte_field;
7d077cd3
MB		 1795 static const u8 a0_dmfs_query_hw_steering[] = {
1796 [0] = MLX4_STEERING_DMFS_A0_DEFAULT,
1797 [1] = MLX4_STEERING_DMFS_A0_DYNAMIC,
1798 [2] = MLX4_STEERING_DMFS_A0_STATIC,
1799 [3] = MLX4_STEERING_DMFS_A0_DISABLE
1800 };
ab9c17a0
JM		 1801
1802#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1803#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1804
1805 mailbox = mlx4_alloc_cmd_mailbox(dev);
1806 if (IS_ERR(mailbox))
1807 return PTR_ERR(mailbox);
1808 outbox = mailbox->buf;
1809
1810 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1811 MLX4_CMD_QUERY_HCA,
1812 MLX4_CMD_TIME_CLASS_B,
1813 !mlx4_is_slave(dev));
1814 if (err)
1815 goto out;
1816
1817 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1818 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1819
1820 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1821
1822 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1823 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1824 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1825 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1826 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1827 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1828 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1829 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1830 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1831 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1832 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
ab9c17a0
JM		 1833 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1834 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1835
7b8157be
JM		 1836 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1837 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1838 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1839 } else {
1840 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1841 if (byte_field & 0x8)
1842 param->steering_mode = MLX4_STEERING_MODE_B0;
1843 else
1844 param->steering_mode = MLX4_STEERING_MODE_A0;
1845 }
0ff1fb65 1846 /* steering attributes */
7b8157be 1847 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1848 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1849 MLX4_GET(param->log_mc_entry_sz, outbox,
1850 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1851 MLX4_GET(param->log_mc_table_sz, outbox,
1852 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
7d077cd3
MB		 1853 MLX4_GET(byte_field, outbox,
1854 INIT_HCA_FS_A0_OFFSET);
1855 param->dmfs_high_steer_mode =
1856 a0_dmfs_query_hw_steering[(byte_field >> 6) & 3];
0ff1fb65
HHZ		 1857 } else {
1858 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1859 MLX4_GET(param->log_mc_entry_sz, outbox,
1860 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1861 MLX4_GET(param->log_mc_hash_sz, outbox,
1862 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1863 MLX4_GET(param->log_mc_table_sz, outbox,
1864 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1865 }
ab9c17a0 1866
08ff3235
OG		 1867 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1868 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1869 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1870 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1871 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1872 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1873
77507aa2
IS		 1874 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1875 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1876 if (byte_field) {
c3f2511f
IS		 1877 param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED;
1878 param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED;
77507aa2
IS		 1879 param->cqe_size = 1 << ((byte_field &
1880 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
1881 param->eqe_size = 1 << (((byte_field &
1882 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
1883 }
1884
ab9c17a0
JM		 1885 /* TPT attributes */
1886
1887 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1888 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1889 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1890 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1891 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1892
1893 /* UAR attributes */
1894
1895 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1896 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1897
1898out:
1899 mlx4_free_cmd_mailbox(dev, mailbox);
1900
1901 return err;
1902}
1903
6d6e996c
MD		 1904static int mlx4_hca_core_clock_update(struct mlx4_dev *dev)
1905{
1906 struct mlx4_cmd_mailbox *mailbox;
1907 __be32 *outbox;
1908 int err;
1909
1910 mailbox = mlx4_alloc_cmd_mailbox(dev);
1911 if (IS_ERR(mailbox)) {
1912 mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n");
1913 return PTR_ERR(mailbox);
1914 }
1915 outbox = mailbox->buf;
1916
1917 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1918 MLX4_CMD_QUERY_HCA,
1919 MLX4_CMD_TIME_CLASS_B,
1920 !mlx4_is_slave(dev));
1921 if (err) {
1922 mlx4_warn(dev, "hca_core_clock update failed\n");
1923 goto out;
1924 }
1925
1926 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
1927
1928out:
1929 mlx4_free_cmd_mailbox(dev, mailbox);
1930
1931 return err;
1932}
1933
980e9001
JM		 1934/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1935 * and real QP0 are active, so that the paravirtualized QP0 is ready
1936 * to operate */
1937static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1938{
1939 struct mlx4_priv *priv = mlx4_priv(dev);
1940 /* irrelevant if not infiniband */
1941 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1942 priv->mfunc.master.qp0_state[port].qp0_active)
1943 return 1;
1944 return 0;
1945}
1946
5cc914f1
MA		 1947int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1948 struct mlx4_vhcr *vhcr,
1949 struct mlx4_cmd_mailbox *inbox,
1950 struct mlx4_cmd_mailbox *outbox,
1951 struct mlx4_cmd_info *cmd)
1952{
1953 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1954 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1955 int err;
1956
449fc488
MB		 1957 if (port < 0)
1958 return -EINVAL;
1959
5cc914f1
MA		 1960 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1961 return 0;
1962
980e9001
JM		 1963 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1964 /* Enable port only if it was previously disabled */
1965 if (!priv->mfunc.master.init_port_ref[port]) {
1966 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1967 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1968 if (err)
1969 return err;
1970 }
1971 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1972 } else {
1973 if (slave == mlx4_master_func_num(dev)) {
1974 if (check_qp0_state(dev, slave, port) &&
1975 !priv->mfunc.master.qp0_state[port].port_active) {
1976 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1977 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1978 if (err)
1979 return err;
1980 priv->mfunc.master.qp0_state[port].port_active = 1;
1981 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1982 }
1983 } else
1984 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1985 }
1986 ++priv->mfunc.master.init_port_ref[port];
1987 return 0;
1988}
1989
5ae2a7a8 1990int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1991{
1992 struct mlx4_cmd_mailbox *mailbox;
1993 u32 *inbox;
1994 int err;
1995 u32 flags;
5ae2a7a8 1996 u16 field;
225c7b1f 1997
5ae2a7a8 1998 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1999#define INIT_PORT_IN_SIZE 256
2000#define INIT_PORT_FLAGS_OFFSET 0x00
2001#define INIT_PORT_FLAG_SIG (1 << 18)
2002#define INIT_PORT_FLAG_NG (1 << 17)
2003#define INIT_PORT_FLAG_G0 (1 << 16)
2004#define INIT_PORT_VL_SHIFT 4
2005#define INIT_PORT_PORT_WIDTH_SHIFT 8
2006#define INIT_PORT_MTU_OFFSET 0x04
2007#define INIT_PORT_MAX_GID_OFFSET 0x06
2008#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
2009#define INIT_PORT_GUID0_OFFSET 0x10
2010#define INIT_PORT_NODE_GUID_OFFSET 0x18
2011#define INIT_PORT_SI_GUID_OFFSET 0x20
2012
5ae2a7a8
RD		 2013 mailbox = mlx4_alloc_cmd_mailbox(dev);
2014 if (IS_ERR(mailbox))
2015 return PTR_ERR(mailbox);
2016 inbox = mailbox->buf;
225c7b1f 2017
5ae2a7a8
RD		 2018 flags = 0;
2019 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
2020 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
2021 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 2022
b79acb49 2023 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 2024 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
2025 field = dev->caps.gid_table_len[port];
2026 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
2027 field = dev->caps.pkey_table_len[port];
2028 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 2029
5ae2a7a8 2030 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 2031 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 2032
5ae2a7a8
RD		 2033 mlx4_free_cmd_mailbox(dev, mailbox);
2034 } else
2035 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 2036 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f 2037
6d6e996c
MD		 2038 if (!err)
2039 mlx4_hca_core_clock_update(dev);
2040
225c7b1f
RD		 2041 return err;
2042}
2043EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
2044
5cc914f1
MA		 2045int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
2046 struct mlx4_vhcr *vhcr,
2047 struct mlx4_cmd_mailbox *inbox,
2048 struct mlx4_cmd_mailbox *outbox,
2049 struct mlx4_cmd_info *cmd)
2050{
2051 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 2052 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 2053 int err;
2054
449fc488
MB		 2055 if (port < 0)
2056 return -EINVAL;
2057
5cc914f1
MA		 2058 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
2059 (1 << port)))
2060 return 0;
2061
980e9001
JM		 2062 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
2063 if (priv->mfunc.master.init_port_ref[port] == 1) {
2064 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
5a031086 2065 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
980e9001
JM		 2066 if (err)
2067 return err;
2068 }
2069 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2070 } else {
2071 /* infiniband port */
2072 if (slave == mlx4_master_func_num(dev)) {
2073 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
2074 priv->mfunc.master.qp0_state[port].port_active) {
2075 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
5a031086 2076 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
980e9001
JM		 2077 if (err)
2078 return err;
2079 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
2080 priv->mfunc.master.qp0_state[port].port_active = 0;
2081 }
2082 } else
2083 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 2084 }
5cc914f1
MA		 2085 --priv->mfunc.master.init_port_ref[port];
2086 return 0;
2087}
2088
225c7b1f
RD		 2089int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
2090{
5a031086
JM		 2091 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
2092 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 2093}
2094EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
2095
2096int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
2097{
5a031086
JM		 2098 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA,
2099 MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
225c7b1f
RD		 2100}
2101
d18f141a
OG		 2102struct mlx4_config_dev {
2103 __be32 update_flags;
d475c95b 2104 __be32 rsvd1[3];
d18f141a
OG		 2105 __be16 vxlan_udp_dport;
2106 __be16 rsvd2;
59e14e32
MS		 2107 __be32 rsvd3;
2108 __be32 roce_flags;
2109 __be32 rsvd4[25];
2110 __be16 rsvd5;
2111 u8 rsvd6;
d475c95b 2112 u8 rx_checksum_val;
d18f141a
OG		 2113};
2114
2115#define MLX4_VXLAN_UDP_DPORT (1 << 0)
59e14e32 2116#define MLX4_DISABLE_RX_PORT BIT(18)
d18f141a 2117
d475c95b 2118static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
d18f141a
OG		 2119{
2120 int err;
2121 struct mlx4_cmd_mailbox *mailbox;
2122
2123 mailbox = mlx4_alloc_cmd_mailbox(dev);
2124 if (IS_ERR(mailbox))
2125 return PTR_ERR(mailbox);
2126
2127 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
2128
2129 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
2130 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2131
2132 mlx4_free_cmd_mailbox(dev, mailbox);
2133 return err;
2134}
2135
d475c95b
MB		 2136static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2137{
2138 int err;
2139 struct mlx4_cmd_mailbox *mailbox;
2140
2141 mailbox = mlx4_alloc_cmd_mailbox(dev);
2142 if (IS_ERR(mailbox))
2143 return PTR_ERR(mailbox);
2144
2145 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV,
2146 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2147
2148 if (!err)
2149 memcpy(config_dev, mailbox->buf, sizeof(*config_dev));
2150
2151 mlx4_free_cmd_mailbox(dev, mailbox);
2152 return err;
2153}
2154
2155/* Conversion between the HW values and the actual functionality.
2156 * The value represented by the array index,
2157 * and the functionality determined by the flags.
2158 */
2159static const u8 config_dev_csum_flags[] = {
2160 [0] = 0,
2161 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP,
2162 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP |
2163 MLX4_RX_CSUM_MODE_L4,
2164 [3] = MLX4_RX_CSUM_MODE_L4 |
2165 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP |
2166 MLX4_RX_CSUM_MODE_MULTI_VLAN
2167};
2168
2169int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
2170 struct mlx4_config_dev_params *params)
2171{
2172 struct mlx4_config_dev config_dev;
2173 int err;
2174 u8 csum_mask;
2175
2176#define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2177#define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2178#define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2179
2180 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2181 return -ENOTSUPP;
2182
2183 err = mlx4_CONFIG_DEV_get(dev, &config_dev);
2184 if (err)
2185 return err;
2186
2187 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) &
2188 CONFIG_DEV_RX_CSUM_MODE_MASK;
2189
2190 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2191 return -EINVAL;
2192 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask];
2193
2194 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) &
2195 CONFIG_DEV_RX_CSUM_MODE_MASK;
2196
2197 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2198 return -EINVAL;
2199 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask];
2200
2201 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport);
2202
2203 return 0;
2204}
2205EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval);
2206
d18f141a
OG		 2207int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
2208{
2209 struct mlx4_config_dev config_dev;
2210
2211 memset(&config_dev, 0, sizeof(config_dev));
2212 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
2213 config_dev.vxlan_udp_dport = udp_port;
2214
d475c95b 2215 return mlx4_CONFIG_DEV_set(dev, &config_dev);
d18f141a
OG		 2216}
2217EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
2218
59e14e32
MS		 2219#define CONFIG_DISABLE_RX_PORT BIT(15)
2220int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis)
2221{
2222 struct mlx4_config_dev config_dev;
2223
2224 memset(&config_dev, 0, sizeof(config_dev));
2225 config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT);
2226 if (dis)
2227 config_dev.roce_flags =
2228 cpu_to_be32(CONFIG_DISABLE_RX_PORT);
2229
2230 return mlx4_CONFIG_DEV_set(dev, &config_dev);
2231}
2232
2233int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2)
2234{
2235 struct mlx4_cmd_mailbox *mailbox;
2236 struct {
2237 __be32 v_port1;
2238 __be32 v_port2;
2239 } *v2p;
2240 int err;
2241
2242 mailbox = mlx4_alloc_cmd_mailbox(dev);
2243 if (IS_ERR(mailbox))
2244 return -ENOMEM;
2245
2246 v2p = mailbox->buf;
2247 v2p->v_port1 = cpu_to_be32(port1);
2248 v2p->v_port2 = cpu_to_be32(port2);
2249
2250 err = mlx4_cmd(dev, mailbox->dma, 0,
2251 MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP,
2252 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2253
2254 mlx4_free_cmd_mailbox(dev, mailbox);
2255 return err;
2256}
2257
d18f141a 2258
225c7b1f
RD		 2259int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
2260{
2261 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
2262 MLX4_CMD_SET_ICM_SIZE,
f9baff50 2263 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 2264 if (ret)
2265 return ret;
2266
2267 /*
2268 * Round up number of system pages needed in case
2269 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2270 */
2271 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
2272 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
2273
2274 return 0;
2275}
2276
2277int mlx4_NOP(struct mlx4_dev *dev)
2278{
2279 /* Input modifier of 0x1f means "finish as soon as possible." */
5a031086
JM		 2280 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A,
2281 MLX4_CMD_NATIVE);
225c7b1f 2282}
14c07b13 2283
8e1a28e8
HHZ		 2284int mlx4_get_phys_port_id(struct mlx4_dev *dev)
2285{
2286 u8 port;
2287 u32 *outbox;
2288 struct mlx4_cmd_mailbox *mailbox;
2289 u32 in_mod;
2290 u32 guid_hi, guid_lo;
2291 int err, ret = 0;
2292#define MOD_STAT_CFG_PORT_OFFSET 8
2293#define MOD_STAT_CFG_GUID_H 0X14
2294#define MOD_STAT_CFG_GUID_L 0X1c
2295
2296 mailbox = mlx4_alloc_cmd_mailbox(dev);
2297 if (IS_ERR(mailbox))
2298 return PTR_ERR(mailbox);
2299 outbox = mailbox->buf;
2300
2301 for (port = 1; port <= dev->caps.num_ports; port++) {
2302 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
2303 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
2304 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2305 MLX4_CMD_NATIVE);
2306 if (err) {
2307 mlx4_err(dev, "Fail to get port %d uplink guid\n",
2308 port);
2309 ret = err;
2310 } else {
2311 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2312 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2313 dev->caps.phys_port_id[port] = (u64)guid_lo |
2314 (u64)guid_hi << 32;
2315 }
2316 }
2317 mlx4_free_cmd_mailbox(dev, mailbox);
2318 return ret;
2319}
2320
14c07b13
YP		 2321#define MLX4_WOL_SETUP_MODE (5 << 28)
2322int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
2323{
2324 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2325
2326 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 2327 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2328 MLX4_CMD_NATIVE);
14c07b13
YP		 2329}
2330EXPORT_SYMBOL_GPL(mlx4_wol_read);
2331
2332int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
2333{
2334 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2335
2336 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 2337 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 2338}
2339EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 2340
2341enum {
2342 ADD_TO_MCG = 0x26,
2343};
2344
2345
2346void mlx4_opreq_action(struct work_struct *work)
2347{
2348 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
2349 opreq_task);
2350 struct mlx4_dev *dev = &priv->dev;
2351 int num_tasks = atomic_read(&priv->opreq_count);
2352 struct mlx4_cmd_mailbox *mailbox;
2353 struct mlx4_mgm *mgm;
2354 u32 *outbox;
2355 u32 modifier;
2356 u16 token;
fe6f700d
YP		 2357 u16 type;
2358 int err;
2359 u32 num_qps;
2360 struct mlx4_qp qp;
2361 int i;
2362 u8 rem_mcg;
2363 u8 prot;
2364
2365#define GET_OP_REQ_MODIFIER_OFFSET 0x08
2366#define GET_OP_REQ_TOKEN_OFFSET 0x14
2367#define GET_OP_REQ_TYPE_OFFSET 0x1a
2368#define GET_OP_REQ_DATA_OFFSET 0x20
2369
2370 mailbox = mlx4_alloc_cmd_mailbox(dev);
2371 if (IS_ERR(mailbox)) {
2372 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2373 return;
2374 }
2375 outbox = mailbox->buf;
2376
2377 while (num_tasks) {
2378 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2379 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2380 MLX4_CMD_NATIVE);
2381 if (err) {
6d3be300 2382 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 2383 err);
2384 return;
2385 }
2386 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2387 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2388 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 2389 type &= 0xfff;
2390
2391 switch (type) {
2392 case ADD_TO_MCG:
2393 if (dev->caps.steering_mode ==
2394 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2395 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2396 err = EPERM;
2397 break;
2398 }
2399 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2400 GET_OP_REQ_DATA_OFFSET);
2401 num_qps = be32_to_cpu(mgm->members_count) &
2402 MGM_QPN_MASK;
2403 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2404 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2405
2406 for (i = 0; i < num_qps; i++) {
2407 qp.qpn = be32_to_cpu(mgm->qp[i]);
2408 if (rem_mcg)
2409 err = mlx4_multicast_detach(dev, &qp,
2410 mgm->gid,
2411 prot, 0);
2412 else
2413 err = mlx4_multicast_attach(dev, &qp,
2414 mgm->gid,
2415 mgm->gid[5]
2416 , 0, prot,
2417 NULL);
2418 if (err)
2419 break;
2420 }
2421 break;
2422 default:
2423 mlx4_warn(dev, "Bad type for required operation\n");
2424 err = EINVAL;
2425 break;
2426 }
28d222bb
EP		 2427 err = mlx4_cmd(dev, 0, ((u32) err |
2428 (__force u32)cpu_to_be32(token) << 16),
fe6f700d
YP		 2429 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2430 MLX4_CMD_NATIVE);
2431 if (err) {
2432 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2433 err);
2434 goto out;
2435 }
2436 memset(outbox, 0, 0xffc);
2437 num_tasks = atomic_dec_return(&priv->opreq_count);
2438 }
2439
2440out:
2441 mlx4_free_cmd_mailbox(dev, mailbox);
2442}
114840c3
JM		 2443
2444static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2445 struct mlx4_cmd_mailbox *mailbox)
2446{
2447#define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2448#define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2449#define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2450#define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2451
2452 u32 set_attr_mask, getresp_attr_mask;
2453 u32 trap_attr_mask, traprepress_attr_mask;
2454
2455 MLX4_GET(set_attr_mask, mailbox->buf,
2456 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2457 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2458 set_attr_mask);
2459
2460 MLX4_GET(getresp_attr_mask, mailbox->buf,
2461 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2462 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2463 getresp_attr_mask);
2464
2465 MLX4_GET(trap_attr_mask, mailbox->buf,
2466 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2467 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2468 trap_attr_mask);
2469
2470 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2471 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2472 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2473 traprepress_attr_mask);
2474
2475 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2476 traprepress_attr_mask)
2477 return 1;
2478
2479 return 0;
2480}
2481
2482int mlx4_config_mad_demux(struct mlx4_dev *dev)
2483{
2484 struct mlx4_cmd_mailbox *mailbox;
2485 int secure_host_active;
2486 int err;
2487
2488 /* Check if mad_demux is supported */
2489 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2490 return 0;
2491
2492 mailbox = mlx4_alloc_cmd_mailbox(dev);
2493 if (IS_ERR(mailbox)) {
2494 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2495 return -ENOMEM;
2496 }
2497
2498 /* Query mad_demux to find out which MADs are handled by internal sma */
2499 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2500 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2501 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2502 if (err) {
2503 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2504 err);
2505 goto out;
2506 }
2507
2508 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2509
2510 /* Config mad_demux to handle all MADs returned by the query above */
2511 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2512 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2513 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2514 if (err) {
2515 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2516 goto out;
2517 }
2518
2519 if (secure_host_active)
2520 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2521out:
2522 mlx4_free_cmd_mailbox(dev, mailbox);
2523 return err;
2524}
adbc7ac5
SM		 2525
2526/* Access Reg commands */
2527enum mlx4_access_reg_masks {
2528 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2529 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2530 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2531};
2532
2533struct mlx4_access_reg {
2534 __be16 constant1;
2535 u8 status;
2536 u8 resrvd1;
2537 __be16 reg_id;
2538 u8 method;
2539 u8 constant2;
2540 __be32 resrvd2[2];
2541 __be16 len_const;
2542 __be16 resrvd3;
2543#define MLX4_ACCESS_REG_HEADER_SIZE (20)
2544 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2545} __attribute__((__packed__));
2546
2547/**
2548 * mlx4_ACCESS_REG - Generic access reg command.
2549 * @dev: mlx4_dev.
2550 * @reg_id: register ID to access.
2551 * @method: Access method Read/Write.
2552 * @reg_len: register length to Read/Write in bytes.
2553 * @reg_data: reg_data pointer to Read/Write From/To.
2554 *
2555 * Access ConnectX registers FW command.
2556 * Returns 0 on success and copies outbox mlx4_access_reg data
2557 * field into reg_data or a negative error code.
2558 */
2559static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2560 enum mlx4_access_reg_method method,
2561 u16 reg_len, void *reg_data)
2562{
2563 struct mlx4_cmd_mailbox *inbox, *outbox;
2564 struct mlx4_access_reg *inbuf, *outbuf;
2565 int err;
2566
2567 inbox = mlx4_alloc_cmd_mailbox(dev);
2568 if (IS_ERR(inbox))
2569 return PTR_ERR(inbox);
2570
2571 outbox = mlx4_alloc_cmd_mailbox(dev);
2572 if (IS_ERR(outbox)) {
2573 mlx4_free_cmd_mailbox(dev, inbox);
2574 return PTR_ERR(outbox);
2575 }
2576
2577 inbuf = inbox->buf;
2578 outbuf = outbox->buf;
2579
2580 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2581 inbuf->constant2 = 0x1;
2582 inbuf->reg_id = cpu_to_be16(reg_id);
2583 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2584
2585 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2586 inbuf->len_const =
2587 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2588 ((0x3) << 12));
2589
2590 memcpy(inbuf->reg_data, reg_data, reg_len);
2591 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2592 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
6e806699 2593 MLX4_CMD_WRAPPED);
adbc7ac5
SM		 2594 if (err)
2595 goto out;
2596
2597 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2598 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2599 mlx4_err(dev,
2600 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2601 reg_id, err);
2602 goto out;
2603 }
2604
2605 memcpy(reg_data, outbuf->reg_data, reg_len);
2606out:
2607 mlx4_free_cmd_mailbox(dev, inbox);
2608 mlx4_free_cmd_mailbox(dev, outbox);
2609 return err;
2610}
2611
2612/* ConnectX registers IDs */
2613enum mlx4_reg_id {
2614 MLX4_REG_ID_PTYS = 0x5004,
2615};
2616
2617/**
2618 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2619 * register
2620 * @dev: mlx4_dev.
2621 * @method: Access method Read/Write.
2622 * @ptys_reg: PTYS register data pointer.
2623 *
2624 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2625 * configuration
2626 * Returns 0 on success or a negative error code.
2627 */
2628int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2629 enum mlx4_access_reg_method method,
2630 struct mlx4_ptys_reg *ptys_reg)
2631{
2632 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2633 method, sizeof(*ptys_reg), ptys_reg);
2634}
2635EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
6e806699
SM		 2636
2637int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2638 struct mlx4_vhcr *vhcr,
2639 struct mlx4_cmd_mailbox *inbox,
2640 struct mlx4_cmd_mailbox *outbox,
2641 struct mlx4_cmd_info *cmd)
2642{
2643 struct mlx4_access_reg *inbuf = inbox->buf;
2644 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2645 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2646
2647 if (slave != mlx4_master_func_num(dev) &&
2648 method == MLX4_ACCESS_REG_WRITE)
2649 return -EPERM;
2650
2651 if (reg_id == MLX4_REG_ID_PTYS) {
2652 struct mlx4_ptys_reg *ptys_reg =
2653 (struct mlx4_ptys_reg *)inbuf->reg_data;
2654
2655 ptys_reg->local_port =
2656 mlx4_slave_convert_port(dev, slave,
2657 ptys_reg->local_port);
2658 }
2659
2660 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2661 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2662 MLX4_CMD_NATIVE);
2663}
Linux 6.x block layer and io_uring tree(s)