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powerpc/boot: don't clobber r6 and r7 in epapr boot
[linux-2.6-block.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
d1cdcf22
AB		 4
5#include <asm/asm-compat.h>
c5157e58 6#include <asm/feature-fixups.h>
c3617f72 7#include <uapi/asm/cputable.h>
d1cdcf22 8
10b35d99
KG		 9#ifndef __ASSEMBLY__
10
11/* This structure can grow, it's real size is used by head.S code
12 * via the mkdefs mechanism.
13 */
14struct cpu_spec;
10b35d99 15
10b35d99 16typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 17typedef void (*cpu_restore_t)(void);
10b35d99 18
32a33994 19enum powerpc_oprofile_type {
7a45fb19
AW		 20 PPC_OPROFILE_INVALID = 0,
21 PPC_OPROFILE_RS64 = 1,
22 PPC_OPROFILE_POWER4 = 2,
23 PPC_OPROFILE_G4 = 3,
39aef685 24 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 25 PPC_OPROFILE_CELL = 5,
25fc530e 26 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 27};
28
1bd2e5ae
OJ		 29enum powerpc_pmc_type {
30 PPC_PMC_DEFAULT = 0,
31 PPC_PMC_IBM = 1,
32 PPC_PMC_PA6T = 2,
b950bdd0 33 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 34};
35
47c0bd1a
BH		 36struct pt_regs;
37
38extern int machine_check_generic(struct pt_regs *regs);
39extern int machine_check_4xx(struct pt_regs *regs);
40extern int machine_check_440A(struct pt_regs *regs);
fe04b112 41extern int machine_check_e500mc(struct pt_regs *regs);
47c0bd1a
BH		 42extern int machine_check_e500(struct pt_regs *regs);
43extern int machine_check_e200(struct pt_regs *regs);
fc5e7097 44extern int machine_check_47x(struct pt_regs *regs);
47c0bd1a 45
87a72f9e 46/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 47struct cpu_spec {
48 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
49 unsigned int pvr_mask;
50 unsigned int pvr_value;
51
52 char *cpu_name;
53 unsigned long cpu_features; /* Kernel features */
54 unsigned int cpu_user_features; /* Userland features */
2171364d 55 unsigned int cpu_user_features2; /* Userland features v2 */
7c03d653 56 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 57
58 /* cache line sizes */
59 unsigned int icache_bsize;
60 unsigned int dcache_bsize;
61
62 /* number of performance monitor counters */
63 unsigned int num_pmcs;
1bd2e5ae 64 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 65
66 /* this is called to initialize various CPU bits like L1 cache,
67 * BHT, SPD, etc... from head.S before branching to identify_machine
68 */
69 cpu_setup_t cpu_setup;
f39b7a55
OJ		 70 /* Used to restore cpu setup on secondary processors and at resume */
71 cpu_restore_t cpu_restore;
10b35d99
KG		 72
73 /* Used by oprofile userspace to select the right counters */
74 char *oprofile_cpu_type;
75
76 /* Processor specific oprofile operations */
32a33994 77 enum powerpc_oprofile_type oprofile_type;
80f15dc7 78
e78dbc80
MN		 79 /* Bit locations inside the mmcra change */
80 unsigned long oprofile_mmcra_sihv;
81 unsigned long oprofile_mmcra_sipr;
82
83 /* Bits to clear during an oprofile exception */
84 unsigned long oprofile_mmcra_clear;
85
80f15dc7
PM		 86 /* Name of processor class, for the ELF AT_PLATFORM entry */
87 char *platform;
47c0bd1a
BH		 88
89 /* Processor specific machine check handling. Return negative
90 * if the error is fatal, 1 if it was fully recovered and 0 to
91 * pass up (not CPU originated) */
92 int (*machine_check)(struct pt_regs *regs);
4c703416
MS		 93
94 /*
95 * Processor specific early machine check handler which is
96 * called in real mode to handle SLB and TLB errors.
97 */
98 long (*machine_check_early)(struct pt_regs *regs);
99
04407050
MS		 100 /*
101 * Processor specific routine to flush tlbs.
102 */
103 void (*flush_tlb)(unsigned long inval_selector);
104
10b35d99
KG		 105};
106
10b35d99 107extern struct cpu_spec *cur_cpu_spec;
10b35d99 108
42c4aaad
BH		 109extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
110
974a76f5 111extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 112extern void do_feature_fixups(unsigned long value, void *fixup_start,
113 void *fixup_end);
9b6b563c 114
9115d134
NL		 115extern const char *powerpc_base_platform;
116
10b35d99
KG		 117#endif /* __ASSEMBLY__ */
118
119/* CPU kernel features */
120
121/* Retain the 32b definitions all use bottom half of word */
cde4d494
MN		 122#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
123#define CPU_FTR_L2CR ASM_CONST(0x00000002)
124#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
125#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
126#define CPU_FTR_TAU ASM_CONST(0x00000010)
127#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
128#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
129#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
130#define CPU_FTR_601 ASM_CONST(0x00000100)
131#define CPU_FTR_DBELL ASM_CONST(0x00000200)
132#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
133#define CPU_FTR_L3CR ASM_CONST(0x00000800)
134#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
135#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
136#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
137#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
138#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
139#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
140#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
141#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
142#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
143#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
144#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
145#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
146#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
147#define CPU_FTR_SPE ASM_CONST(0x02000000)
148#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
149#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
150#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
151#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
152#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
10b35d99 153
3965f8c5
PM		 154/*
155 * Add the 64-bit processor unique features in the top half of the word;
156 * on 32-bit, make the names available but defined to be 0.
157 */
10b35d99 158#ifdef __powerpc64__
3965f8c5 159#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 160#else
3965f8c5 161#define LONG_ASM_CONST(x) 0
10b35d99
KG		 162#endif
163
1580b3b8
MN		 164#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
165#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
166#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
1de2bd4e 167#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
ed77d418 168/* Free LONG_ASM_CONST(0x0000001000000000) */
1580b3b8
MN		 169#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
170#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
171#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
172#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
173#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
174#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
175#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
176#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
177#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
178#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
179#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
180#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
181#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
182#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
183#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
184#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
185#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
186#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
187#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
1de2bd4e 188#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
1580b3b8 189#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
79879c17 190#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
82a9f16a 191#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
68f2f0d4 192#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
3965f8c5 193
10b35d99
KG		 194#ifndef __ASSEMBLY__
195
44ae3ab3
ME		 196#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
197
13b3d13b 198#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
10b35d99
KG		 199
200/* We only set the altivec features if the kernel was compiled with altivec
201 * support
202 */
203#ifdef CONFIG_ALTIVEC
204#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
205#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
206#else
207#define CPU_FTR_ALTIVEC_COMP 0
208#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
209#endif
210
b962ce9d
MN		 211/* We only set the VSX features if the kernel was compiled with VSX
212 * support
213 */
214#ifdef CONFIG_VSX
215#define CPU_FTR_VSX_COMP CPU_FTR_VSX
216#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
217#else
218#define CPU_FTR_VSX_COMP 0
219#define PPC_FEATURE_HAS_VSX_COMP 0
220#endif
221
5e14d21e
KG		 222/* We only set the spe features if the kernel was compiled with spe
223 * support
224 */
225#ifdef CONFIG_SPE
226#define CPU_FTR_SPE_COMP CPU_FTR_SPE
227#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
228#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
229#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
230#else
231#define CPU_FTR_SPE_COMP 0
232#define PPC_FEATURE_HAS_SPE_COMP 0
233#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
234#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
235#endif
236
6a6d541f
MN		 237/* We only set the TM feature if the kernel was compiled with TM supprt */
238#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
239#define CPU_FTR_TM_COMP CPU_FTR_TM
cbbc6f1b 240#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
6a6d541f
MN		 241#else
242#define CPU_FTR_TM_COMP 0
cbbc6f1b 243#define PPC_FEATURE2_HTM_COMP 0
6a6d541f
MN		 244#endif
245
11af1192
SW		 246/* We need to mark all pages as being coherent if we're SMP or we have a
247 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
248 * require it for PCI "streaming/prefetch" to work properly.
c9310920 249 * This is also required by 52xx family.
10b35d99 250 */
1775dbbc 251#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
c9310920
PZ		 252 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
253 || defined(CONFIG_PPC_MPC52xx)
10b35d99
KG		 254#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
255#else
256#define CPU_FTR_COMMON 0
257#endif
258
259/* The powersave features NAP & DOZE seems to confuse BDI when
260 debugging. So if a BDI is used, disable theses
261 */
262#ifndef CONFIG_BDI_SWITCH
263#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
264#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
265#else
266#define CPU_FTR_MAYBE_CAN_DOZE 0
267#define CPU_FTR_MAYBE_CAN_NAP 0
268#endif
269
7c03d653 270#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
4508dc21
DG		 271 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
272#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 273 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 274 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 275#define CPU_FTRS_604 (CPU_FTR_COMMON | \
7c03d653 276 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
4508dc21 277#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 278 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 279 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 280#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 281 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 282 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 283 CPU_FTR_PPC_LE)
4508dc21 284#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 285 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 286 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 287 CPU_FTR_PPC_LE)
7c03d653 288#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 289#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
290#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 291#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 292#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 293#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c 294 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 295 CPU_FTR_ALTIVEC_COMP | \
fab5db97 296 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 297#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c 298 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 299 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 301#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c 302 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 303 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 304 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 305#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 306 CPU_FTR_USE_TB | \
307 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 308 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 309 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 310 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 311#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 312 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 313 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 314 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 315 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 316#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 317 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 318 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 319 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 320#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 321 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 322 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 323 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 324 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 325 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 326#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 327 CPU_FTR_USE_TB | \
328 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 329 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 330 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 331#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 332 CPU_FTR_USE_TB | \
333 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 334 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 335 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
336 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 337#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 338 CPU_FTR_USE_TB | \
339 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 340 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 341 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 342#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 343 CPU_FTR_USE_TB | \
344 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 345 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 346 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 347#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 348 CPU_FTR_USE_TB | \
349 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 350 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 351 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 352#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 353 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 354#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 355 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
4508dc21 356#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 357 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
7c92943c 358 CPU_FTR_COMMON)
4508dc21 359#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 360 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
aa42c69c 361 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
7c03d653 362#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
4508dc21 363#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
8309ce72
BH		 364#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
365#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
6d2170be
BH		 366#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
367 CPU_FTR_INDEXED_DCR)
e7f75ad0 368#define CPU_FTRS_47X (CPU_FTRS_440x6)
5e14d21e
KG		 369#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
370 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
52b066fa
SW		 371 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
372 CPU_FTR_DEBUG_LVL_EXC)
fc4033b2 373#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
8309ce72
BH		 374 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
375 CPU_FTR_NOEXECUTE)
fc4033b2 376#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
7c03d653 377 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 378 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
d51ad915 379#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
620165f9 380 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
73196cd3 381 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
d52459ca
SW		 382/*
383 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
384 * same workaround as CPU_FTR_CELL_TB_BUG.
385 */
11ed0db9
KG		 386#define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
387 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
d36b4c4f 388 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 389 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
10241842
KG		 390#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
391 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
392 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d52459ca 393 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
e16c8765 394 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
7c92943c 395#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 396
397/* 64-bit CPUs */
2d1b2027 398#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 399 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
f89451fb
AB		 400 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
401 CPU_FTR_STCX_CHECKS_ADDRESS)
2d1b2027 402#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 403 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
2a929436 404 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
969391c5 405 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
82a9f16a 406 CPU_FTR_HVMODE | CPU_FTR_DABRX)
2d1b2027 407#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 408 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 409 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 410 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
82a9f16a 411 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
2d1b2027 412#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 413 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51 414 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 415 CPU_FTR_COHERENT_ICACHE | \
4c198557 416 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 417 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
82a9f16a
MN		 418 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
419 CPU_FTR_DABRX)
2d1b2027 420#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
969391c5 421 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
e952e6c4 422 CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 423 CPU_FTR_COHERENT_ICACHE | \
e952e6c4 424 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 425 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
851d2e2f 426 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
d2613868 427 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
82a9f16a 428 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
71e18497
MN		 429#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
430 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
431 CPU_FTR_MMCRA | CPU_FTR_SMT | \
432 CPU_FTR_COHERENT_ICACHE | \
433 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
434 CPU_FTR_DSCR | CPU_FTR_SAO | \
435 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
e5e84f0a 436 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
1de2bd4e
ME		 437 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
438 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
68f2f0d4 439#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
bd6ba351 440#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
2d1b2027 441#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 442 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 443 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
44ae3ab3 444 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
82a9f16a 445 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
2d1b2027 446#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
44ae3ab3 447 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
82a9f16a 448 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
7c03d653 449#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 450
2406f606 451#ifdef __powerpc64__
11ed0db9 452#ifdef CONFIG_PPC_BOOK3E
90029640 453#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
11ed0db9 454#else
7c92943c 455#define CPU_FTRS_POSSIBLE \
468a3302
ME		 456 (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
457 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
3609e09f
ME		 458 CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
459 CPU_FTRS_PA6T | CPU_FTR_VSX)
11ed0db9 460#endif
2406f606 461#else
7c92943c
SR		 462enum {
463 CPU_FTRS_POSSIBLE =
1e07a0a0 464#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 465 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
466 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
467 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
468 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
469 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
470 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
471 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 472 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
473 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 474#else
475 CPU_FTRS_GENERIC_32 |
476#endif
10b35d99
KG		 477#ifdef CONFIG_8xx
478 CPU_FTRS_8XX |
479#endif
480#ifdef CONFIG_40x
481 CPU_FTRS_40X |
482#endif
483#ifdef CONFIG_44x
6d2170be 484 CPU_FTRS_44X | CPU_FTRS_440x6 |
10b35d99 485#endif
e7f75ad0 486#ifdef CONFIG_PPC_47x
c48d0dba 487 CPU_FTRS_47X | CPU_FTR_476_DD2 |
e7f75ad0 488#endif
10b35d99
KG		 489#ifdef CONFIG_E200
490 CPU_FTRS_E200 |
491#endif
492#ifdef CONFIG_E500
06aae867
SW		 493 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
494#endif
495#ifdef CONFIG_PPC_E500MC
496 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
10b35d99 497#endif
10b35d99 498 0,
7c92943c
SR		 499};
500#endif /* __powerpc64__ */
10b35d99 501
2406f606 502#ifdef __powerpc64__
11ed0db9 503#ifdef CONFIG_PPC_BOOK3E
90029640 504#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
11ed0db9 505#else
7c92943c 506#define CPU_FTRS_ALWAYS \
468a3302
ME		 507 (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
508 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
3609e09f 509 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
66f3d4fe 510 CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE)
11ed0db9 511#endif
2406f606 512#else
7c92943c
SR		 513enum {
514 CPU_FTRS_ALWAYS =
1e07a0a0 515#ifdef CONFIG_PPC_BOOK3S_32
10b35d99
KG		 516 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
517 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
518 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
519 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
520 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
521 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
522 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 523 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
524 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 525#else
526 CPU_FTRS_GENERIC_32 &
527#endif
10b35d99
KG		 528#ifdef CONFIG_8xx
529 CPU_FTRS_8XX &
530#endif
531#ifdef CONFIG_40x
532 CPU_FTRS_40X &
533#endif
534#ifdef CONFIG_44x
6d2170be 535 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99
KG		 536#endif
537#ifdef CONFIG_E200
538 CPU_FTRS_E200 &
539#endif
540#ifdef CONFIG_E500
06aae867
SW		 541 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
542#endif
543#ifdef CONFIG_PPC_E500MC
544 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
10b35d99 545#endif
73196cd3 546 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
10b35d99
KG		 547 CPU_FTRS_POSSIBLE,
548};
7c92943c 549#endif /* __powerpc64__ */
10b35d99
KG		 550
551static inline int cpu_has_feature(unsigned long feature)
552{
553 return (CPU_FTRS_ALWAYS & feature) ||
554 (CPU_FTRS_POSSIBLE
10b35d99 555 & cur_cpu_spec->cpu_features
10b35d99
KG		 556 & feature);
557}
558
5aae8a53 559#define HBP_NUM 1
5aae8a53 560
10b35d99
KG		 561#endif /* !__ASSEMBLY__ */
562
10b35d99 563#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)