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powerpc: Check device status before adding serial device
[linux-2.6-block.git] / arch / powerpc / include / asm / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
10b35d99
KG		 4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000
9#define PPC_FEATURE_HAS_MMU 0x04000000
10#define PPC_FEATURE_HAS_4xxMAC 0x02000000
11#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
12#define PPC_FEATURE_HAS_SPE 0x00800000
13#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
14#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
98599013 15#define PPC_FEATURE_NO_TB 0x00100000
a7ddc5e8
PM		 16#define PPC_FEATURE_POWER4 0x00080000
17#define PPC_FEATURE_POWER5 0x00040000
18#define PPC_FEATURE_POWER5_PLUS 0x00020000
19#define PPC_FEATURE_CELL 0x00010000
80f15dc7 20#define PPC_FEATURE_BOOKE 0x00008000
aa5cb021
BH		 21#define PPC_FEATURE_SMT 0x00004000
22#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
03054d51 23#define PPC_FEATURE_ARCH_2_05 0x00001000
b3ebd1d8 24#define PPC_FEATURE_PA6T 0x00000800
974a76f5
PM		 25#define PPC_FEATURE_HAS_DFP 0x00000400
26#define PPC_FEATURE_POWER6_EXT 0x00000200
e952e6c4 27#define PPC_FEATURE_ARCH_2_06 0x00000100
b962ce9d 28#define PPC_FEATURE_HAS_VSX 0x00000080
10b35d99 29
0f473314
NL		 30#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
31 0x00000040
32
fab5db97
PM		 33#define PPC_FEATURE_TRUE_LE 0x00000002
34#define PPC_FEATURE_PPC_LE 0x00000001
35
10b35d99 36#ifdef __KERNEL__
d1cdcf22
AB		 37
38#include <asm/asm-compat.h>
c5157e58 39#include <asm/feature-fixups.h>
d1cdcf22 40
10b35d99
KG		 41#ifndef __ASSEMBLY__
42
43/* This structure can grow, it's real size is used by head.S code
44 * via the mkdefs mechanism.
45 */
46struct cpu_spec;
10b35d99 47
10b35d99 48typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 49typedef void (*cpu_restore_t)(void);
10b35d99 50
32a33994 51enum powerpc_oprofile_type {
7a45fb19
AW		 52 PPC_OPROFILE_INVALID = 0,
53 PPC_OPROFILE_RS64 = 1,
54 PPC_OPROFILE_POWER4 = 2,
55 PPC_OPROFILE_G4 = 3,
39aef685 56 PPC_OPROFILE_FSL_EMB = 4,
18f2190d 57 PPC_OPROFILE_CELL = 5,
25fc530e 58 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 59};
60
1bd2e5ae
OJ		 61enum powerpc_pmc_type {
62 PPC_PMC_DEFAULT = 0,
63 PPC_PMC_IBM = 1,
64 PPC_PMC_PA6T = 2,
b950bdd0 65 PPC_PMC_G4 = 3,
1bd2e5ae
OJ		 66};
67
47c0bd1a
BH		 68struct pt_regs;
69
70extern int machine_check_generic(struct pt_regs *regs);
71extern int machine_check_4xx(struct pt_regs *regs);
72extern int machine_check_440A(struct pt_regs *regs);
fe04b112 73extern int machine_check_e500mc(struct pt_regs *regs);
47c0bd1a
BH		 74extern int machine_check_e500(struct pt_regs *regs);
75extern int machine_check_e200(struct pt_regs *regs);
fc5e7097 76extern int machine_check_47x(struct pt_regs *regs);
47c0bd1a 77
87a72f9e 78/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 79struct cpu_spec {
80 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
81 unsigned int pvr_mask;
82 unsigned int pvr_value;
83
84 char *cpu_name;
85 unsigned long cpu_features; /* Kernel features */
86 unsigned int cpu_user_features; /* Userland features */
7c03d653 87 unsigned int mmu_features; /* MMU features */
10b35d99
KG		 88
89 /* cache line sizes */
90 unsigned int icache_bsize;
91 unsigned int dcache_bsize;
92
93 /* number of performance monitor counters */
94 unsigned int num_pmcs;
1bd2e5ae 95 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 96
97 /* this is called to initialize various CPU bits like L1 cache,
98 * BHT, SPD, etc... from head.S before branching to identify_machine
99 */
100 cpu_setup_t cpu_setup;
f39b7a55
OJ		 101 /* Used to restore cpu setup on secondary processors and at resume */
102 cpu_restore_t cpu_restore;
10b35d99
KG		 103
104 /* Used by oprofile userspace to select the right counters */
105 char *oprofile_cpu_type;
106
107 /* Processor specific oprofile operations */
32a33994 108 enum powerpc_oprofile_type oprofile_type;
80f15dc7 109
e78dbc80
MN		 110 /* Bit locations inside the mmcra change */
111 unsigned long oprofile_mmcra_sihv;
112 unsigned long oprofile_mmcra_sipr;
113
114 /* Bits to clear during an oprofile exception */
115 unsigned long oprofile_mmcra_clear;
116
80f15dc7
PM		 117 /* Name of processor class, for the ELF AT_PLATFORM entry */
118 char *platform;
47c0bd1a
BH		 119
120 /* Processor specific machine check handling. Return negative
121 * if the error is fatal, 1 if it was fully recovered and 0 to
122 * pass up (not CPU originated) */
123 int (*machine_check)(struct pt_regs *regs);
10b35d99
KG		 124};
125
10b35d99 126extern struct cpu_spec *cur_cpu_spec;
10b35d99 127
42c4aaad
BH		 128extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
129
974a76f5 130extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 131extern void do_feature_fixups(unsigned long value, void *fixup_start,
132 void *fixup_end);
9b6b563c 133
9115d134
NL		 134extern const char *powerpc_base_platform;
135
10b35d99
KG		 136#endif /* __ASSEMBLY__ */
137
138/* CPU kernel features */
139
140/* Retain the 32b definitions all use bottom half of word */
4508dc21 141#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
10b35d99
KG		 142#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
143#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
144#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
145#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
146#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
147#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
aba11fc5 148#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
10b35d99 149#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
620165f9 150#define CPU_FTR_DBELL ASM_CONST(0x0000000000000200)
10b35d99
KG		 151#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
152#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
153#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
154#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
155#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
156#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
c48d0dba 157#define CPU_FTR_476_DD2 ASM_CONST(0x0000000000010000)
10b35d99
KG		 158#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
159#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
3d15910b 160#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
fab5db97
PM		 161#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
162#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
aa42c69c 163#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
4508dc21 164#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
5e14d21e 165#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
b64f87c1 166#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
2d1b2027 167#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
8309ce72 168#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000010000000)
6d2170be 169#define CPU_FTR_INDEXED_DCR ASM_CONST(0x0000000020000000)
10b35d99 170
3965f8c5
PM		 171/*
172 * Add the 64-bit processor unique features in the top half of the word;
173 * on 32-bit, make the names available but defined to be 0.
174 */
10b35d99 175#ifdef __powerpc64__
3965f8c5 176#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 177#else
3965f8c5 178#define LONG_ASM_CONST(x) 0
10b35d99
KG		 179#endif
180
3965f8c5
PM		 181#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
182#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
183#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
3965f8c5
PM		 184#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
185#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
186#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
187#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
3965f8c5
PM		 188#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
189#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
190#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
191#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
859deea9 192#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
974a76f5 193#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
4c198557 194#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
1189be65 195#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
f66bce5e 196#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
b962ce9d 197#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
37907049 198#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
2a929436 199#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
4ec577a2 200#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
76cbd8a8 201#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000)
f89451fb 202#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000)
64ff3128
AB		 203#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0400000000000000)
204#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0800000000000000)
3965f8c5 205
10b35d99
KG		 206#ifndef __ASSEMBLY__
207
0470466d
SR		 208#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
209 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
210 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
10b35d99
KG		 211
212/* We only set the altivec features if the kernel was compiled with altivec
213 * support
214 */
215#ifdef CONFIG_ALTIVEC
216#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
217#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
218#else
219#define CPU_FTR_ALTIVEC_COMP 0
220#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
221#endif
222
b962ce9d
MN		 223/* We only set the VSX features if the kernel was compiled with VSX
224 * support
225 */
226#ifdef CONFIG_VSX
227#define CPU_FTR_VSX_COMP CPU_FTR_VSX
228#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
229#else
230#define CPU_FTR_VSX_COMP 0
231#define PPC_FEATURE_HAS_VSX_COMP 0
232#endif
233
5e14d21e
KG		 234/* We only set the spe features if the kernel was compiled with spe
235 * support
236 */
237#ifdef CONFIG_SPE
238#define CPU_FTR_SPE_COMP CPU_FTR_SPE
239#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
240#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
241#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
242#else
243#define CPU_FTR_SPE_COMP 0
244#define PPC_FEATURE_HAS_SPE_COMP 0
245#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
246#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
247#endif
248
11af1192
SW		 249/* We need to mark all pages as being coherent if we're SMP or we have a
250 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
251 * require it for PCI "streaming/prefetch" to work properly.
c9310920 252 * This is also required by 52xx family.
10b35d99 253 */
1775dbbc 254#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
c9310920
PZ		 255 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
256 || defined(CONFIG_PPC_MPC52xx)
10b35d99
KG		 257#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
258#else
259#define CPU_FTR_COMMON 0
260#endif
261
262/* The powersave features NAP & DOZE seems to confuse BDI when
263 debugging. So if a BDI is used, disable theses
264 */
265#ifndef CONFIG_BDI_SWITCH
266#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
267#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
268#else
269#define CPU_FTR_MAYBE_CAN_DOZE 0
270#define CPU_FTR_MAYBE_CAN_NAP 0
271#endif
272
273#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
274 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
275 !defined(CONFIG_BOOKE))
276
7c03d653 277#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
4508dc21
DG		 278 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
279#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 280 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 281 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 282#define CPU_FTRS_604 (CPU_FTR_COMMON | \
7c03d653 283 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
4508dc21 284#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 285 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 286 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 287#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 288 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 289 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 290 CPU_FTR_PPC_LE)
4508dc21 291#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 292 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 293 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
fab5db97 294 CPU_FTR_PPC_LE)
7c03d653 295#define CPU_FTRS_750CL (CPU_FTRS_750)
b6f41cc8
JB		 296#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
297#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
7c03d653 298#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
b6f41cc8 299#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 300#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c 301 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 302 CPU_FTR_ALTIVEC_COMP | \
fab5db97 303 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 304#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c 305 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
7c03d653 306 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
fab5db97 307 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 308#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c 309 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 310 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
b64f87c1 311 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 312#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 313 CPU_FTR_USE_TB | \
314 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 315 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 316 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
b64f87c1 317 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 318#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
b64f87c1 319 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 320 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 321 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
fab5db97 322 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 323#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
b64f87c1 324 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 325 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
7c03d653 326 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 327#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
b64f87c1 328 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
7c92943c 329 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 330 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
7c92943c 331 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
7c03d653 332 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 333#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 334 CPU_FTR_USE_TB | \
335 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 336 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 337 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 338#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 339 CPU_FTR_USE_TB | \
340 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 341 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1
BB		 342 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
343 CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 344#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 345 CPU_FTR_USE_TB | \
346 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 347 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 348 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 349#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 350 CPU_FTR_USE_TB | \
351 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 352 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 353 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 354#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 355 CPU_FTR_USE_TB | \
356 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
7c03d653 357 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
b64f87c1 358 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
4508dc21 359#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 360 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 361#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 362 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
4508dc21 363#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 364 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
7c92943c 365 CPU_FTR_COMMON)
4508dc21 366#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
7c03d653 367 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
aa42c69c 368 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
7c03d653 369#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
4508dc21 370#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
8309ce72
BH		 371#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
372#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
6d2170be
BH		 373#define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
374 CPU_FTR_INDEXED_DCR)
e7f75ad0 375#define CPU_FTRS_47X (CPU_FTRS_440x6)
5e14d21e
KG		 376#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
377 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
8309ce72 378 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
fc4033b2 379#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
8309ce72
BH		 380 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
381 CPU_FTR_NOEXECUTE)
fc4033b2 382#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
7c03d653 383 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
8309ce72 384 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
fc4033b2 385#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
7c03d653 386 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
620165f9
KG		 387 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
388 CPU_FTR_DBELL)
7c92943c 389#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 390
391/* 64-bit CPUs */
5a0e9b57 392#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
7c03d653 393 CPU_FTR_IABR | CPU_FTR_PPC_LE)
5a0e9b57 394#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
7c03d653 395 CPU_FTR_IABR | \
7c92943c 396 CPU_FTR_MMCRA | CPU_FTR_CTRL)
2d1b2027 397#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 398 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
f89451fb
AB		 399 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
400 CPU_FTR_STCX_CHECKS_ADDRESS)
2d1b2027 401#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 402 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
2a929436 403 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
f89451fb 404 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS)
2d1b2027 405#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 406 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c
SR		 407 CPU_FTR_MMCRA | CPU_FTR_SMT | \
408 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
64ff3128
AB		 409 CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \
410 CPU_FTR_POPCNTB)
2d1b2027 411#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 412 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51
AB		 413 CPU_FTR_MMCRA | CPU_FTR_SMT | \
414 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
4c198557 415 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 416 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
64ff3128 417 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
2d1b2027 418#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 419 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
e952e6c4
MN		 420 CPU_FTR_MMCRA | CPU_FTR_SMT | \
421 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
422 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
f89451fb 423 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
64ff3128 424 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
2d1b2027 425#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 426 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 427 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
2a929436 428 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
4ec577a2
MN		 429 CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
430 CPU_FTR_UNALIGNED_LD_STD)
2d1b2027 431#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
7c03d653 432 CPU_FTR_PPCAS_ARCH_V2 | \
b3ebd1d8 433 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
f66bce5e 434 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
7c03d653 435#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 436
2406f606 437#ifdef __powerpc64__
7c92943c
SR		 438#define CPU_FTRS_POSSIBLE \
439 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
03054d51 440 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
e952e6c4 441 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
b962ce9d 442 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
2406f606 443#else
7c92943c
SR		 444enum {
445 CPU_FTRS_POSSIBLE =
10b35d99
KG		 446#if CLASSIC_PPC
447 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
448 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
449 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
450 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
451 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
452 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
453 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 454 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
455 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 456#else
457 CPU_FTRS_GENERIC_32 |
458#endif
10b35d99
KG		 459#ifdef CONFIG_8xx
460 CPU_FTRS_8XX |
461#endif
462#ifdef CONFIG_40x
463 CPU_FTRS_40X |
464#endif
465#ifdef CONFIG_44x
6d2170be 466 CPU_FTRS_44X | CPU_FTRS_440x6 |
10b35d99 467#endif
e7f75ad0 468#ifdef CONFIG_PPC_47x
c48d0dba 469 CPU_FTRS_47X | CPU_FTR_476_DD2 |
e7f75ad0 470#endif
10b35d99
KG		 471#ifdef CONFIG_E200
472 CPU_FTRS_E200 |
473#endif
474#ifdef CONFIG_E500
3dfa8773 475 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
10b35d99 476#endif
10b35d99 477 0,
7c92943c
SR		 478};
479#endif /* __powerpc64__ */
10b35d99 480
2406f606 481#ifdef __powerpc64__
7c92943c
SR		 482#define CPU_FTRS_ALWAYS \
483 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51 484 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
e952e6c4 485 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
2406f606 486#else
7c92943c
SR		 487enum {
488 CPU_FTRS_ALWAYS =
10b35d99
KG		 489#if CLASSIC_PPC
490 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
491 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
492 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
493 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
494 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
495 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
496 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 497 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
498 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 499#else
500 CPU_FTRS_GENERIC_32 &
501#endif
10b35d99
KG		 502#ifdef CONFIG_8xx
503 CPU_FTRS_8XX &
504#endif
505#ifdef CONFIG_40x
506 CPU_FTRS_40X &
507#endif
508#ifdef CONFIG_44x
6d2170be 509 CPU_FTRS_44X & CPU_FTRS_440x6 &
10b35d99
KG		 510#endif
511#ifdef CONFIG_E200
512 CPU_FTRS_E200 &
513#endif
514#ifdef CONFIG_E500
3dfa8773 515 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
10b35d99 516#endif
10b35d99
KG		 517 CPU_FTRS_POSSIBLE,
518};
7c92943c 519#endif /* __powerpc64__ */
10b35d99
KG		 520
521static inline int cpu_has_feature(unsigned long feature)
522{
523 return (CPU_FTRS_ALWAYS & feature) ||
524 (CPU_FTRS_POSSIBLE
10b35d99 525 & cur_cpu_spec->cpu_features
10b35d99
KG		 526 & feature);
527}
528
5aae8a53
P		 529#ifdef CONFIG_HAVE_HW_BREAKPOINT
530#define HBP_NUM 1
531#endif /* CONFIG_HAVE_HW_BREAKPOINT */
532
10b35d99
KG		 533#endif /* !__ASSEMBLY__ */
534
10b35d99
KG		 535#endif /* __KERNEL__ */
536#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)