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[POWERPC] Enable NO_HZ and high res timers for pseries and ppc64 configs
[linux-2.6-block.git] / include / asm-powerpc / cputable.h
CommitLineData
10b35d99
KG		 1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
3ddfbcf1 4#include <asm/asm-compat.h>
10b35d99
KG		 5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
98599013 17#define PPC_FEATURE_NO_TB 0x00100000
a7ddc5e8
PM		 18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
80f15dc7 22#define PPC_FEATURE_BOOKE 0x00008000
aa5cb021
BH		 23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
03054d51 25#define PPC_FEATURE_ARCH_2_05 0x00001000
b3ebd1d8 26#define PPC_FEATURE_PA6T 0x00000800
974a76f5
PM		 27#define PPC_FEATURE_HAS_DFP 0x00000400
28#define PPC_FEATURE_POWER6_EXT 0x00000200
10b35d99 29
fab5db97
PM		 30#define PPC_FEATURE_TRUE_LE 0x00000002
31#define PPC_FEATURE_PPC_LE 0x00000001
32
10b35d99
KG		 33#ifdef __KERNEL__
34#ifndef __ASSEMBLY__
35
36/* This structure can grow, it's real size is used by head.S code
37 * via the mkdefs mechanism.
38 */
39struct cpu_spec;
10b35d99 40
10b35d99 41typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
f39b7a55 42typedef void (*cpu_restore_t)(void);
10b35d99 43
32a33994 44enum powerpc_oprofile_type {
7a45fb19
AW		 45 PPC_OPROFILE_INVALID = 0,
46 PPC_OPROFILE_RS64 = 1,
47 PPC_OPROFILE_POWER4 = 2,
48 PPC_OPROFILE_G4 = 3,
49 PPC_OPROFILE_BOOKE = 4,
18f2190d 50 PPC_OPROFILE_CELL = 5,
25fc530e 51 PPC_OPROFILE_PA6T = 6,
32a33994
AB		 52};
53
1bd2e5ae
OJ		 54enum powerpc_pmc_type {
55 PPC_PMC_DEFAULT = 0,
56 PPC_PMC_IBM = 1,
57 PPC_PMC_PA6T = 2,
58};
59
87a72f9e 60/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
10b35d99
KG		 61struct cpu_spec {
62 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
63 unsigned int pvr_mask;
64 unsigned int pvr_value;
65
66 char *cpu_name;
67 unsigned long cpu_features; /* Kernel features */
68 unsigned int cpu_user_features; /* Userland features */
69
70 /* cache line sizes */
71 unsigned int icache_bsize;
72 unsigned int dcache_bsize;
73
74 /* number of performance monitor counters */
75 unsigned int num_pmcs;
1bd2e5ae 76 enum powerpc_pmc_type pmc_type;
10b35d99
KG		 77
78 /* this is called to initialize various CPU bits like L1 cache,
79 * BHT, SPD, etc... from head.S before branching to identify_machine
80 */
81 cpu_setup_t cpu_setup;
f39b7a55
OJ		 82 /* Used to restore cpu setup on secondary processors and at resume */
83 cpu_restore_t cpu_restore;
10b35d99
KG		 84
85 /* Used by oprofile userspace to select the right counters */
86 char *oprofile_cpu_type;
87
88 /* Processor specific oprofile operations */
32a33994 89 enum powerpc_oprofile_type oprofile_type;
80f15dc7 90
e78dbc80
MN		 91 /* Bit locations inside the mmcra change */
92 unsigned long oprofile_mmcra_sihv;
93 unsigned long oprofile_mmcra_sipr;
94
95 /* Bits to clear during an oprofile exception */
96 unsigned long oprofile_mmcra_clear;
97
80f15dc7
PM		 98 /* Name of processor class, for the ELF AT_PLATFORM entry */
99 char *platform;
10b35d99
KG		 100};
101
10b35d99 102extern struct cpu_spec *cur_cpu_spec;
10b35d99 103
42c4aaad
BH		 104extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
105
974a76f5 106extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
0909c8c2
BH		 107extern void do_feature_fixups(unsigned long value, void *fixup_start,
108 void *fixup_end);
9b6b563c 109
10b35d99
KG		 110#endif /* __ASSEMBLY__ */
111
112/* CPU kernel features */
113
114/* Retain the 32b definitions all use bottom half of word */
4508dc21 115#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
10b35d99
KG		 116#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
117#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
118#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
119#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
120#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
121#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
122#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
123#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
124#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
125#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
126#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
127#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
128#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
129#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
130#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
131#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
132#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
133#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
134#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
3d15910b 135#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
fab5db97
PM		 136#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
137#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
aa42c69c 138#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
4508dc21 139#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
5e14d21e 140#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
10b35d99 141
3965f8c5
PM		 142/*
143 * Add the 64-bit processor unique features in the top half of the word;
144 * on 32-bit, make the names available but defined to be 0.
145 */
10b35d99 146#ifdef __powerpc64__
3965f8c5 147#define LONG_ASM_CONST(x) ASM_CONST(x)
10b35d99 148#else
3965f8c5 149#define LONG_ASM_CONST(x) 0
10b35d99
KG		 150#endif
151
3965f8c5
PM		 152#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
153#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
154#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
155#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
156#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
157#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
158#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
159#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
3965f8c5
PM		 160#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
161#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
162#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
163#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
859deea9 164#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
974a76f5 165#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
4c198557 166#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
1189be65 167#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
3965f8c5 168
10b35d99
KG		 169#ifndef __ASSEMBLY__
170
0470466d
SR		 171#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
172 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
173 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
10b35d99
KG		 174
175/* We only set the altivec features if the kernel was compiled with altivec
176 * support
177 */
178#ifdef CONFIG_ALTIVEC
179#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
180#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
181#else
182#define CPU_FTR_ALTIVEC_COMP 0
183#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
184#endif
185
5e14d21e
KG		 186/* We only set the spe features if the kernel was compiled with spe
187 * support
188 */
189#ifdef CONFIG_SPE
190#define CPU_FTR_SPE_COMP CPU_FTR_SPE
191#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
192#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
193#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
194#else
195#define CPU_FTR_SPE_COMP 0
196#define PPC_FEATURE_HAS_SPE_COMP 0
197#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
198#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
199#endif
200
11af1192
SW		 201/* We need to mark all pages as being coherent if we're SMP or we have a
202 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
203 * require it for PCI "streaming/prefetch" to work properly.
10b35d99 204 */
1775dbbc 205#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
11af1192 206 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
10b35d99
KG		 207#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
208#else
209#define CPU_FTR_COMMON 0
210#endif
211
212/* The powersave features NAP & DOZE seems to confuse BDI when
213 debugging. So if a BDI is used, disable theses
214 */
215#ifndef CONFIG_BDI_SWITCH
216#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
217#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
218#else
219#define CPU_FTR_MAYBE_CAN_DOZE 0
220#define CPU_FTR_MAYBE_CAN_NAP 0
221#endif
222
223#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
224 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
225 !defined(CONFIG_BOOKE))
226
4508dc21
DG		 227#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
228 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
229#define CPU_FTRS_603 (CPU_FTR_COMMON | \
7c92943c 230 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
fab5db97 231 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 232#define CPU_FTRS_604 (CPU_FTR_COMMON | \
fab5db97
PM		 233 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
234 CPU_FTR_PPC_LE)
4508dc21 235#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
7c92943c 236 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97 237 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 238#define CPU_FTRS_740 (CPU_FTR_COMMON | \
7c92943c 239 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 240 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
241 CPU_FTR_PPC_LE)
4508dc21 242#define CPU_FTRS_750 (CPU_FTR_COMMON | \
7c92943c 243 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
fab5db97
PM		 244 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
245 CPU_FTR_PPC_LE)
b6f41cc8
JB		 246#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
247#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
248#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
249#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
250 CPU_FTR_HAS_HIGH_BATS)
251#define CPU_FTRS_750GX (CPU_FTRS_750FX)
4508dc21 252#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
7c92943c
SR		 253 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
254 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 255 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 256#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
7c92943c
SR		 257 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
258 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
fab5db97 259 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
4508dc21 260#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
7c92943c
SR		 261 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
262 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
fab5db97 263 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 264#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
7c92943c
SR		 265 CPU_FTR_USE_TB | \
266 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
267 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
268 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
fab5db97 269 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 270#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
7c92943c
SR		 271 CPU_FTR_USE_TB | \
272 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
273 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
fab5db97 274 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 275#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
7c92943c
SR		 276 CPU_FTR_USE_TB | \
277 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
278 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 279 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 280#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
7c92943c
SR		 281 CPU_FTR_USE_TB | \
282 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
283 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
284 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
fab5db97 285 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
4508dc21 286#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
7c92943c
SR		 287 CPU_FTR_USE_TB | \
288 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
289 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
290 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 291 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 292#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
7c92943c
SR		 293 CPU_FTR_USE_TB | \
294 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
295 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
296 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 297 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
4508dc21 298#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
7c92943c
SR		 299 CPU_FTR_USE_TB | \
300 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
301 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
302 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 303 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 304#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
7c92943c
SR		 305 CPU_FTR_USE_TB | \
306 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
307 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
308 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
fab5db97 309 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
4508dc21 310#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
3d372548
JY		 311 CPU_FTR_USE_TB | \
312 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
313 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
314 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
315 CPU_FTR_PPC_LE)
4508dc21 316#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
7c92943c 317 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
11af1192 318#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
7c92943c 319 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
4508dc21 320#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
7c92943c
SR		 321 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
322 CPU_FTR_COMMON)
4508dc21 323#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
aa42c69c
KP		 324 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
325 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
4508dc21 326#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
7c92943c 327 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
4508dc21
DG		 328#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
329#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
330#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
5e14d21e
KG		 331#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
332 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
333 CPU_FTR_UNIFIED_ID_CACHE)
334#define CPU_FTRS_E500 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
335 CPU_FTR_NODSISRALIGN)
336#define CPU_FTRS_E500_2 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
7c92943c
SR		 337 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
338#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
0b8e2e13
ME		 339
340/* 64-bit CPUs */
4508dc21 341#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | \
fab5db97 342 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
4508dc21 343#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | \
7c92943c
SR		 344 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
345 CPU_FTR_MMCRA | CPU_FTR_CTRL)
4508dc21 346#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | \
00243000
OJ		 347 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
348 CPU_FTR_MMCRA)
4508dc21 349#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | \
00243000 350 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 351 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
4508dc21 352#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | \
00243000 353 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c
SR		 354 CPU_FTR_MMCRA | CPU_FTR_SMT | \
355 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
e78dbc80 356 CPU_FTR_PURR)
4508dc21 357#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | \
00243000 358 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
03054d51
AB		 359 CPU_FTR_MMCRA | CPU_FTR_SMT | \
360 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
4c198557
AB		 361 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
362 CPU_FTR_DSCR)
4508dc21 363#define CPU_FTRS_CELL (CPU_FTR_USE_TB | \
00243000 364 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
7c92943c 365 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
859deea9 366 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
4508dc21 367#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
b3ebd1d8
OJ		 368 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
369 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
370 CPU_FTR_PURR | CPU_FTR_REAL_LE)
4508dc21 371#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
7c92943c 372 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
10b35d99 373
2406f606 374#ifdef __powerpc64__
7c92943c
SR		 375#define CPU_FTRS_POSSIBLE \
376 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
03054d51 377 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
1189be65 378 CPU_FTRS_CELL | CPU_FTRS_PA6T | CPU_FTR_1T_SEGMENT)
2406f606 379#else
7c92943c
SR		 380enum {
381 CPU_FTRS_POSSIBLE =
10b35d99
KG		 382#if CLASSIC_PPC
383 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
384 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
385 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
386 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
387 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
388 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
389 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
aa42c69c
KP		 390 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
391 CPU_FTRS_CLASSIC32 |
10b35d99
KG		 392#else
393 CPU_FTRS_GENERIC_32 |
394#endif
10b35d99
KG		 395#ifdef CONFIG_8xx
396 CPU_FTRS_8XX |
397#endif
398#ifdef CONFIG_40x
399 CPU_FTRS_40X |
400#endif
401#ifdef CONFIG_44x
402 CPU_FTRS_44X |
403#endif
404#ifdef CONFIG_E200
405 CPU_FTRS_E200 |
406#endif
407#ifdef CONFIG_E500
408 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
409#endif
10b35d99 410 0,
7c92943c
SR		 411};
412#endif /* __powerpc64__ */
10b35d99 413
2406f606 414#ifdef __powerpc64__
7c92943c
SR		 415#define CPU_FTRS_ALWAYS \
416 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
03054d51 417 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
b3ebd1d8 418 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
2406f606 419#else
7c92943c
SR		 420enum {
421 CPU_FTRS_ALWAYS =
10b35d99
KG		 422#if CLASSIC_PPC
423 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
424 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
425 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
426 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
427 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
428 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
429 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
aa42c69c
KP		 430 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
431 CPU_FTRS_CLASSIC32 &
10b35d99
KG		 432#else
433 CPU_FTRS_GENERIC_32 &
434#endif
10b35d99
KG		 435#ifdef CONFIG_8xx
436 CPU_FTRS_8XX &
437#endif
438#ifdef CONFIG_40x
439 CPU_FTRS_40X &
440#endif
441#ifdef CONFIG_44x
442 CPU_FTRS_44X &
443#endif
444#ifdef CONFIG_E200
445 CPU_FTRS_E200 &
446#endif
447#ifdef CONFIG_E500
448 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
449#endif
10b35d99
KG		 450 CPU_FTRS_POSSIBLE,
451};
7c92943c 452#endif /* __powerpc64__ */
10b35d99
KG		 453
454static inline int cpu_has_feature(unsigned long feature)
455{
456 return (CPU_FTRS_ALWAYS & feature) ||
457 (CPU_FTRS_POSSIBLE
10b35d99 458 & cur_cpu_spec->cpu_features
10b35d99
KG		 459 & feature);
460}
461
462#endif /* !__ASSEMBLY__ */
463
464#ifdef __ASSEMBLY__
465
7aeb7324 466#define BEGIN_FTR_SECTION_NESTED(label) label:
0909c8c2 467#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
7aeb7324 468#define END_FTR_SECTION_NESTED(msk, val, label) \
0909c8c2 469 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
7aeb7324 470#define END_FTR_SECTION(msk, val) \
0909c8c2 471 END_FTR_SECTION_NESTED(msk, val, 97)
7aeb7324 472
10b35d99
KG		 473#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
474#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
475#endif /* __ASSEMBLY__ */
476
477#endif /* __KERNEL__ */
478#endif /* __ASM_POWERPC_CPUTABLE_H */
Linux 6.x block layer and io_uring tree(s)