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net/mlx4_core: Mask out host side virtualization features for guests
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
4d531aa8 94 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
540b3a39 112 [53] = "Port ETS Scheduler support",
4d531aa8 113 [55] = "Port link type sensing support",
00f5ce99 114 [59] = "Port management change event support",
08ff3235
OG		 115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
225c7b1f
RD		 117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 122 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
b3416f44
SP		 126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 131 [2] = "RSS XOR Hash Function support",
56cb4567 132 [3] = "Device managed flow steering support",
d998735f 133 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
b01978ca 136 [7] = "FSM (MAC anti-spoofing) support",
7ffdf726 137 [8] = "Dynamic QP updates support",
56cb4567 138 [9] = "Device managed flow steering IPoIB support",
114840c3 139 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
77507aa2
IS		 140 [11] = "MAD DEMUX (Secure-Host) support",
141 [12] = "Large cache line (>64B) CQE stride support",
adbc7ac5 142 [13] = "Large cache line (>64B) EQE stride support",
a53e3e8c 143 [14] = "Ethernet protocol control support",
d475c95b 144 [15] = "Ethernet Backplane autoneg support",
7ae0e400 145 [16] = "CONFIG DEV support",
de966c59
MB		 146 [17] = "Asymmetric EQs support",
147 [18] = "More than 80 VFs support"
b3416f44
SP		 148 };
149 int i;
150
151 for (i = 0; i < ARRAY_SIZE(fname); ++i)
152 if (fname[i] && (flags & (1LL << i)))
153 mlx4_dbg(dev, " %s\n", fname[i]);
154}
155
2d928651
VS		 156int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
157{
158 struct mlx4_cmd_mailbox *mailbox;
159 u32 *inbox;
160 int err = 0;
161
162#define MOD_STAT_CFG_IN_SIZE 0x100
163
164#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
165#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
166
167 mailbox = mlx4_alloc_cmd_mailbox(dev);
168 if (IS_ERR(mailbox))
169 return PTR_ERR(mailbox);
170 inbox = mailbox->buf;
171
2d928651
VS		 172 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
173 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
174
175 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 176 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 177
178 mlx4_free_cmd_mailbox(dev, mailbox);
179 return err;
180}
181
e8c4265b
MB		 182int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave)
183{
184 struct mlx4_cmd_mailbox *mailbox;
185 u32 *outbox;
186 u8 in_modifier;
187 u8 field;
188 u16 field16;
189 int err;
190
191#define QUERY_FUNC_BUS_OFFSET 0x00
192#define QUERY_FUNC_DEVICE_OFFSET 0x01
193#define QUERY_FUNC_FUNCTION_OFFSET 0x01
194#define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
195#define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
196#define QUERY_FUNC_MAX_EQ_OFFSET 0x06
197#define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
198
199 mailbox = mlx4_alloc_cmd_mailbox(dev);
200 if (IS_ERR(mailbox))
201 return PTR_ERR(mailbox);
202 outbox = mailbox->buf;
203
204 in_modifier = slave;
e8c4265b
MB		 205
206 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0,
207 MLX4_CMD_QUERY_FUNC,
208 MLX4_CMD_TIME_CLASS_A,
209 MLX4_CMD_NATIVE);
210 if (err)
211 goto out;
212
213 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
214 func->bus = field & 0xf;
215 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
216 func->device = field & 0xf1;
217 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
218 func->function = field & 0x7;
219 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
220 func->physical_function = field & 0xf;
221 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
222 func->rsvd_eqs = field16 & 0xffff;
223 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
224 func->max_eq = field16 & 0xffff;
225 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
226 func->rsvd_uars = field & 0x0f;
227
228 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
229 func->bus, func->device, func->function, func->physical_function,
230 func->max_eq, func->rsvd_eqs, func->rsvd_uars);
231
232out:
233 mlx4_free_cmd_mailbox(dev, mailbox);
234 return err;
235}
236
5cc914f1
MA		 237int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
238 struct mlx4_vhcr *vhcr,
239 struct mlx4_cmd_mailbox *inbox,
240 struct mlx4_cmd_mailbox *outbox,
241 struct mlx4_cmd_info *cmd)
242{
5a0d0a61 243 struct mlx4_priv *priv = mlx4_priv(dev);
99ec41d0
JM		 244 u8 field, port;
245 u32 size, proxy_qp, qkey;
5cc914f1 246 int err = 0;
7ae0e400 247 struct mlx4_func func;
5cc914f1
MA		 248
249#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
250#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 251#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 252#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 253#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
254#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
255#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
256#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
257#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
258#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 259#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 260#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 261
eb456a68
JM		 262#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
263#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
264#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
265#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
266#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
267#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
268
105c320f
JM		 269#define QUERY_FUNC_CAP_FMR_FLAG 0x80
270#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
271#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 272#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
105c320f
JM		 273
274/* when opcode modifier = 1 */
5cc914f1 275#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
99ec41d0 276#define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
73e74ab4
HHZ		 277#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
278#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 279
47605df9
JM		 280#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
281#define QUERY_FUNC_CAP_QP0_PROXY 0x14
282#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
283#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
8e1a28e8 284#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
47605df9 285
73e74ab4
HHZ		 286#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
287#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
eb17711b 288#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
99ec41d0 289#define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
105c320f 290
73e74ab4 291#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
7ae0e400 292#define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
105c320f 293
5cc914f1 294 if (vhcr->op_modifier == 1) {
449fc488
MB		 295 struct mlx4_active_ports actv_ports =
296 mlx4_get_active_ports(dev, slave);
297 int converted_port = mlx4_slave_convert_port(
298 dev, slave, vhcr->in_modifier);
299
300 if (converted_port < 0)
301 return -EINVAL;
302
303 vhcr->in_modifier = converted_port;
449fc488
MB		 304 /* phys-port = logical-port */
305 field = vhcr->in_modifier -
306 find_first_bit(actv_ports.ports, dev->caps.num_ports);
47605df9
JM		 307 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
308
99ec41d0
JM		 309 port = vhcr->in_modifier;
310 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
311
312 /* Set nic_info bit to mark new fields support */
313 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
314
315 if (mlx4_vf_smi_enabled(dev, slave, port) &&
316 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
317 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
318 MLX4_PUT(outbox->buf, qkey,
319 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
320 }
321 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
322
47605df9 323 /* size is now the QP number */
99ec41d0 324 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
47605df9
JM		 325 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
326
327 size += 2;
328 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
329
99ec41d0
JM		 330 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
331 proxy_qp += 2;
332 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
47605df9 333
8e1a28e8
HHZ		 334 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
335 QUERY_FUNC_CAP_PHYS_PORT_ID);
336
5cc914f1 337 } else if (vhcr->op_modifier == 0) {
449fc488
MB		 338 struct mlx4_active_ports actv_ports =
339 mlx4_get_active_ports(dev, slave);
eb456a68
JM		 340 /* enable rdma and ethernet interfaces, and new quota locations */
341 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
342 QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1
MA		 343 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
344
449fc488
MB		 345 field = min(
346 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
347 dev->caps.num_ports);
5cc914f1
MA		 348 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
349
08ff3235 350 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 351 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
352
105c320f
JM		 353 field = 0; /* protected FMR support not available as yet */
354 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
355
5a0d0a61 356 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 357 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 358 size = dev->caps.num_qps;
359 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 360
5a0d0a61 361 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 362 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 363 size = dev->caps.num_srqs;
364 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 365
5a0d0a61 366 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 367 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 368 size = dev->caps.num_cqs;
369 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1 370
7ae0e400
MB		 371 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
372 mlx4_QUERY_FUNC(dev, &func, slave)) {
373 size = vhcr->in_modifier &
374 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
375 dev->caps.num_eqs :
376 rounddown_pow_of_two(dev->caps.num_eqs);
377 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
378 size = dev->caps.reserved_eqs;
379 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
380 } else {
381 size = vhcr->in_modifier &
382 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
383 func.max_eq :
384 rounddown_pow_of_two(func.max_eq);
385 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
386 size = func.rsvd_eqs;
387 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
388 }
5cc914f1 389
5a0d0a61 390 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 391 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 392 size = dev->caps.num_mpts;
393 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 394
5a0d0a61 395 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 396 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 397 size = dev->caps.num_mtts;
398 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 399
400 size = dev->caps.num_mgms + dev->caps.num_amgms;
401 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 402 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1
MA		 403
404 } else
405 err = -EINVAL;
406
407 return err;
408}
409
225c6c8c 410int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
47605df9 411 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 412{
413 struct mlx4_cmd_mailbox *mailbox;
414 u32 *outbox;
47605df9 415 u8 field, op_modifier;
99ec41d0 416 u32 size, qkey;
eb456a68 417 int err = 0, quotas = 0;
7ae0e400 418 u32 in_modifier;
5cc914f1 419
47605df9 420 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
7ae0e400
MB		 421 in_modifier = op_modifier ? gen_or_port :
422 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS;
5cc914f1
MA		 423
424 mailbox = mlx4_alloc_cmd_mailbox(dev);
425 if (IS_ERR(mailbox))
426 return PTR_ERR(mailbox);
427
7ae0e400 428 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier,
47605df9 429 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 430 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
431 if (err)
432 goto out;
433
434 outbox = mailbox->buf;
435
47605df9
JM		 436 if (!op_modifier) {
437 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
438 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
439 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
440 err = -EPROTONOSUPPORT;
441 goto out;
442 }
443 func_cap->flags = field;
eb456a68 444 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 445
47605df9
JM		 446 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
447 func_cap->num_ports = field;
5cc914f1 448
47605df9
JM		 449 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
450 func_cap->pf_context_behaviour = size;
5cc914f1 451
eb456a68
JM		 452 if (quotas) {
453 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
454 func_cap->qp_quota = size & 0xFFFFFF;
455
456 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
457 func_cap->srq_quota = size & 0xFFFFFF;
458
459 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
460 func_cap->cq_quota = size & 0xFFFFFF;
461
462 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
463 func_cap->mpt_quota = size & 0xFFFFFF;
464
465 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
466 func_cap->mtt_quota = size & 0xFFFFFF;
467
468 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
469 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 470
eb456a68
JM		 471 } else {
472 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
473 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 474
eb456a68
JM		 475 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
476 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 477
eb456a68
JM		 478 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
479 func_cap->cq_quota = size & 0xFFFFFF;
480
481 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
482 func_cap->mpt_quota = size & 0xFFFFFF;
483
484 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
485 func_cap->mtt_quota = size & 0xFFFFFF;
486
487 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
488 func_cap->mcg_quota = size & 0xFFFFFF;
489 }
47605df9
JM		 490 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
491 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 492
47605df9
JM		 493 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
494 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 495
47605df9
JM		 496 goto out;
497 }
5cc914f1 498
47605df9
JM		 499 /* logical port query */
500 if (gen_or_port > dev->caps.num_ports) {
501 err = -EINVAL;
502 goto out;
503 }
5cc914f1 504
eb17711b 505 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
47605df9 506 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
bc82878b 507 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
47605df9
JM		 508 mlx4_err(dev, "VLAN is enforced on this port\n");
509 err = -EPROTONOSUPPORT;
5cc914f1 510 goto out;
47605df9 511 }
5cc914f1 512
eb17711b 513 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 514 mlx4_err(dev, "Force mac is enabled on this port\n");
515 err = -EPROTONOSUPPORT;
516 goto out;
5cc914f1 517 }
47605df9 518 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 519 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
520 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
1a91de28 521 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
47605df9
JM		 522 err = -EPROTONOSUPPORT;
523 goto out;
524 }
525 }
5cc914f1 526
47605df9
JM		 527 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
528 func_cap->physical_port = field;
529 if (func_cap->physical_port != gen_or_port) {
530 err = -ENOSYS;
531 goto out;
5cc914f1
MA		 532 }
533
99ec41d0
JM		 534 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
535 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
536 func_cap->qp0_qkey = qkey;
537 } else {
538 func_cap->qp0_qkey = 0;
539 }
540
47605df9
JM		 541 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
542 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
543
544 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
545 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
546
547 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
548 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
549
550 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
551 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
552
8e1a28e8
HHZ		 553 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
554 MLX4_GET(func_cap->phys_port_id, outbox,
555 QUERY_FUNC_CAP_PHYS_PORT_ID);
556
5cc914f1
MA		 557 /* All other resources are allocated by the master, but we still report
558 * 'num' and 'reserved' capabilities as follows:
559 * - num remains the maximum resource index
560 * - 'num - reserved' is the total available objects of a resource, but
561 * resource indices may be less than 'reserved'
562 * TODO: set per-resource quotas */
563
564out:
565 mlx4_free_cmd_mailbox(dev, mailbox);
566
567 return err;
568}
569
225c7b1f
RD		 570int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
571{
572 struct mlx4_cmd_mailbox *mailbox;
573 u32 *outbox;
574 u8 field;
ccf86321 575 u32 field32, flags, ext_flags;
225c7b1f
RD		 576 u16 size;
577 u16 stat_rate;
578 int err;
5ae2a7a8 579 int i;
225c7b1f
RD		 580
581#define QUERY_DEV_CAP_OUT_SIZE 0x100
582#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
583#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
584#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
585#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
586#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
587#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
588#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
589#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
590#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
591#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
592#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
593#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
594#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
595#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
596#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
597#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
598#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
599#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
7ae0e400 600#define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
225c7b1f
RD		 601#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
602#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
603#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 604#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 605#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 606#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
607#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
608#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
609#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
610#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 611#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 612#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
613#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 614#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 615#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 616#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 617#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
618#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
619#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
620#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
621#define QUERY_DEV_CAP_BF_OFFSET 0x4c
622#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
623#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
624#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
625#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
626#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
627#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
628#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
629#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
630#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
631#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
632#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
633#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 634#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
635#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 636#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
3f7fb021 637#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
4de65803 638#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
0ff1fb65
HHZ		 639#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
640#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
77507aa2 641#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
adbc7ac5 642#define QUERY_DEV_CAP_ETH_PROT_CTRL_OFFSET 0x7a
225c7b1f
RD		 643#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
644#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
645#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
646#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
647#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
648#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
649#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
650#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
651#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
652#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 653#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
d475c95b 654#define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
225c7b1f
RD		 655#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
656#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
a53e3e8c 657#define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
955154fa 658#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
7ffdf726 659#define QUERY_DEV_CAP_VXLAN 0x9e
114840c3 660#define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
225c7b1f 661
b3416f44 662 dev_cap->flags2 = 0;
225c7b1f
RD		 663 mailbox = mlx4_alloc_cmd_mailbox(dev);
664 if (IS_ERR(mailbox))
665 return PTR_ERR(mailbox);
666 outbox = mailbox->buf;
667
668 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 669 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 670 if (err)
671 goto out;
672
673 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
674 dev_cap->reserved_qps = 1 << (field & 0xf);
675 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
676 dev_cap->max_qps = 1 << (field & 0x1f);
677 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
678 dev_cap->reserved_srqs = 1 << (field >> 4);
679 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
680 dev_cap->max_srqs = 1 << (field & 0x1f);
681 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
682 dev_cap->max_cq_sz = 1 << field;
683 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
684 dev_cap->reserved_cqs = 1 << (field & 0xf);
685 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
686 dev_cap->max_cqs = 1 << (field & 0x1f);
687 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
688 dev_cap->max_mpts = 1 << (field & 0x3f);
689 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
7c68dd43 690 dev_cap->reserved_eqs = 1 << (field & 0xf);
225c7b1f 691 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 692 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 693 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
694 dev_cap->reserved_mtts = 1 << (field >> 4);
695 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
696 dev_cap->max_mrw_sz = 1 << field;
697 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
698 dev_cap->reserved_mrws = 1 << (field & 0xf);
699 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
700 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
7ae0e400
MB		 701 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
702 dev_cap->num_sys_eqs = size & 0xfff;
225c7b1f
RD		 703 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
704 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
705 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
706 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 707 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
708 field &= 0x1f;
709 if (!field)
710 dev_cap->max_gso_sz = 0;
711 else
712 dev_cap->max_gso_sz = 1 << field;
713
b3416f44
SP		 714 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
715 if (field & 0x20)
716 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
717 if (field & 0x10)
718 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
719 field &= 0xf;
720 if (field) {
721 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
722 dev_cap->max_rss_tbl_sz = 1 << field;
723 } else
724 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 725 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
726 dev_cap->max_rdma_global = 1 << (field & 0x3f);
727 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
728 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 729 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 730 dev_cap->num_ports = field & 0xf;
149983af
DB		 731 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
732 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 733 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
734 if (field & 0x80)
735 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
736 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
4de65803
MB		 737 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
738 if (field & 0x80)
739 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
0ff1fb65
HHZ		 740 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
741 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 742 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
743 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 744 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
745 if (field & 0x80)
746 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 747 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 748 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 749 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 750 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
751 dev_cap->reserved_uars = field >> 4;
752 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
753 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
754 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
755 dev_cap->min_page_sz = 1 << field;
756
757 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
758 if (field & 0x80) {
759 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
760 dev_cap->bf_reg_size = 1 << (field & 0x1f);
761 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 762 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 763 field = 3;
225c7b1f
RD		 764 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
765 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
766 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
767 } else {
768 dev_cap->bf_reg_size = 0;
769 mlx4_dbg(dev, "BlueFlame not available\n");
770 }
771
772 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
773 dev_cap->max_sq_sg = field;
774 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
775 dev_cap->max_sq_desc_sz = size;
776
777 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
778 dev_cap->max_qp_per_mcg = 1 << field;
779 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
780 dev_cap->reserved_mgms = field & 0xf;
781 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
782 dev_cap->max_mcgs = 1 << field;
783 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
784 dev_cap->reserved_pds = field >> 4;
785 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
786 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 787 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
788 dev_cap->reserved_xrcds = field >> 4;
426dd00d 789 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 790 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 791
792 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
793 dev_cap->rdmarc_entry_sz = size;
794 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
795 dev_cap->qpc_entry_sz = size;
796 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
797 dev_cap->aux_entry_sz = size;
798 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
799 dev_cap->altc_entry_sz = size;
800 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
801 dev_cap->eqc_entry_sz = size;
802 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
803 dev_cap->cqc_entry_sz = size;
804 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
805 dev_cap->srq_entry_sz = size;
806 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
807 dev_cap->cmpt_entry_sz = size;
808 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
809 dev_cap->mtt_entry_sz = size;
810 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
811 dev_cap->dmpt_entry_sz = size;
812
813 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
814 dev_cap->max_srq_sz = 1 << field;
815 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
816 dev_cap->max_qp_sz = 1 << field;
817 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
818 dev_cap->resize_srq = field & 1;
819 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
820 dev_cap->max_rq_sg = field;
821 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
822 dev_cap->max_rq_desc_sz = size;
77507aa2 823 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
adbc7ac5
SM		 824 if (field & (1 << 5))
825 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
77507aa2
IS		 826 if (field & (1 << 6))
827 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
828 if (field & (1 << 7))
829 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
225c7b1f
RD		 830 MLX4_GET(dev_cap->bmme_flags, outbox,
831 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
d475c95b
MB		 832 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
833 if (field & 0x20)
834 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
225c7b1f
RD		 835 MLX4_GET(dev_cap->reserved_lkey, outbox,
836 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
a53e3e8c
SM		 837 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
838 if (field32 & (1 << 0))
839 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
955154fa
MB		 840 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
841 if (field & 1<<6)
5930e8d0 842 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
7ffdf726
OG		 843 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
844 if (field & 1<<3)
845 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
225c7b1f
RD		 846 MLX4_GET(dev_cap->max_icm_sz, outbox,
847 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 848 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
849 MLX4_GET(dev_cap->max_counters, outbox,
850 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 851
114840c3
JM		 852 MLX4_GET(field32, outbox,
853 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
854 if (field32 & (1 << 0))
855 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
856
3f7fb021 857 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 858 if (field32 & (1 << 16))
859 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
3f7fb021
RE		 860 if (field32 & (1 << 26))
861 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 862 if (field32 & (1 << 20))
863 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
de966c59
MB		 864 if (field32 & (1 << 21))
865 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
3f7fb021 866
5ae2a7a8
RD		 867 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
868 for (i = 1; i <= dev_cap->num_ports; ++i) {
869 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
870 dev_cap->max_vl[i] = field >> 4;
871 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 872 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 873 dev_cap->max_port_width[i] = field & 0xf;
874 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
875 dev_cap->max_gids[i] = 1 << (field & 0xf);
876 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
877 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
878 }
879 } else {
7ff93f8b 880#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 881#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 882#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 883#define QUERY_PORT_WIDTH_OFFSET 0x06
884#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 885#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 886#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 887#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 888#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
889#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
890#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 891
892 for (i = 1; i <= dev_cap->num_ports; ++i) {
893 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 894 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 895 if (err)
896 goto out;
897
7ff93f8b
YP		 898 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
899 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 900 dev_cap->suggested_type[i] = (field >> 3) & 1;
901 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 902 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 903 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 904 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
905 dev_cap->max_port_width[i] = field & 0xf;
906 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
907 dev_cap->max_gids[i] = 1 << (field >> 4);
908 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
909 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
910 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 911 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
912 dev_cap->log_max_macs[i] = field & 0xf;
913 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 914 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
915 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 916 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
917 dev_cap->trans_type[i] = field32 >> 24;
918 dev_cap->vendor_oui[i] = field32 & 0xffffff;
919 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
920 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 921 }
922 }
923
95d04f07
RD		 924 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
925 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 926
927 /*
928 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
929 * we can't use any EQs whose doorbell falls on that page,
930 * even if the EQ itself isn't reserved.
931 */
7ae0e400
MB		 932 if (dev_cap->num_sys_eqs == 0)
933 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
934 dev_cap->reserved_eqs);
935 else
936 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
225c7b1f
RD		 937
938 mlx4_dbg(dev, "Max ICM size %lld MB\n",
939 (unsigned long long) dev_cap->max_icm_sz >> 20);
940 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
941 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
942 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
943 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
944 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
945 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
7ae0e400
MB		 946 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
947 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
948 dev_cap->eqc_entry_sz);
225c7b1f
RD		 949 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
950 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
951 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
952 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
953 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
954 dev_cap->max_pds, dev_cap->reserved_mgms);
955 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
956 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
957 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 958 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 959 dev_cap->max_port_width[1]);
225c7b1f
RD		 960 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
961 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
962 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
963 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 964 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 965 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 966 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 967
968 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 969 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 970
971out:
972 mlx4_free_cmd_mailbox(dev, mailbox);
973 return err;
974}
975
383677da
OG		 976#define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
977#define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
978#define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
979
b91cb3eb
JM		 980int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
981 struct mlx4_vhcr *vhcr,
982 struct mlx4_cmd_mailbox *inbox,
983 struct mlx4_cmd_mailbox *outbox,
984 struct mlx4_cmd_info *cmd)
985{
2a4fae14 986 u64 flags;
b91cb3eb
JM		 987 int err = 0;
988 u8 field;
383677da 989 u32 bmme_flags, field32;
449fc488
MB		 990 int real_port;
991 int slave_port;
992 int first_port;
993 struct mlx4_active_ports actv_ports;
b91cb3eb
JM		 994
995 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
996 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
997 if (err)
998 return err;
999
cc1ade94
SM		 1000 /* add port mng change event capability and disable mw type 1
1001 * unconditionally to slaves
1002 */
2a4fae14
JM		 1003 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1004 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 1005 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
449fc488
MB		 1006 actv_ports = mlx4_get_active_ports(dev, slave);
1007 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
1008 for (slave_port = 0, real_port = first_port;
1009 real_port < first_port +
1010 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
1011 ++real_port, ++slave_port) {
1012 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
1013 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
1014 else
1015 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1016 }
1017 for (; slave_port < dev->caps.num_ports; ++slave_port)
1018 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
2a4fae14
JM		 1019 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1020
449fc488
MB		 1021 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1022 field &= ~0x0F;
1023 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1024 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1025
30b40c31
AV		 1026 /* For guests, disable timestamp */
1027 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1028 field &= 0x7f;
1029 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1030
7ffdf726 1031 /* For guests, disable vxlan tunneling */
57352ef4 1032 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
7ffdf726
OG		 1033 field &= 0xf7;
1034 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1035
b91cb3eb
JM		 1036 /* For guests, report Blueflame disabled */
1037 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1038 field &= 0x7f;
1039 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1040
cc1ade94 1041 /* For guests, disable mw type 2 */
57352ef4 1042 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
cc1ade94
SM		 1043 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
1044 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1045
0081c8f3
JM		 1046 /* turn off device-managed steering capability if not enabled */
1047 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1048 MLX4_GET(field, outbox->buf,
1049 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1050 field &= 0x7f;
1051 MLX4_PUT(outbox->buf, field,
1052 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1053 }
4de65803
MB		 1054
1055 /* turn off ipoib managed steering for guests */
57352ef4 1056 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
4de65803
MB		 1057 field &= ~0x80;
1058 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1059
383677da
OG		 1060 /* turn off host side virt features (VST, FSM, etc) for guests */
1061 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1062 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS |
1063 DEV_CAP_EXT_2_FLAG_FSM);
1064 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1065
b91cb3eb
JM		 1066 return 0;
1067}
1068
5cc914f1
MA		 1069int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1070 struct mlx4_vhcr *vhcr,
1071 struct mlx4_cmd_mailbox *inbox,
1072 struct mlx4_cmd_mailbox *outbox,
1073 struct mlx4_cmd_info *cmd)
1074{
0eb62b93 1075 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 1076 u64 def_mac;
1077 u8 port_type;
6634961c 1078 u16 short_field;
5cc914f1 1079 int err;
948e306d 1080 int admin_link_state;
449fc488
MB		 1081 int port = mlx4_slave_convert_port(dev, slave,
1082 vhcr->in_modifier & 0xFF);
5cc914f1 1083
105c320f 1084#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 1085#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 1086#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1087#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 1088
449fc488
MB		 1089 if (port < 0)
1090 return -EINVAL;
1091
a7401b9c
JM		 1092 /* Protect against untrusted guests: enforce that this is the
1093 * QUERY_PORT general query.
1094 */
1095 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
1096 return -EINVAL;
1097
1098 vhcr->in_modifier = port;
449fc488 1099
5cc914f1
MA		 1100 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1101 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1102 MLX4_CMD_NATIVE);
1103
1104 if (!err && dev->caps.function != slave) {
0508ad64 1105 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 1106 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1107
1108 /* get port type - currently only eth is enabled */
1109 MLX4_GET(port_type, outbox->buf,
1110 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1111
105c320f
JM		 1112 /* No link sensing allowed */
1113 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1114 /* set port type to currently operating port type */
1115 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 1116
948e306d
RE		 1117 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1118 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1119 port_type |= MLX4_PORT_LINK_UP_MASK;
1120 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1121 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1122
5cc914f1
MA		 1123 MLX4_PUT(outbox->buf, port_type,
1124 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c 1125
b6ffaeff 1126 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
449fc488 1127 short_field = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 1128 else
1129 short_field = 1; /* slave max gids */
6634961c
JM		 1130 MLX4_PUT(outbox->buf, short_field,
1131 QUERY_PORT_CUR_MAX_GID_OFFSET);
1132
1133 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1134 MLX4_PUT(outbox->buf, short_field,
1135 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 1136 }
1137
1138 return err;
1139}
1140
6634961c
JM		 1141int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1142 int *gid_tbl_len, int *pkey_tbl_len)
1143{
1144 struct mlx4_cmd_mailbox *mailbox;
1145 u32 *outbox;
1146 u16 field;
1147 int err;
1148
1149 mailbox = mlx4_alloc_cmd_mailbox(dev);
1150 if (IS_ERR(mailbox))
1151 return PTR_ERR(mailbox);
1152
1153 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1154 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1155 MLX4_CMD_WRAPPED);
1156 if (err)
1157 goto out;
1158
1159 outbox = mailbox->buf;
1160
1161 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1162 *gid_tbl_len = field;
1163
1164 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1165 *pkey_tbl_len = field;
1166
1167out:
1168 mlx4_free_cmd_mailbox(dev, mailbox);
1169 return err;
1170}
1171EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1172
225c7b1f
RD		 1173int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1174{
1175 struct mlx4_cmd_mailbox *mailbox;
1176 struct mlx4_icm_iter iter;
1177 __be64 *pages;
1178 int lg;
1179 int nent = 0;
1180 int i;
1181 int err = 0;
1182 int ts = 0, tc = 0;
1183
1184 mailbox = mlx4_alloc_cmd_mailbox(dev);
1185 if (IS_ERR(mailbox))
1186 return PTR_ERR(mailbox);
225c7b1f
RD		 1187 pages = mailbox->buf;
1188
1189 for (mlx4_icm_first(icm, &iter);
1190 !mlx4_icm_last(&iter);
1191 mlx4_icm_next(&iter)) {
1192 /*
1193 * We have to pass pages that are aligned to their
1194 * size, so find the least significant 1 in the
1195 * address or size and use that as our log2 size.
1196 */
1197 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1198 if (lg < MLX4_ICM_PAGE_SHIFT) {
1a91de28
JP		 1199 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1200 MLX4_ICM_PAGE_SIZE,
1201 (unsigned long long) mlx4_icm_addr(&iter),
1202 mlx4_icm_size(&iter));
225c7b1f
RD		 1203 err = -EINVAL;
1204 goto out;
1205 }
1206
1207 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1208 if (virt != -1) {
1209 pages[nent * 2] = cpu_to_be64(virt);
1210 virt += 1 << lg;
1211 }
1212
1213 pages[nent * 2 + 1] =
1214 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1215 (lg - MLX4_ICM_PAGE_SHIFT));
1216 ts += 1 << (lg - 10);
1217 ++tc;
1218
1219 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1220 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 1221 MLX4_CMD_TIME_CLASS_B,
1222 MLX4_CMD_NATIVE);
225c7b1f
RD		 1223 if (err)
1224 goto out;
1225 nent = 0;
1226 }
1227 }
1228 }
1229
1230 if (nent)
f9baff50
JM		 1231 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1232 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1233 if (err)
1234 goto out;
1235
1236 switch (op) {
1237 case MLX4_CMD_MAP_FA:
1a91de28 1238 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
225c7b1f
RD		 1239 break;
1240 case MLX4_CMD_MAP_ICM_AUX:
1a91de28 1241 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
225c7b1f
RD		 1242 break;
1243 case MLX4_CMD_MAP_ICM:
1a91de28
JP		 1244 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1245 tc, ts, (unsigned long long) virt - (ts << 10));
225c7b1f
RD		 1246 break;
1247 }
1248
1249out:
1250 mlx4_free_cmd_mailbox(dev, mailbox);
1251 return err;
1252}
1253
1254int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1255{
1256 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1257}
1258
1259int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1260{
f9baff50
JM		 1261 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1262 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1263}
1264
1265
1266int mlx4_RUN_FW(struct mlx4_dev *dev)
1267{
f9baff50
JM		 1268 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1269 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1270}
1271
1272int mlx4_QUERY_FW(struct mlx4_dev *dev)
1273{
1274 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1275 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1276 struct mlx4_cmd_mailbox *mailbox;
1277 u32 *outbox;
1278 int err = 0;
1279 u64 fw_ver;
fe40900f 1280 u16 cmd_if_rev;
225c7b1f
RD		 1281 u8 lg;
1282
1283#define QUERY_FW_OUT_SIZE 0x100
1284#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1285#define QUERY_FW_PPF_ID 0x09
fe40900f 1286#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1287#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1288#define QUERY_FW_ERR_START_OFFSET 0x30
1289#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1290#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1291
1292#define QUERY_FW_SIZE_OFFSET 0x00
1293#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1294#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1295
5cc914f1
MA		 1296#define QUERY_FW_COMM_BASE_OFFSET 0x40
1297#define QUERY_FW_COMM_BAR_OFFSET 0x48
1298
ddd8a6c1
EE		 1299#define QUERY_FW_CLOCK_OFFSET 0x50
1300#define QUERY_FW_CLOCK_BAR 0x58
1301
225c7b1f
RD		 1302 mailbox = mlx4_alloc_cmd_mailbox(dev);
1303 if (IS_ERR(mailbox))
1304 return PTR_ERR(mailbox);
1305 outbox = mailbox->buf;
1306
1307 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1308 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1309 if (err)
1310 goto out;
1311
1312 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1313 /*
3e1db334 1314 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1315 * version, so swap here.
1316 */
1317 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1318 ((fw_ver & 0xffff0000ull) >> 16) |
1319 ((fw_ver & 0x0000ffffull) << 16);
1320
752a50ca
JM		 1321 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1322 dev->caps.function = lg;
1323
b91cb3eb
JM		 1324 if (mlx4_is_slave(dev))
1325 goto out;
1326
5cc914f1 1327
fe40900f 1328 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1329 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1330 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1a91de28 1331 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
fe40900f
RD		 1332 cmd_if_rev);
1333 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1334 (int) (dev->caps.fw_ver >> 32),
1335 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1336 (int) dev->caps.fw_ver & 0xffff);
1a91de28 1337 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
5ae2a7a8 1338 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1339 err = -ENODEV;
1340 goto out;
1341 }
1342
5ae2a7a8
RD		 1343 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1344 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1345
225c7b1f
RD		 1346 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1347 cmd->max_cmds = 1 << lg;
1348
fe40900f 1349 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1350 (int) (dev->caps.fw_ver >> 32),
1351 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1352 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1353 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1354
1355 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1356 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1357 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1358 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1359
1360 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1361 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1362
1363 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1364 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1365 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1366 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1367
5cc914f1
MA		 1368 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1369 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1370 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1371 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1372 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1373 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1374
ddd8a6c1
EE		 1375 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1376 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1377 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1378 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1379 fw->clock_bar, fw->clock_offset);
1380
225c7b1f
RD		 1381 /*
1382 * Round up number of system pages needed in case
1383 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1384 */
1385 fw->fw_pages =
1386 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1387 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1388
1389 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1390 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1391
1392out:
1393 mlx4_free_cmd_mailbox(dev, mailbox);
1394 return err;
1395}
1396
b91cb3eb
JM		 1397int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1398 struct mlx4_vhcr *vhcr,
1399 struct mlx4_cmd_mailbox *inbox,
1400 struct mlx4_cmd_mailbox *outbox,
1401 struct mlx4_cmd_info *cmd)
1402{
1403 u8 *outbuf;
1404 int err;
1405
1406 outbuf = outbox->buf;
1407 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1408 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1409 if (err)
1410 return err;
1411
752a50ca
JM		 1412 /* for slaves, set pci PPF ID to invalid and zero out everything
1413 * else except FW version */
b91cb3eb
JM		 1414 outbuf[0] = outbuf[1] = 0;
1415 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1416 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1417
b91cb3eb
JM		 1418 return 0;
1419}
1420
225c7b1f
RD		 1421static void get_board_id(void *vsd, char *board_id)
1422{
1423 int i;
1424
1425#define VSD_OFFSET_SIG1 0x00
1426#define VSD_OFFSET_SIG2 0xde
1427#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1428#define VSD_OFFSET_TS_BOARD_ID 0x20
1429
1430#define VSD_SIGNATURE_TOPSPIN 0x5ad
1431
1432 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1433
1434 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1435 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1436 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1437 } else {
1438 /*
1439 * The board ID is a string but the firmware byte
1440 * swaps each 4-byte word before passing it back to
1441 * us. Therefore we need to swab it before printing.
1442 */
1443 for (i = 0; i < 4; ++i)
1444 ((u32 *) board_id)[i] =
1445 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1446 }
1447}
1448
1449int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1450{
1451 struct mlx4_cmd_mailbox *mailbox;
1452 u32 *outbox;
1453 int err;
1454
1455#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1456#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1457#define QUERY_ADAPTER_VSD_OFFSET 0x20
1458
1459 mailbox = mlx4_alloc_cmd_mailbox(dev);
1460 if (IS_ERR(mailbox))
1461 return PTR_ERR(mailbox);
1462 outbox = mailbox->buf;
1463
1464 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1465 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1466 if (err)
1467 goto out;
1468
225c7b1f
RD		 1469 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1470
1471 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1472 adapter->board_id);
1473
1474out:
1475 mlx4_free_cmd_mailbox(dev, mailbox);
1476 return err;
1477}
1478
1479int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1480{
1481 struct mlx4_cmd_mailbox *mailbox;
1482 __be32 *inbox;
1483 int err;
1484
1485#define INIT_HCA_IN_SIZE 0x200
1486#define INIT_HCA_VERSION_OFFSET 0x000
1487#define INIT_HCA_VERSION 2
7ffdf726 1488#define INIT_HCA_VXLAN_OFFSET 0x0c
c57e20dc 1489#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1490#define INIT_HCA_FLAGS_OFFSET 0x014
1491#define INIT_HCA_QPC_OFFSET 0x020
1492#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1493#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1494#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1495#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1496#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1497#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1498#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
77507aa2 1499#define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
225c7b1f
RD		 1500#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1501#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1502#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1503#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
7ae0e400 1504#define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
225c7b1f
RD		 1505#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1506#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1507#define INIT_HCA_MCAST_OFFSET 0x0c0
1508#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1509#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1510#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1511#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1512#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1513#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1514#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1515#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1516#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1517#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1518#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1519#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1520#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1521#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1522#define INIT_HCA_TPT_OFFSET 0x0f0
1523#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1524#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1525#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1526#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1527#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1528#define INIT_HCA_UAR_OFFSET 0x120
1529#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1530#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1531
1532 mailbox = mlx4_alloc_cmd_mailbox(dev);
1533 if (IS_ERR(mailbox))
1534 return PTR_ERR(mailbox);
1535 inbox = mailbox->buf;
1536
225c7b1f
RD		 1537 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1538
c57e20dc
EC		 1539 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1540 (ilog2(cache_line_size()) - 4) << 5;
1541
225c7b1f
RD		 1542#if defined(__LITTLE_ENDIAN)
1543 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1544#elif defined(__BIG_ENDIAN)
1545 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1546#else
1547#error Host endianness not defined
1548#endif
1549 /* Check port for UD address vector: */
1550 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1551
8ff095ec
EC		 1552 /* Enable IPoIB checksumming if we can: */
1553 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1554 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1555
51f5f0ee
JM		 1556 /* Enable QoS support if module parameter set */
1557 if (enable_qos)
1558 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1559
f2a3f6a3
OG		 1560 /* enable counters */
1561 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1562 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1563
08ff3235
OG		 1564 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1565 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1566 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1567 dev->caps.eqe_size = 64;
1568 dev->caps.eqe_factor = 1;
1569 } else {
1570 dev->caps.eqe_size = 32;
1571 dev->caps.eqe_factor = 0;
1572 }
1573
1574 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1575 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1576 dev->caps.cqe_size = 64;
77507aa2 1577 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1578 } else {
1579 dev->caps.cqe_size = 32;
1580 }
1581
77507aa2
IS		 1582 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1583 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1584 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1585 dev->caps.eqe_size = cache_line_size();
1586 dev->caps.cqe_size = cache_line_size();
1587 dev->caps.eqe_factor = 0;
1588 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1589 (ilog2(dev->caps.eqe_size) - 5)),
1590 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1591
1592 /* User still need to know to support CQE > 32B */
1593 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1594 }
1595
225c7b1f
RD		 1596 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1597
1598 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1599 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1600 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1601 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1602 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1603 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1604 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1605 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1606 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1607 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1608 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
225c7b1f
RD		 1609 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1610 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1611
0ff1fb65
HHZ		 1612 /* steering attributes */
1613 if (dev->caps.steering_mode ==
1614 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1615 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1616 cpu_to_be32(1 <<
1617 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1618
1619 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1620 MLX4_PUT(inbox, param->log_mc_entry_sz,
1621 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1622 MLX4_PUT(inbox, param->log_mc_table_sz,
1623 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1624 /* Enable Ethernet flow steering
1625 * with udp unicast and tcp unicast
1626 */
23537b73 1627 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1628 INIT_HCA_FS_ETH_BITS_OFFSET);
1629 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1630 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1631 /* Enable IPoIB flow steering
1632 * with udp unicast and tcp unicast
1633 */
23537b73 1634 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1635 INIT_HCA_FS_IB_BITS_OFFSET);
1636 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1637 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1638 } else {
1639 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1640 MLX4_PUT(inbox, param->log_mc_entry_sz,
1641 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1642 MLX4_PUT(inbox, param->log_mc_hash_sz,
1643 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1644 MLX4_PUT(inbox, param->log_mc_table_sz,
1645 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1646 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1647 MLX4_PUT(inbox, (u8) (1 << 3),
1648 INIT_HCA_UC_STEERING_OFFSET);
1649 }
225c7b1f
RD		 1650
1651 /* TPT attributes */
1652
1653 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1654 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1655 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1656 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1657 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1658
1659 /* UAR attributes */
1660
ab9c17a0 1661 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1662 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1663
7ffdf726
OG		 1664 /* set parser VXLAN attributes */
1665 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1666 u8 parser_params = 0;
1667 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1668 }
1669
f9baff50
JM		 1670 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1671 MLX4_CMD_NATIVE);
225c7b1f
RD		 1672
1673 if (err)
1674 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1675
1676 mlx4_free_cmd_mailbox(dev, mailbox);
1677 return err;
1678}
1679
ab9c17a0
JM		 1680int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1681 struct mlx4_init_hca_param *param)
1682{
1683 struct mlx4_cmd_mailbox *mailbox;
1684 __be32 *outbox;
7b8157be 1685 u32 dword_field;
ab9c17a0 1686 int err;
08ff3235 1687 u8 byte_field;
ab9c17a0
JM		 1688
1689#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1690#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1691
1692 mailbox = mlx4_alloc_cmd_mailbox(dev);
1693 if (IS_ERR(mailbox))
1694 return PTR_ERR(mailbox);
1695 outbox = mailbox->buf;
1696
1697 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1698 MLX4_CMD_QUERY_HCA,
1699 MLX4_CMD_TIME_CLASS_B,
1700 !mlx4_is_slave(dev));
1701 if (err)
1702 goto out;
1703
1704 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1705 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1706
1707 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1708
1709 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1710 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1711 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1712 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1713 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1714 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1715 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1716 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1717 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1718 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1719 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
ab9c17a0
JM		 1720 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1721 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1722
7b8157be
JM		 1723 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1724 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1725 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1726 } else {
1727 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1728 if (byte_field & 0x8)
1729 param->steering_mode = MLX4_STEERING_MODE_B0;
1730 else
1731 param->steering_mode = MLX4_STEERING_MODE_A0;
1732 }
0ff1fb65 1733 /* steering attributes */
7b8157be 1734 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1735 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1736 MLX4_GET(param->log_mc_entry_sz, outbox,
1737 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1738 MLX4_GET(param->log_mc_table_sz, outbox,
1739 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1740 } else {
1741 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1742 MLX4_GET(param->log_mc_entry_sz, outbox,
1743 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1744 MLX4_GET(param->log_mc_hash_sz, outbox,
1745 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1746 MLX4_GET(param->log_mc_table_sz, outbox,
1747 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1748 }
ab9c17a0 1749
08ff3235
OG		 1750 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1751 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1752 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1753 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1754 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1755 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1756
77507aa2
IS		 1757 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1758 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1759 if (byte_field) {
1760 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1761 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1762 param->cqe_size = 1 << ((byte_field &
1763 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
1764 param->eqe_size = 1 << (((byte_field &
1765 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
1766 }
1767
ab9c17a0
JM		 1768 /* TPT attributes */
1769
1770 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1771 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1772 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1773 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1774 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1775
1776 /* UAR attributes */
1777
1778 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1779 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1780
1781out:
1782 mlx4_free_cmd_mailbox(dev, mailbox);
1783
1784 return err;
1785}
1786
980e9001
JM		 1787/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1788 * and real QP0 are active, so that the paravirtualized QP0 is ready
1789 * to operate */
1790static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1791{
1792 struct mlx4_priv *priv = mlx4_priv(dev);
1793 /* irrelevant if not infiniband */
1794 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1795 priv->mfunc.master.qp0_state[port].qp0_active)
1796 return 1;
1797 return 0;
1798}
1799
5cc914f1
MA		 1800int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1801 struct mlx4_vhcr *vhcr,
1802 struct mlx4_cmd_mailbox *inbox,
1803 struct mlx4_cmd_mailbox *outbox,
1804 struct mlx4_cmd_info *cmd)
1805{
1806 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1807 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1808 int err;
1809
449fc488
MB		 1810 if (port < 0)
1811 return -EINVAL;
1812
5cc914f1
MA		 1813 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1814 return 0;
1815
980e9001
JM		 1816 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1817 /* Enable port only if it was previously disabled */
1818 if (!priv->mfunc.master.init_port_ref[port]) {
1819 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1820 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1821 if (err)
1822 return err;
1823 }
1824 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1825 } else {
1826 if (slave == mlx4_master_func_num(dev)) {
1827 if (check_qp0_state(dev, slave, port) &&
1828 !priv->mfunc.master.qp0_state[port].port_active) {
1829 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1830 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1831 if (err)
1832 return err;
1833 priv->mfunc.master.qp0_state[port].port_active = 1;
1834 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1835 }
1836 } else
1837 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1838 }
1839 ++priv->mfunc.master.init_port_ref[port];
1840 return 0;
1841}
1842
5ae2a7a8 1843int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1844{
1845 struct mlx4_cmd_mailbox *mailbox;
1846 u32 *inbox;
1847 int err;
1848 u32 flags;
5ae2a7a8 1849 u16 field;
225c7b1f 1850
5ae2a7a8 1851 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1852#define INIT_PORT_IN_SIZE 256
1853#define INIT_PORT_FLAGS_OFFSET 0x00
1854#define INIT_PORT_FLAG_SIG (1 << 18)
1855#define INIT_PORT_FLAG_NG (1 << 17)
1856#define INIT_PORT_FLAG_G0 (1 << 16)
1857#define INIT_PORT_VL_SHIFT 4
1858#define INIT_PORT_PORT_WIDTH_SHIFT 8
1859#define INIT_PORT_MTU_OFFSET 0x04
1860#define INIT_PORT_MAX_GID_OFFSET 0x06
1861#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1862#define INIT_PORT_GUID0_OFFSET 0x10
1863#define INIT_PORT_NODE_GUID_OFFSET 0x18
1864#define INIT_PORT_SI_GUID_OFFSET 0x20
1865
5ae2a7a8
RD		 1866 mailbox = mlx4_alloc_cmd_mailbox(dev);
1867 if (IS_ERR(mailbox))
1868 return PTR_ERR(mailbox);
1869 inbox = mailbox->buf;
225c7b1f 1870
5ae2a7a8
RD		 1871 flags = 0;
1872 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1873 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1874 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1875
b79acb49 1876 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1877 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1878 field = dev->caps.gid_table_len[port];
1879 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1880 field = dev->caps.pkey_table_len[port];
1881 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1882
5ae2a7a8 1883 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1884 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1885
5ae2a7a8
RD		 1886 mlx4_free_cmd_mailbox(dev, mailbox);
1887 } else
1888 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1889 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1890
1891 return err;
1892}
1893EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1894
5cc914f1
MA		 1895int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1896 struct mlx4_vhcr *vhcr,
1897 struct mlx4_cmd_mailbox *inbox,
1898 struct mlx4_cmd_mailbox *outbox,
1899 struct mlx4_cmd_info *cmd)
1900{
1901 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1902 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1903 int err;
1904
449fc488
MB		 1905 if (port < 0)
1906 return -EINVAL;
1907
5cc914f1
MA		 1908 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1909 (1 << port)))
1910 return 0;
1911
980e9001
JM		 1912 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1913 if (priv->mfunc.master.init_port_ref[port] == 1) {
1914 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1915 1000, MLX4_CMD_NATIVE);
1916 if (err)
1917 return err;
1918 }
1919 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1920 } else {
1921 /* infiniband port */
1922 if (slave == mlx4_master_func_num(dev)) {
1923 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1924 priv->mfunc.master.qp0_state[port].port_active) {
1925 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1926 1000, MLX4_CMD_NATIVE);
1927 if (err)
1928 return err;
1929 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1930 priv->mfunc.master.qp0_state[port].port_active = 0;
1931 }
1932 } else
1933 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1934 }
5cc914f1
MA		 1935 --priv->mfunc.master.init_port_ref[port];
1936 return 0;
1937}
1938
225c7b1f
RD		 1939int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1940{
f9baff50
JM		 1941 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1942 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1943}
1944EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1945
1946int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1947{
f9baff50
JM		 1948 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1949 MLX4_CMD_NATIVE);
225c7b1f
RD		 1950}
1951
d18f141a
OG		 1952struct mlx4_config_dev {
1953 __be32 update_flags;
d475c95b 1954 __be32 rsvd1[3];
d18f141a
OG		 1955 __be16 vxlan_udp_dport;
1956 __be16 rsvd2;
d475c95b
MB		 1957 __be32 rsvd3[27];
1958 __be16 rsvd4;
1959 u8 rsvd5;
1960 u8 rx_checksum_val;
d18f141a
OG		 1961};
1962
1963#define MLX4_VXLAN_UDP_DPORT (1 << 0)
1964
d475c95b 1965static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
d18f141a
OG		 1966{
1967 int err;
1968 struct mlx4_cmd_mailbox *mailbox;
1969
1970 mailbox = mlx4_alloc_cmd_mailbox(dev);
1971 if (IS_ERR(mailbox))
1972 return PTR_ERR(mailbox);
1973
1974 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
1975
1976 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
1977 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1978
1979 mlx4_free_cmd_mailbox(dev, mailbox);
1980 return err;
1981}
1982
d475c95b
MB		 1983static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
1984{
1985 int err;
1986 struct mlx4_cmd_mailbox *mailbox;
1987
1988 mailbox = mlx4_alloc_cmd_mailbox(dev);
1989 if (IS_ERR(mailbox))
1990 return PTR_ERR(mailbox);
1991
1992 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV,
1993 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1994
1995 if (!err)
1996 memcpy(config_dev, mailbox->buf, sizeof(*config_dev));
1997
1998 mlx4_free_cmd_mailbox(dev, mailbox);
1999 return err;
2000}
2001
2002/* Conversion between the HW values and the actual functionality.
2003 * The value represented by the array index,
2004 * and the functionality determined by the flags.
2005 */
2006static const u8 config_dev_csum_flags[] = {
2007 [0] = 0,
2008 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP,
2009 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP |
2010 MLX4_RX_CSUM_MODE_L4,
2011 [3] = MLX4_RX_CSUM_MODE_L4 |
2012 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP |
2013 MLX4_RX_CSUM_MODE_MULTI_VLAN
2014};
2015
2016int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
2017 struct mlx4_config_dev_params *params)
2018{
2019 struct mlx4_config_dev config_dev;
2020 int err;
2021 u8 csum_mask;
2022
2023#define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2024#define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2025#define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2026
2027 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2028 return -ENOTSUPP;
2029
2030 err = mlx4_CONFIG_DEV_get(dev, &config_dev);
2031 if (err)
2032 return err;
2033
2034 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) &
2035 CONFIG_DEV_RX_CSUM_MODE_MASK;
2036
2037 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2038 return -EINVAL;
2039 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask];
2040
2041 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) &
2042 CONFIG_DEV_RX_CSUM_MODE_MASK;
2043
2044 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2045 return -EINVAL;
2046 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask];
2047
2048 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport);
2049
2050 return 0;
2051}
2052EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval);
2053
d18f141a
OG		 2054int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
2055{
2056 struct mlx4_config_dev config_dev;
2057
2058 memset(&config_dev, 0, sizeof(config_dev));
2059 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
2060 config_dev.vxlan_udp_dport = udp_port;
2061
d475c95b 2062 return mlx4_CONFIG_DEV_set(dev, &config_dev);
d18f141a
OG		 2063}
2064EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
2065
2066
225c7b1f
RD		 2067int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
2068{
2069 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
2070 MLX4_CMD_SET_ICM_SIZE,
f9baff50 2071 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 2072 if (ret)
2073 return ret;
2074
2075 /*
2076 * Round up number of system pages needed in case
2077 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2078 */
2079 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
2080 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
2081
2082 return 0;
2083}
2084
2085int mlx4_NOP(struct mlx4_dev *dev)
2086{
2087 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 2088 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 2089}
14c07b13 2090
8e1a28e8
HHZ		 2091int mlx4_get_phys_port_id(struct mlx4_dev *dev)
2092{
2093 u8 port;
2094 u32 *outbox;
2095 struct mlx4_cmd_mailbox *mailbox;
2096 u32 in_mod;
2097 u32 guid_hi, guid_lo;
2098 int err, ret = 0;
2099#define MOD_STAT_CFG_PORT_OFFSET 8
2100#define MOD_STAT_CFG_GUID_H 0X14
2101#define MOD_STAT_CFG_GUID_L 0X1c
2102
2103 mailbox = mlx4_alloc_cmd_mailbox(dev);
2104 if (IS_ERR(mailbox))
2105 return PTR_ERR(mailbox);
2106 outbox = mailbox->buf;
2107
2108 for (port = 1; port <= dev->caps.num_ports; port++) {
2109 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
2110 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
2111 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2112 MLX4_CMD_NATIVE);
2113 if (err) {
2114 mlx4_err(dev, "Fail to get port %d uplink guid\n",
2115 port);
2116 ret = err;
2117 } else {
2118 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2119 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2120 dev->caps.phys_port_id[port] = (u64)guid_lo |
2121 (u64)guid_hi << 32;
2122 }
2123 }
2124 mlx4_free_cmd_mailbox(dev, mailbox);
2125 return ret;
2126}
2127
14c07b13
YP		 2128#define MLX4_WOL_SETUP_MODE (5 << 28)
2129int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
2130{
2131 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2132
2133 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 2134 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2135 MLX4_CMD_NATIVE);
14c07b13
YP		 2136}
2137EXPORT_SYMBOL_GPL(mlx4_wol_read);
2138
2139int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
2140{
2141 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2142
2143 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 2144 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 2145}
2146EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 2147
2148enum {
2149 ADD_TO_MCG = 0x26,
2150};
2151
2152
2153void mlx4_opreq_action(struct work_struct *work)
2154{
2155 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
2156 opreq_task);
2157 struct mlx4_dev *dev = &priv->dev;
2158 int num_tasks = atomic_read(&priv->opreq_count);
2159 struct mlx4_cmd_mailbox *mailbox;
2160 struct mlx4_mgm *mgm;
2161 u32 *outbox;
2162 u32 modifier;
2163 u16 token;
fe6f700d
YP		 2164 u16 type;
2165 int err;
2166 u32 num_qps;
2167 struct mlx4_qp qp;
2168 int i;
2169 u8 rem_mcg;
2170 u8 prot;
2171
2172#define GET_OP_REQ_MODIFIER_OFFSET 0x08
2173#define GET_OP_REQ_TOKEN_OFFSET 0x14
2174#define GET_OP_REQ_TYPE_OFFSET 0x1a
2175#define GET_OP_REQ_DATA_OFFSET 0x20
2176
2177 mailbox = mlx4_alloc_cmd_mailbox(dev);
2178 if (IS_ERR(mailbox)) {
2179 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2180 return;
2181 }
2182 outbox = mailbox->buf;
2183
2184 while (num_tasks) {
2185 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2186 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2187 MLX4_CMD_NATIVE);
2188 if (err) {
6d3be300 2189 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 2190 err);
2191 return;
2192 }
2193 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2194 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2195 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 2196 type &= 0xfff;
2197
2198 switch (type) {
2199 case ADD_TO_MCG:
2200 if (dev->caps.steering_mode ==
2201 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2202 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2203 err = EPERM;
2204 break;
2205 }
2206 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2207 GET_OP_REQ_DATA_OFFSET);
2208 num_qps = be32_to_cpu(mgm->members_count) &
2209 MGM_QPN_MASK;
2210 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2211 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2212
2213 for (i = 0; i < num_qps; i++) {
2214 qp.qpn = be32_to_cpu(mgm->qp[i]);
2215 if (rem_mcg)
2216 err = mlx4_multicast_detach(dev, &qp,
2217 mgm->gid,
2218 prot, 0);
2219 else
2220 err = mlx4_multicast_attach(dev, &qp,
2221 mgm->gid,
2222 mgm->gid[5]
2223 , 0, prot,
2224 NULL);
2225 if (err)
2226 break;
2227 }
2228 break;
2229 default:
2230 mlx4_warn(dev, "Bad type for required operation\n");
2231 err = EINVAL;
2232 break;
2233 }
28d222bb
EP		 2234 err = mlx4_cmd(dev, 0, ((u32) err |
2235 (__force u32)cpu_to_be32(token) << 16),
fe6f700d
YP		 2236 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2237 MLX4_CMD_NATIVE);
2238 if (err) {
2239 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2240 err);
2241 goto out;
2242 }
2243 memset(outbox, 0, 0xffc);
2244 num_tasks = atomic_dec_return(&priv->opreq_count);
2245 }
2246
2247out:
2248 mlx4_free_cmd_mailbox(dev, mailbox);
2249}
114840c3
JM		 2250
2251static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2252 struct mlx4_cmd_mailbox *mailbox)
2253{
2254#define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2255#define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2256#define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2257#define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2258
2259 u32 set_attr_mask, getresp_attr_mask;
2260 u32 trap_attr_mask, traprepress_attr_mask;
2261
2262 MLX4_GET(set_attr_mask, mailbox->buf,
2263 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2264 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2265 set_attr_mask);
2266
2267 MLX4_GET(getresp_attr_mask, mailbox->buf,
2268 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2269 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2270 getresp_attr_mask);
2271
2272 MLX4_GET(trap_attr_mask, mailbox->buf,
2273 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2274 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2275 trap_attr_mask);
2276
2277 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2278 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2279 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2280 traprepress_attr_mask);
2281
2282 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2283 traprepress_attr_mask)
2284 return 1;
2285
2286 return 0;
2287}
2288
2289int mlx4_config_mad_demux(struct mlx4_dev *dev)
2290{
2291 struct mlx4_cmd_mailbox *mailbox;
2292 int secure_host_active;
2293 int err;
2294
2295 /* Check if mad_demux is supported */
2296 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2297 return 0;
2298
2299 mailbox = mlx4_alloc_cmd_mailbox(dev);
2300 if (IS_ERR(mailbox)) {
2301 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2302 return -ENOMEM;
2303 }
2304
2305 /* Query mad_demux to find out which MADs are handled by internal sma */
2306 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2307 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2308 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2309 if (err) {
2310 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2311 err);
2312 goto out;
2313 }
2314
2315 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2316
2317 /* Config mad_demux to handle all MADs returned by the query above */
2318 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2319 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2320 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2321 if (err) {
2322 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2323 goto out;
2324 }
2325
2326 if (secure_host_active)
2327 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2328out:
2329 mlx4_free_cmd_mailbox(dev, mailbox);
2330 return err;
2331}
adbc7ac5
SM		 2332
2333/* Access Reg commands */
2334enum mlx4_access_reg_masks {
2335 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2336 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2337 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2338};
2339
2340struct mlx4_access_reg {
2341 __be16 constant1;
2342 u8 status;
2343 u8 resrvd1;
2344 __be16 reg_id;
2345 u8 method;
2346 u8 constant2;
2347 __be32 resrvd2[2];
2348 __be16 len_const;
2349 __be16 resrvd3;
2350#define MLX4_ACCESS_REG_HEADER_SIZE (20)
2351 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2352} __attribute__((__packed__));
2353
2354/**
2355 * mlx4_ACCESS_REG - Generic access reg command.
2356 * @dev: mlx4_dev.
2357 * @reg_id: register ID to access.
2358 * @method: Access method Read/Write.
2359 * @reg_len: register length to Read/Write in bytes.
2360 * @reg_data: reg_data pointer to Read/Write From/To.
2361 *
2362 * Access ConnectX registers FW command.
2363 * Returns 0 on success and copies outbox mlx4_access_reg data
2364 * field into reg_data or a negative error code.
2365 */
2366static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2367 enum mlx4_access_reg_method method,
2368 u16 reg_len, void *reg_data)
2369{
2370 struct mlx4_cmd_mailbox *inbox, *outbox;
2371 struct mlx4_access_reg *inbuf, *outbuf;
2372 int err;
2373
2374 inbox = mlx4_alloc_cmd_mailbox(dev);
2375 if (IS_ERR(inbox))
2376 return PTR_ERR(inbox);
2377
2378 outbox = mlx4_alloc_cmd_mailbox(dev);
2379 if (IS_ERR(outbox)) {
2380 mlx4_free_cmd_mailbox(dev, inbox);
2381 return PTR_ERR(outbox);
2382 }
2383
2384 inbuf = inbox->buf;
2385 outbuf = outbox->buf;
2386
2387 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2388 inbuf->constant2 = 0x1;
2389 inbuf->reg_id = cpu_to_be16(reg_id);
2390 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2391
2392 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2393 inbuf->len_const =
2394 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2395 ((0x3) << 12));
2396
2397 memcpy(inbuf->reg_data, reg_data, reg_len);
2398 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2399 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
6e806699 2400 MLX4_CMD_WRAPPED);
adbc7ac5
SM		 2401 if (err)
2402 goto out;
2403
2404 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2405 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2406 mlx4_err(dev,
2407 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2408 reg_id, err);
2409 goto out;
2410 }
2411
2412 memcpy(reg_data, outbuf->reg_data, reg_len);
2413out:
2414 mlx4_free_cmd_mailbox(dev, inbox);
2415 mlx4_free_cmd_mailbox(dev, outbox);
2416 return err;
2417}
2418
2419/* ConnectX registers IDs */
2420enum mlx4_reg_id {
2421 MLX4_REG_ID_PTYS = 0x5004,
2422};
2423
2424/**
2425 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2426 * register
2427 * @dev: mlx4_dev.
2428 * @method: Access method Read/Write.
2429 * @ptys_reg: PTYS register data pointer.
2430 *
2431 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2432 * configuration
2433 * Returns 0 on success or a negative error code.
2434 */
2435int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2436 enum mlx4_access_reg_method method,
2437 struct mlx4_ptys_reg *ptys_reg)
2438{
2439 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2440 method, sizeof(*ptys_reg), ptys_reg);
2441}
2442EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
6e806699
SM		 2443
2444int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2445 struct mlx4_vhcr *vhcr,
2446 struct mlx4_cmd_mailbox *inbox,
2447 struct mlx4_cmd_mailbox *outbox,
2448 struct mlx4_cmd_info *cmd)
2449{
2450 struct mlx4_access_reg *inbuf = inbox->buf;
2451 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2452 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2453
2454 if (slave != mlx4_master_func_num(dev) &&
2455 method == MLX4_ACCESS_REG_WRITE)
2456 return -EPERM;
2457
2458 if (reg_id == MLX4_REG_ID_PTYS) {
2459 struct mlx4_ptys_reg *ptys_reg =
2460 (struct mlx4_ptys_reg *)inbuf->reg_data;
2461
2462 ptys_reg->local_port =
2463 mlx4_slave_convert_port(dev, slave,
2464 ptys_reg->local_port);
2465 }
2466
2467 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2468 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2469 MLX4_CMD_NATIVE);
2470}
Linux 6.x block layer and io_uring tree(s)