drm/nouveau/kms/gv100-: attach pixel blend mode property to planes

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/dispnv50/atom.h b/drivers/gpu/drm/nouveau/dispnv50/atom.h
index 973074403f3c2dcb361bd11d609245d037201d3b..43df86c38f58bcf061491cb718f66e215db40a7c 100644 (file)
--- a/drivers/gpu/drm/nouveau/dispnv50/atom.h
+++ b/drivers/gpu/drm/nouveau/dispnv50/atom.h
@@ -224,6 +224,8 @@ struct nv50_wndw_atom {
        struct {
                u8 depth;
                u8 k1;
+               u8 src_color:4;
+               u8 dst_color:4;
        } blend;
 
        union nv50_wndw_atom_mask {

diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
index 76c69c6eca7722d4b979f44bdc6f9c28c4d79fd2..2db029371c9192c5b3740e93bb370df657e05c56 100644 (file)
--- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c
@@ -289,6 +289,21 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset,
        if (wndw->func->blend_set) {
                asyw->blend.depth = 255 - asyw->state.normalized_zpos;
                asyw->blend.k1 = asyw->state.alpha >> 8;
+               switch (asyw->state.pixel_blend_mode) {
+               case DRM_MODE_BLEND_PREMULTI:
+                       asyw->blend.src_color = 2; /* K1 */
+                       asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */
+                       break;
+               case DRM_MODE_BLEND_COVERAGE:
+                       asyw->blend.src_color = 5; /* K1_TIMES_SRC */
+                       asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */
+                       break;
+               case DRM_MODE_BLEND_PIXEL_NONE:
+               default:
+                       asyw->blend.src_color = 2; /* K1 */
+                       asyw->blend.dst_color = 4; /* NEG_K1 */
+                       break;
+               }
                if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend)))
                        asyw->set.blend = true;
        }
@@ -661,6 +676,13 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,
                ret = drm_plane_create_alpha_property(&wndw->plane);
                if (ret)
                        return ret;
+
+               ret = drm_plane_create_blend_mode_property(&wndw->plane,
+                               BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+                               BIT(DRM_MODE_BLEND_PREMULTI) |
+                               BIT(DRM_MODE_BLEND_COVERAGE));
+               if (ret)
+                       return ret;
        } else {
                ret = drm_plane_create_zpos_immutable_property(&wndw->plane,
                                nv50_wndw_zpos_default(&wndw->plane));

diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
index 3c6d64d1b70820ca608b9c95813d4f76755b23d0..0f9402162bde92eab82c0b86e0b554606dddd2e3 100644 (file)
--- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c
@@ -89,7 +89,10 @@ wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
                evo_mthd(push, 0x02ec, 7);
                evo_data(push, asyw->blend.depth << 4);
                evo_data(push, asyw->blend.k1);
-               evo_data(push, 0x00007722);
+               evo_data(push, asyw->blend.dst_color << 12 |
+                              asyw->blend.dst_color << 8 |
+                              asyw->blend.src_color << 4 |
+                              asyw->blend.src_color);
                evo_data(push, 0xffff0000);
                evo_data(push, 0xffff0000);
                evo_data(push, 0xffff0000);