[linux-2.6-block.git] / drivers / gpu / drm / nouveau / dispnv50 / atom.h

#ifndef __NV50_KMS_ATOM_H__
#define __NV50_KMS_ATOM_H__
#define nv50_atom(p) container_of((p), struct nv50_atom, state)
#include <drm/drm_atomic.h>

struct nv50_atom {
	struct drm_atomic_state state;

	struct list_head outp;
	bool lock_core;
	bool flush_disable;
};

#define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)

struct nv50_head_atom {
	struct drm_crtc_state state;

	struct {
		u32 mask;
		u32 olut;
	} wndw;

	struct {
		u16 iW;
		u16 iH;
		u16 oW;
		u16 oH;
	} view;

	struct nv50_head_mode {
		bool interlace;
		u32 clock;
		struct {
			u16 active;
			u16 synce;
			u16 blanke;
			u16 blanks;
		} h;
		struct {
			u32 active;
			u16 synce;
			u16 blanke;
			u16 blanks;
			u16 blank2s;
			u16 blank2e;
			u16 blankus;
		} v;
	} mode;

	struct {
		bool visible;
		u32 handle;
		u64 offset:40;
		u8 buffer:1;
		u8 mode:4;
		u16 size:11;
		u8 range:2;
		u8 output_mode:2;
		void (*load)(struct drm_color_lut *, int size, void __iomem *);
	} olut;

	struct {
		bool visible;
		u32 handle;
		u64 offset:40;
		u8  format;
		u8  kind:7;
		u8  layout:1;
		u8  blockh:4;
		u16 blocks:12;
		u32 pitch:20;
		u16 x;
		u16 y;
		u16 w;
		u16 h;
	} core;

	struct {
		bool visible;
		u32 handle;
		u64 offset:40;
		u8  layout:2;
		u8  format:8;
	} curs;

	struct {
		u8  depth;
		u8  cpp;
		u16 x;
		u16 y;
		u16 w;
		u16 h;
	} base;

	struct {
		u8 cpp;
	} ovly;

	struct {
		bool enable:1;
		u8 bits:2;
		u8 mode:4;
	} dither;

	struct {
		struct {
			u16 cos:12;
			u16 sin:12;
		} sat;
	} procamp;

	struct {
		u8 nhsync:1;
		u8 nvsync:1;
		u8 depth:4;
	} or;

	/* Currently only used for MST */
	struct {
		int pbn;
		u8 tu:6;
	} dp;

	union nv50_head_atom_mask {
		struct {
			bool olut:1;
			bool core:1;
			bool curs:1;
			bool view:1;
			bool mode:1;
			bool base:1;
			bool ovly:1;
			bool dither:1;
			bool procamp:1;
			bool or:1;
		};
		u16 mask;
	} set, clr;
};

static inline struct nv50_head_atom *
nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
{
	struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
	if (IS_ERR(statec))
		return (void *)statec;
	return nv50_head_atom(statec);
}

#define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)

struct nv50_wndw_atom {
	struct drm_plane_state state;

	struct drm_property_blob *ilut;
	bool visible;

	struct {
		u32  handle;
		u16  offset:12;
		bool awaken:1;
	} ntfy;

	struct {
		u32 handle;
		u16 offset:12;
		u32 acquire;
		u32 release;
	} sema;

	struct {
		u32 handle;
		struct {
			u64 offset:40;
			u8  buffer:1;
			u8  enable:2;
			u8  mode:4;
			u16 size:11;
			u8  range:2;
			u8  output_mode:2;
			void (*load)(struct drm_color_lut *, int size,
				     void __iomem *);
		} i;
	} xlut;

	struct {
		u32 matrix[12];
		bool valid;
	} csc;

	struct {
		u8  mode:2;
		u8  interval:4;

		u8  colorspace:2;
		u8  format;
		u8  kind:7;
		u8  layout:1;
		u8  blockh:4;
		u16 blocks[3];
		u32 pitch[3];
		u16 w;
		u16 h;

		u32 handle[6];
		u64 offset[6];
	} image;

	struct {
		u16 sx;
		u16 sy;
		u16 sw;
		u16 sh;
		u16 dw;
		u16 dh;
	} scale;

	struct {
		u16 x;
		u16 y;
	} point;

	struct {
		u8 depth;
		u8 k1;
		u8 src_color:4;
		u8 dst_color:4;
	} blend;

	union nv50_wndw_atom_mask {
		struct {
			bool ntfy:1;
			bool sema:1;
			bool xlut:1;
			bool csc:1;
			bool image:1;
			bool scale:1;
			bool point:1;
			bool blend:1;
		};
		u8 mask;
	} set, clr;
};
#endif
Commit	Line	Data
1590700d BS	1	#ifndef __NV50_KMS_ATOM_H__
	2	#define __NV50_KMS_ATOM_H__
	3	#define nv50_atom(p) container_of((p), struct nv50_atom, state)
	4	#include <drm/drm_atomic.h>
	5
	6	struct nv50_atom {
	7	struct drm_atomic_state state;
	8
	9	struct list_head outp;
	10	bool lock_core;
	11	bool flush_disable;
	12	};
	13
	14	#define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
	15
	16	struct nv50_head_atom {
	17	struct drm_crtc_state state;
	18
119608a7 BS	19	struct {
	20	u32 mask;
	21	u32 olut;
	22	} wndw;
	23
1590700d BS	24	struct {
	25	u16 iW;
	26	u16 iH;
	27	u16 oW;
	28	u16 oH;
	29	} view;
	30
	31	struct nv50_head_mode {
	32	bool interlace;
	33	u32 clock;
	34	struct {
	35	u16 active;
	36	u16 synce;
	37	u16 blanke;
	38	u16 blanks;
	39	} h;
	40	struct {
	41	u32 active;
	42	u16 synce;
	43	u16 blanke;
	44	u16 blanks;
	45	u16 blank2s;
	46	u16 blank2e;
	47	u16 blankus;
	48	} v;
	49	} mode;
	50
	51	struct {
	52	bool visible;
	53	u32 handle;
	54	u64 offset:40;
119608a7 BS	55	u8 buffer:1;
119608a7 BS	56	u8 mode:4;
563737c5	57	u16 size:11;
facaed62 BS	58	u8 range:2;
facaed62 BS	59	u8 output_mode:2;
cb55cd0c	60	void (load)(struct drm_color_lut , int size, void __iomem *);
119608a7	61	} olut;
1590700d BS	62
	63	struct {
	64	bool visible;
	65	u32 handle;
	66	u64 offset:40;
	67	u8 format;
	68	u8 kind:7;
	69	u8 layout:1;
b05d8738 BS	70	u8 blockh:4;
b05d8738 BS	71	u16 blocks:12;
1590700d BS	72	u32 pitch:20;
	73	u16 x;
	74	u16 y;
	75	u16 w;
	76	u16 h;
	77	} core;
	78
	79	struct {
	80	bool visible;
	81	u32 handle;
	82	u64 offset:40;
01d380ab	83	u8 layout:2;
facaed62	84	u8 format:8;
1590700d BS	85	} curs;
	86
	87	struct {
	88	u8 depth;
	89	u8 cpp;
	90	u16 x;
	91	u16 y;
	92	u16 w;
	93	u16 h;
	94	} base;
	95
	96	struct {
	97	u8 cpp;
	98	} ovly;
	99
	100	struct {
	101	bool enable:1;
	102	u8 bits:2;
	103	u8 mode:4;
	104	} dither;
	105
	106	struct {
	107	struct {
	108	u16 cos:12;
	109	u16 sin:12;
	110	} sat;
	111	} procamp;
	112
	113	struct {
	114	u8 nhsync:1;
	115	u8 nvsync:1;
	116	u8 depth:4;
	117	} or;
	118
88ec89ad LP	119	/* Currently only used for MST */
	120	struct {
	121	int pbn;
	122	u8 tu:6;
	123	} dp;
	124
f88bc9d3	125	union nv50_head_atom_mask {
1590700d	126	struct {
119608a7	127	bool olut:1;
1590700d BS	128	bool core:1;
	129	bool curs:1;
	130	bool view:1;
	131	bool mode:1;
	132	bool base:1;
	133	bool ovly:1;
	134	bool dither:1;
	135	bool procamp:1;
	136	bool or:1;
	137	};
	138	u16 mask;
f88bc9d3	139	} set, clr;
1590700d BS	140	};
	141
	142	static inline struct nv50_head_atom *
	143	nv50_head_atom_get(struct drm_atomic_state state, struct drm_crtc crtc)
	144	{
	145	struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
	146	if (IS_ERR(statec))
	147	return (void *)statec;
	148	return nv50_head_atom(statec);
	149	}
	150
	151	#define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
	152
	153	struct nv50_wndw_atom {
	154	struct drm_plane_state state;
1590700d	155
119608a7	156	struct drm_property_blob *ilut;
859b456b BS	157	bool visible;
859b456b BS	158
1590700d BS	159	struct {
	160	u32 handle;
	161	u16 offset:12;
	162	bool awaken:1;
	163	} ntfy;
	164
	165	struct {
	166	u32 handle;
	167	u16 offset:12;
	168	u32 acquire;
	169	u32 release;
	170	} sema;
	171
	172	struct {
119608a7 BS	173	u32 handle;
	174	struct {
	175	u64 offset:40;
	176	u8 buffer:1;
	177	u8 enable:2;
	178	u8 mode:4;
563737c5	179	u16 size:11;
facaed62 BS	180	u8 range:2;
facaed62 BS	181	u8 output_mode:2;
cb55cd0c BS	182	void (load)(struct drm_color_lut , int size,
cb55cd0c BS	183	void __iomem *);
119608a7 BS	184	} i;
119608a7 BS	185	} xlut;
1590700d	186
88b70352 IM	187	struct {
	188	u32 matrix[12];
	189	bool valid;
	190	} csc;
	191
1590700d BS	192	struct {
	193	u8 mode:2;
	194	u8 interval:4;
	195
2ce7f386	196	u8 colorspace:2;
1590700d BS	197	u8 format;
	198	u8 kind:7;
	199	u8 layout:1;
b05d8738 BS	200	u8 blockh:4;
b05d8738 BS	201	u16 blocks[3];
261fcfa9	202	u32 pitch[3];
1590700d BS	203	u16 w;
	204	u16 h;
	205
261fcfa9 BS	206	u32 handle[6];
261fcfa9 BS	207	u64 offset[6];
1590700d BS	208	} image;
1590700d BS	209
2ce7f386 BS	210	struct {
	211	u16 sx;
	212	u16 sy;
	213	u16 sw;
	214	u16 sh;
	215	u16 dw;
	216	u16 dh;
	217	} scale;
	218
1590700d BS	219	struct {
	220	u16 x;
	221	u16 y;
	222	} point;
	223
9a99e904 BS	224	struct {
9a99e904 BS	225	u8 depth;
a0a76244	226	u8 k1;
edc641b2 BS	227	u8 src_color:4;
edc641b2 BS	228	u8 dst_color:4;
9a99e904 BS	229	} blend;
9a99e904 BS	230
f88bc9d3	231	union nv50_wndw_atom_mask {
1590700d BS	232	struct {
	233	bool ntfy:1;
	234	bool sema:1;
119608a7	235	bool xlut:1;
88b70352	236	bool csc:1;
1590700d	237	bool image:1;
2ce7f386	238	bool scale:1;
1590700d	239	bool point:1;
9a99e904	240	bool blend:1;
1590700d BS	241	};
1590700d BS	242	u8 mask;
f88bc9d3	243	} set, clr;
1590700d BS	244	};
1590700d BS	245	#endif