[linux-2.6-block.git] / drivers / staging / iio / adc / ad7793.c

/*
 * AD7785/AD7792/AD7793/AD7794/AD7795 SPI ADC driver
 *
 * Copyright 2011-2012 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/interrupt.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/sched.h>
#include <linux/delay.h>
#include <linux/module.h>

#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/iio/buffer.h>
#include <linux/iio/trigger.h>
#include <linux/iio/trigger_consumer.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/iio/adc/ad_sigma_delta.h>

#include "ad7793.h"

/* NOTE:
 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
 * In order to avoid contentions on the SPI bus, it's therefore necessary
 * to use spi bus locking.
 *
 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
 */

struct ad7793_chip_info {
	const struct iio_chan_spec *channels;
	unsigned int num_channels;
};

struct ad7793_state {
	const struct ad7793_chip_info	*chip_info;
	struct regulator		*reg;
	u16				int_vref_mv;
	u16				mode;
	u16				conf;
	u32				scale_avail[8][2];

	struct ad_sigma_delta		sd;

};

enum ad7793_supported_device_ids {
	ID_AD7785,
	ID_AD7792,
	ID_AD7793,
	ID_AD7794,
	ID_AD7795,
};

static struct ad7793_state *ad_sigma_delta_to_ad7793(struct ad_sigma_delta *sd)
{
	return container_of(sd, struct ad7793_state, sd);
}

static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
{
	struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);

	st->conf &= ~AD7793_CONF_CHAN_MASK;
	st->conf |= AD7793_CONF_CHAN(channel);

	return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf);
}

static int ad7793_set_mode(struct ad_sigma_delta *sd,
			   enum ad_sigma_delta_mode mode)
{
	struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);

	st->mode &= ~AD7793_MODE_SEL_MASK;
	st->mode |= AD7793_MODE_SEL(mode);

	return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode);
}

static const struct ad_sigma_delta_info ad7793_sigma_delta_info = {
	.set_channel = ad7793_set_channel,
	.set_mode = ad7793_set_mode,
	.has_registers = true,
	.addr_shift = 3,
	.read_mask = BIT(6),
};

static const struct ad_sd_calib_data ad7793_calib_arr[6] = {
	{AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
	{AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
	{AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
	{AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
	{AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
	{AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
};

static int ad7793_calibrate_all(struct ad7793_state *st)
{
	return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr,
				   ARRAY_SIZE(ad7793_calib_arr));
}

static int ad7793_setup(struct iio_dev *indio_dev,
	const struct ad7793_platform_data *pdata)
{
	struct ad7793_state *st = iio_priv(indio_dev);
	int i, ret = -1;
	unsigned long long scale_uv;
	u32 id;

	/* reset the serial interface */
	ret = spi_write(st->sd.spi, (u8 *)&ret, sizeof(ret));
	if (ret < 0)
		goto out;
	msleep(1); /* Wait for at least 500us */

	/* write/read test for device presence */
	ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id);
	if (ret)
		goto out;

	id &= AD7793_ID_MASK;

	if (!((id == AD7792_ID) || (id == AD7793_ID) || (id == AD7795_ID))) {
		dev_err(&st->sd.spi->dev, "device ID query failed\n");
		goto out;
	}

	st->mode = pdata->mode;
	st->conf = pdata->conf;

	ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE);
	if (ret)
		goto out;

	ret = ad7793_set_channel(&st->sd, 0);
	if (ret)
		goto out;

	ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO,
			       sizeof(pdata->io), pdata->io);
	if (ret)
		goto out;

	ret = ad7793_calibrate_all(st);
	if (ret)
		goto out;

	/* Populate available ADC input ranges */
	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
		scale_uv = ((u64)st->int_vref_mv * 100000000)
			>> (st->chip_info->channels[0].scan_type.realbits -
			(!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
		scale_uv >>= i;

		st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
		st->scale_avail[i][0] = scale_uv;
	}

	return 0;
out:
	dev_err(&st->sd.spi->dev, "setup failed\n");
	return ret;
}

static const u16 sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 33, 19,
					  17, 16, 12, 10, 8, 6, 4};

static ssize_t ad7793_read_frequency(struct device *dev,
		struct device_attribute *attr,
		char *buf)
{
	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
	struct ad7793_state *st = iio_priv(indio_dev);

	return sprintf(buf, "%d\n",
		       sample_freq_avail[AD7793_MODE_RATE(st->mode)]);
}

static ssize_t ad7793_write_frequency(struct device *dev,
		struct device_attribute *attr,
		const char *buf,
		size_t len)
{
	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
	struct ad7793_state *st = iio_priv(indio_dev);
	long lval;
	int i, ret;

	mutex_lock(&indio_dev->mlock);
	if (iio_buffer_enabled(indio_dev)) {
		mutex_unlock(&indio_dev->mlock);
		return -EBUSY;
	}
	mutex_unlock(&indio_dev->mlock);

	ret = strict_strtol(buf, 10, &lval);
	if (ret)
		return ret;

	ret = -EINVAL;

	for (i = 0; i < ARRAY_SIZE(sample_freq_avail); i++)
		if (lval == sample_freq_avail[i]) {
			mutex_lock(&indio_dev->mlock);
			st->mode &= ~AD7793_MODE_RATE(-1);
			st->mode |= AD7793_MODE_RATE(i);
			ad_sd_write_reg(&st->sd, AD7793_REG_MODE,
					 sizeof(st->mode), st->mode);
			mutex_unlock(&indio_dev->mlock);
			ret = 0;
		}

	return ret ? ret : len;
}

static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
		ad7793_read_frequency,
		ad7793_write_frequency);

static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
	"470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");

static ssize_t ad7793_show_scale_available(struct device *dev,
			struct device_attribute *attr, char *buf)
{
	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
	struct ad7793_state *st = iio_priv(indio_dev);
	int i, len = 0;

	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
		len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
			       st->scale_avail[i][1]);

	len += sprintf(buf + len, "\n");

	return len;
}

static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available,
		in_voltage-voltage_scale_available, S_IRUGO,
		ad7793_show_scale_available, NULL, 0);

static struct attribute *ad7793_attributes[] = {
	&iio_dev_attr_sampling_frequency.dev_attr.attr,
	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
	&iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
	NULL
};

static const struct attribute_group ad7793_attribute_group = {
	.attrs = ad7793_attributes,
};

static int ad7793_read_raw(struct iio_dev *indio_dev,
			   struct iio_chan_spec const *chan,
			   int *val,
			   int *val2,
			   long m)
{
	struct ad7793_state *st = iio_priv(indio_dev);
	int ret;
	unsigned long long scale_uv;
	bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);

	switch (m) {
	case IIO_CHAN_INFO_RAW:
		ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
		if (ret < 0)
			return ret;

		return IIO_VAL_INT;

	case IIO_CHAN_INFO_SCALE:
		switch (chan->type) {
		case IIO_VOLTAGE:
			if (chan->differential) {
				*val = st->
					scale_avail[(st->conf >> 8) & 0x7][0];
				*val2 = st->
					scale_avail[(st->conf >> 8) & 0x7][1];
				return IIO_VAL_INT_PLUS_NANO;
			} else {
				/* 1170mV / 2^23 * 6 */
				scale_uv = (1170ULL * 1000000000ULL * 6ULL);
			}
			break;
		case IIO_TEMP:
				/* 1170mV / 0.81 mV/C / 2^23 */
				scale_uv = 1444444444444444ULL;
			break;
		default:
			return -EINVAL;
		}

		scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1));
		*val = 0;
		*val2 = scale_uv;
		return IIO_VAL_INT_PLUS_NANO;
	case IIO_CHAN_INFO_OFFSET:
		if (!unipolar)
			*val = -(1 << (chan->scan_type.realbits - 1));
		else
			*val = 0;

		/* Kelvin to Celsius */
		if (chan->type == IIO_TEMP) {
			unsigned long long offset;
			unsigned int shift;

			shift = chan->scan_type.realbits - (unipolar ? 0 : 1);
			offset = 273ULL << shift;
			do_div(offset, 1444);
			*val -= offset;
		}
		return IIO_VAL_INT;
	}
	return -EINVAL;
}

static int ad7793_write_raw(struct iio_dev *indio_dev,
			       struct iio_chan_spec const *chan,
			       int val,
			       int val2,
			       long mask)
{
	struct ad7793_state *st = iio_priv(indio_dev);
	int ret, i;
	unsigned int tmp;

	mutex_lock(&indio_dev->mlock);
	if (iio_buffer_enabled(indio_dev)) {
		mutex_unlock(&indio_dev->mlock);
		return -EBUSY;
	}

	switch (mask) {
	case IIO_CHAN_INFO_SCALE:
		ret = -EINVAL;
		for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
			if (val2 == st->scale_avail[i][1]) {
				ret = 0;
				tmp = st->conf;
				st->conf &= ~AD7793_CONF_GAIN(-1);
				st->conf |= AD7793_CONF_GAIN(i);

				if (tmp == st->conf)
					break;

				ad_sd_write_reg(&st->sd, AD7793_REG_CONF,
						sizeof(st->conf), st->conf);
				ad7793_calibrate_all(st);
				break;
			}
		break;
	default:
		ret = -EINVAL;
	}

	mutex_unlock(&indio_dev->mlock);
	return ret;
}

static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
			       struct iio_chan_spec const *chan,
			       long mask)
{
	return IIO_VAL_INT_PLUS_NANO;
}

static const struct iio_info ad7793_info = {
	.read_raw = &ad7793_read_raw,
	.write_raw = &ad7793_write_raw,
	.write_raw_get_fmt = &ad7793_write_raw_get_fmt,
	.attrs = &ad7793_attribute_group,
	.validate_trigger = ad_sd_validate_trigger,
	.driver_module = THIS_MODULE,
};

#define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \
const struct iio_chan_spec _name##_channels[] = { \
	AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \
	AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \
	AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \
	AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \
	AD_SD_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \
	AD_SD_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \
	IIO_CHAN_SOFT_TIMESTAMP(6), \
}

#define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \
const struct iio_chan_spec _name##_channels[] = { \
	AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
	AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
	AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
	AD_SD_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \
	AD_SD_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \
	AD_SD_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \
	AD_SD_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
	AD_SD_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \
	AD_SD_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
	IIO_CHAN_SOFT_TIMESTAMP(9), \
}

static DECLARE_AD7793_CHANNELS(ad7785, 20, 32, 4);
static DECLARE_AD7793_CHANNELS(ad7792, 16, 32, 0);
static DECLARE_AD7793_CHANNELS(ad7793, 24, 32, 0);
static DECLARE_AD7795_CHANNELS(ad7794, 16, 32);
static DECLARE_AD7795_CHANNELS(ad7795, 24, 32);

static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
	[ID_AD7785] = {
		.channels = ad7785_channels,
		.num_channels = ARRAY_SIZE(ad7785_channels),
	},
	[ID_AD7792] = {
		.channels = ad7792_channels,
		.num_channels = ARRAY_SIZE(ad7792_channels),
	},
	[ID_AD7793] = {
		.channels = ad7793_channels,
		.num_channels = ARRAY_SIZE(ad7793_channels),
	},
	[ID_AD7794] = {
		.channels = ad7794_channels,
		.num_channels = ARRAY_SIZE(ad7794_channels),
	},
	[ID_AD7795] = {
		.channels = ad7795_channels,
		.num_channels = ARRAY_SIZE(ad7795_channels),
	},
};

static int ad7793_probe(struct spi_device *spi)
{
	const struct ad7793_platform_data *pdata = spi->dev.platform_data;
	struct ad7793_state *st;
	struct iio_dev *indio_dev;
	int ret, voltage_uv = 0;

	if (!pdata) {
		dev_err(&spi->dev, "no platform data?\n");
		return -ENODEV;
	}

	if (!spi->irq) {
		dev_err(&spi->dev, "no IRQ?\n");
		return -ENODEV;
	}

	indio_dev = iio_device_alloc(sizeof(*st));
	if (indio_dev == NULL)
		return -ENOMEM;

	st = iio_priv(indio_dev);

	ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info);

	st->reg = regulator_get(&spi->dev, "vcc");
	if (!IS_ERR(st->reg)) {
		ret = regulator_enable(st->reg);
		if (ret)
			goto error_put_reg;

		voltage_uv = regulator_get_voltage(st->reg);
	}

	st->chip_info =
		&ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];

	if (pdata && pdata->vref_mv)
		st->int_vref_mv = pdata->vref_mv;
	else if (voltage_uv)
		st->int_vref_mv = voltage_uv / 1000;
	else
		st->int_vref_mv = 1170; /* Build-in ref */

	spi_set_drvdata(spi, indio_dev);

	indio_dev->dev.parent = &spi->dev;
	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->modes = INDIO_DIRECT_MODE;
	indio_dev->channels = st->chip_info->channels;
	indio_dev->num_channels = st->chip_info->num_channels;
	indio_dev->info = &ad7793_info;

	ret = ad_sd_setup_buffer_and_trigger(indio_dev);
	if (ret)
		goto error_disable_reg;

	ret = ad7793_setup(indio_dev, pdata);
	if (ret)
		goto error_remove_trigger;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_remove_trigger;

	return 0;

error_remove_trigger:
	ad_sd_cleanup_buffer_and_trigger(indio_dev);
error_disable_reg:
	if (!IS_ERR(st->reg))
		regulator_disable(st->reg);
error_put_reg:
	if (!IS_ERR(st->reg))
		regulator_put(st->reg);

	iio_device_free(indio_dev);

	return ret;
}

static int ad7793_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct ad7793_state *st = iio_priv(indio_dev);

	iio_device_unregister(indio_dev);
	ad_sd_cleanup_buffer_and_trigger(indio_dev);

	if (!IS_ERR(st->reg)) {
		regulator_disable(st->reg);
		regulator_put(st->reg);
	}

	iio_device_free(indio_dev);

	return 0;
}

static const struct spi_device_id ad7793_id[] = {
	{"ad7785", ID_AD7785},
	{"ad7792", ID_AD7792},
	{"ad7793", ID_AD7793},
	{"ad7794", ID_AD7794},
	{"ad7795", ID_AD7795},
	{}
};
MODULE_DEVICE_TABLE(spi, ad7793_id);

static struct spi_driver ad7793_driver = {
	.driver = {
		.name	= "ad7793",
		.owner	= THIS_MODULE,
	},
	.probe		= ad7793_probe,
	.remove		= ad7793_remove,
	.id_table	= ad7793_id,
};
module_spi_driver(ad7793_driver);

MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
MODULE_DESCRIPTION("Analog Devices AD7793 and simialr ADCs");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
88bc3054	1	/*
8c29ecd3	2	* AD7785/AD7792/AD7793/AD7794/AD7795 SPI ADC driver
88bc3054	3	*
f316983f	4	* Copyright 2011-2012 Analog Devices Inc.
88bc3054 MH	5	*
	6	* Licensed under the GPL-2.
	7	*/
	8
	9	#include <linux/interrupt.h>
	10	#include <linux/device.h>
	11	#include <linux/kernel.h>
	12	#include <linux/slab.h>
	13	#include <linux/sysfs.h>
	14	#include <linux/spi/spi.h>
	15	#include <linux/regulator/consumer.h>
	16	#include <linux/err.h>
	17	#include <linux/sched.h>
	18	#include <linux/delay.h>
45296236	19	#include <linux/module.h>
88bc3054	20
06458e27 JC	21	#include <linux/iio/iio.h>
	22	#include <linux/iio/sysfs.h>
	23	#include <linux/iio/buffer.h>
06458e27 JC	24	#include <linux/iio/trigger.h>
06458e27 JC	25	#include <linux/iio/trigger_consumer.h>
82796edc	26	#include <linux/iio/triggered_buffer.h>
1abec6ac	27	#include <linux/iio/adc/ad_sigma_delta.h>
88bc3054 MH	28
	29	#include "ad7793.h"
	30
	31	/* NOTE:
	32	* The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
	33	* In order to avoid contentions on the SPI bus, it's therefore necessary
	34	* to use spi bus locking.
	35	*
	36	* The DOUT/RDY output must also be wired to an interrupt capable GPIO.
	37	*/
	38
	39	struct ad7793_chip_info {
525e643e LPC	40	const struct iio_chan_spec *channels;
525e643e LPC	41	unsigned int num_channels;
88bc3054 MH	42	};
	43
	44	struct ad7793_state {
88bc3054 MH	45	const struct ad7793_chip_info *chip_info;
88bc3054 MH	46	struct regulator *reg;
88bc3054 MH	47	u16 int_vref_mv;
	48	u16 mode;
	49	u16 conf;
	50	u32 scale_avail[8][2];
8c2c6ba6	51
1abec6ac LPC	52	struct ad_sigma_delta sd;
1abec6ac LPC	53
88bc3054 MH	54	};
	55
	56	enum ad7793_supported_device_ids {
8c29ecd3	57	ID_AD7785,
88bc3054 MH	58	ID_AD7792,
88bc3054 MH	59	ID_AD7793,
525e643e LPC	60	ID_AD7794,
525e643e LPC	61	ID_AD7795,
88bc3054 MH	62	};
88bc3054 MH	63
1abec6ac	64	static struct ad7793_state ad_sigma_delta_to_ad7793(struct ad_sigma_delta sd)
88bc3054	65	{
1abec6ac	66	return container_of(sd, struct ad7793_state, sd);
88bc3054 MH	67	}
88bc3054 MH	68
1abec6ac	69	static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
88bc3054	70	{
1abec6ac	71	struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
88bc3054	72
1abec6ac LPC	73	st->conf &= ~AD7793_CONF_CHAN_MASK;
1abec6ac LPC	74	st->conf \|= AD7793_CONF_CHAN(channel);
88bc3054	75
1abec6ac	76	return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf);
88bc3054 MH	77	}
88bc3054 MH	78
1abec6ac LPC	79	static int ad7793_set_mode(struct ad_sigma_delta *sd,
1abec6ac LPC	80	enum ad_sigma_delta_mode mode)
88bc3054	81	{
1abec6ac	82	struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
88bc3054	83
1abec6ac LPC	84	st->mode &= ~AD7793_MODE_SEL_MASK;
1abec6ac LPC	85	st->mode \|= AD7793_MODE_SEL(mode);
88bc3054	86
1abec6ac	87	return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode);
88bc3054 MH	88	}
88bc3054 MH	89
1abec6ac LPC	90	static const struct ad_sigma_delta_info ad7793_sigma_delta_info = {
	91	.set_channel = ad7793_set_channel,
	92	.set_mode = ad7793_set_mode,
	93	.has_registers = true,
	94	.addr_shift = 3,
	95	.read_mask = BIT(6),
	96	};
88bc3054	97
1abec6ac	98	static const struct ad_sd_calib_data ad7793_calib_arr[6] = {
88bc3054 MH	99	{AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
	100	{AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
	101	{AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
	102	{AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
	103	{AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
	104	{AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
	105	};
	106
	107	static int ad7793_calibrate_all(struct ad7793_state *st)
	108	{
1abec6ac LPC	109	return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr,
1abec6ac LPC	110	ARRAY_SIZE(ad7793_calib_arr));
88bc3054 MH	111	}
88bc3054 MH	112
1abec6ac	113	static int ad7793_setup(struct iio_dev *indio_dev,
c8c194d5	114	const struct ad7793_platform_data *pdata)
88bc3054	115	{
1abec6ac	116	struct ad7793_state *st = iio_priv(indio_dev);
88bc3054 MH	117	int i, ret = -1;
	118	unsigned long long scale_uv;
	119	u32 id;
	120
	121	/* reset the serial interface */
1abec6ac	122	ret = spi_write(st->sd.spi, (u8 *)&ret, sizeof(ret));
88bc3054 MH	123	if (ret < 0)
	124	goto out;
	125	msleep(1); /* Wait for at least 500us */
	126
	127	/* write/read test for device presence */
1abec6ac	128	ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id);
88bc3054 MH	129	if (ret)
	130	goto out;
	131
	132	id &= AD7793_ID_MASK;
	133
525e643e	134	if (!((id == AD7792_ID) \|\| (id == AD7793_ID) \|\| (id == AD7795_ID))) {
1abec6ac	135	dev_err(&st->sd.spi->dev, "device ID query failed\n");
88bc3054 MH	136	goto out;
	137	}
	138
1abec6ac LPC	139	st->mode = pdata->mode;
1abec6ac LPC	140	st->conf = pdata->conf;
88bc3054	141
1abec6ac	142	ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE);
88bc3054 MH	143	if (ret)
	144	goto out;
	145
1abec6ac	146	ret = ad7793_set_channel(&st->sd, 0);
88bc3054 MH	147	if (ret)
	148	goto out;
	149
1abec6ac	150	ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO,
c8c194d5	151	sizeof(pdata->io), pdata->io);
88bc3054 MH	152	if (ret)
	153	goto out;
	154
	155	ret = ad7793_calibrate_all(st);
	156	if (ret)
	157	goto out;
	158
	159	/* Populate available ADC input ranges */
	160	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
	161	scale_uv = ((u64)st->int_vref_mv * 100000000)
525e643e	162	>> (st->chip_info->channels[0].scan_type.realbits -
88bc3054 MH	163	(!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
	164	scale_uv >>= i;
	165
	166	st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
	167	st->scale_avail[i][0] = scale_uv;
	168	}
	169
	170	return 0;
	171	out:
1abec6ac	172	dev_err(&st->sd.spi->dev, "setup failed\n");
88bc3054 MH	173	return ret;
	174	}
	175
88bc3054 MH	176	static const u16 sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 33, 19,
	177	17, 16, 12, 10, 8, 6, 4};
	178
	179	static ssize_t ad7793_read_frequency(struct device *dev,
	180	struct device_attribute *attr,
	181	char *buf)
	182	{
62c51839	183	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
88bc3054 MH	184	struct ad7793_state *st = iio_priv(indio_dev);
	185
	186	return sprintf(buf, "%d\n",
	187	sample_freq_avail[AD7793_MODE_RATE(st->mode)]);
	188	}
	189
	190	static ssize_t ad7793_write_frequency(struct device *dev,
	191	struct device_attribute *attr,
	192	const char *buf,
	193	size_t len)
	194	{
62c51839	195	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
88bc3054 MH	196	struct ad7793_state *st = iio_priv(indio_dev);
	197	long lval;
	198	int i, ret;
	199
	200	mutex_lock(&indio_dev->mlock);
14555b14	201	if (iio_buffer_enabled(indio_dev)) {
88bc3054 MH	202	mutex_unlock(&indio_dev->mlock);
	203	return -EBUSY;
	204	}
	205	mutex_unlock(&indio_dev->mlock);
	206
	207	ret = strict_strtol(buf, 10, &lval);
	208	if (ret)
	209	return ret;
	210
	211	ret = -EINVAL;
	212
	213	for (i = 0; i < ARRAY_SIZE(sample_freq_avail); i++)
	214	if (lval == sample_freq_avail[i]) {
	215	mutex_lock(&indio_dev->mlock);
	216	st->mode &= ~AD7793_MODE_RATE(-1);
	217	st->mode \|= AD7793_MODE_RATE(i);
1abec6ac	218	ad_sd_write_reg(&st->sd, AD7793_REG_MODE,
88bc3054 MH	219	sizeof(st->mode), st->mode);
	220	mutex_unlock(&indio_dev->mlock);
	221	ret = 0;
	222	}
	223
	224	return ret ? ret : len;
	225	}
	226
	227	static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR \| S_IRUGO,
	228	ad7793_read_frequency,
	229	ad7793_write_frequency);
	230
	231	static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
	232	"470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
	233
	234	static ssize_t ad7793_show_scale_available(struct device *dev,
	235	struct device_attribute attr, char buf)
	236	{
62c51839	237	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
88bc3054 MH	238	struct ad7793_state *st = iio_priv(indio_dev);
	239	int i, len = 0;
	240
	241	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
	242	len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
	243	st->scale_avail[i][1]);
	244
	245	len += sprintf(buf + len, "\n");
	246
	247	return len;
	248	}
	249
08ca3b78 LPC	250	static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available,
	251	in_voltage-voltage_scale_available, S_IRUGO,
	252	ad7793_show_scale_available, NULL, 0);
88bc3054 MH	253
	254	static struct attribute *ad7793_attributes[] = {
	255	&iio_dev_attr_sampling_frequency.dev_attr.attr,
	256	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
	257	&iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
	258	NULL
	259	};
	260
	261	static const struct attribute_group ad7793_attribute_group = {
	262	.attrs = ad7793_attributes,
	263	};
	264
	265	static int ad7793_read_raw(struct iio_dev *indio_dev,
	266	struct iio_chan_spec const *chan,
	267	int *val,
	268	int *val2,
	269	long m)
	270	{
	271	struct ad7793_state *st = iio_priv(indio_dev);
1abec6ac	272	int ret;
88bc3054 MH	273	unsigned long long scale_uv;
	274	bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
	275
	276	switch (m) {
b11f98ff	277	case IIO_CHAN_INFO_RAW:
1abec6ac	278	ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
88bc3054 MH	279	if (ret < 0)
	280	return ret;
	281
88bc3054 MH	282	return IIO_VAL_INT;
88bc3054 MH	283
c8a9f805	284	case IIO_CHAN_INFO_SCALE:
88bc3054	285	switch (chan->type) {
6835cb6b	286	case IIO_VOLTAGE:
c8a9f805 JC	287	if (chan->differential) {
	288	*val = st->
	289	scale_avail[(st->conf >> 8) & 0x7][0];
	290	*val2 = st->
	291	scale_avail[(st->conf >> 8) & 0x7][1];
	292	return IIO_VAL_INT_PLUS_NANO;
	293	} else {
	294	/* 1170mV / 2^23 * 6 */
24b27fa1	295	scale_uv = (1170ULL * 1000000000ULL * 6ULL);
c8a9f805	296	}
88bc3054 MH	297	break;
88bc3054 MH	298	case IIO_TEMP:
2a9e0662	299	/* 1170mV / 0.81 mV/C / 2^23 */
e4ac7283	300	scale_uv = 1444444444444444ULL;
88bc3054 MH	301	break;
	302	default:
	303	return -EINVAL;
	304	}
	305
2a9e0662 LPC	306	scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1));
	307	*val = 0;
	308	*val2 = scale_uv;
88bc3054	309	return IIO_VAL_INT_PLUS_NANO;
680f8ea0 LPC	310	case IIO_CHAN_INFO_OFFSET:
680f8ea0 LPC	311	if (!unipolar)
2a9e0662	312	*val = -(1 << (chan->scan_type.realbits - 1));
680f8ea0 LPC	313	else
680f8ea0 LPC	314	*val = 0;
2a9e0662 LPC	315
	316	/* Kelvin to Celsius */
	317	if (chan->type == IIO_TEMP) {
	318	unsigned long long offset;
	319	unsigned int shift;
	320
	321	shift = chan->scan_type.realbits - (unipolar ? 0 : 1);
	322	offset = 273ULL << shift;
	323	do_div(offset, 1444);
	324	*val -= offset;
	325	}
680f8ea0	326	return IIO_VAL_INT;
88bc3054 MH	327	}
	328	return -EINVAL;
	329	}
	330
	331	static int ad7793_write_raw(struct iio_dev *indio_dev,
	332	struct iio_chan_spec const *chan,
	333	int val,
	334	int val2,
	335	long mask)
	336	{
	337	struct ad7793_state *st = iio_priv(indio_dev);
	338	int ret, i;
	339	unsigned int tmp;
	340
	341	mutex_lock(&indio_dev->mlock);
14555b14	342	if (iio_buffer_enabled(indio_dev)) {
88bc3054 MH	343	mutex_unlock(&indio_dev->mlock);
	344	return -EBUSY;
	345	}
	346
	347	switch (mask) {
c8a9f805	348	case IIO_CHAN_INFO_SCALE:
88bc3054 MH	349	ret = -EINVAL;
	350	for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
	351	if (val2 == st->scale_avail[i][1]) {
1abec6ac	352	ret = 0;
88bc3054 MH	353	tmp = st->conf;
	354	st->conf &= ~AD7793_CONF_GAIN(-1);
	355	st->conf \|= AD7793_CONF_GAIN(i);
	356
1abec6ac LPC	357	if (tmp == st->conf)
	358	break;
	359
	360	ad_sd_write_reg(&st->sd, AD7793_REG_CONF,
	361	sizeof(st->conf), st->conf);
	362	ad7793_calibrate_all(st);
	363	break;
88bc3054	364	}
421afe58	365	break;
88bc3054 MH	366	default:
	367	ret = -EINVAL;
	368	}
	369
	370	mutex_unlock(&indio_dev->mlock);
	371	return ret;
	372	}
	373
88bc3054 MH	374	static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
	375	struct iio_chan_spec const *chan,
	376	long mask)
	377	{
	378	return IIO_VAL_INT_PLUS_NANO;
	379	}
	380
	381	static const struct iio_info ad7793_info = {
	382	.read_raw = &ad7793_read_raw,
	383	.write_raw = &ad7793_write_raw,
	384	.write_raw_get_fmt = &ad7793_write_raw_get_fmt,
	385	.attrs = &ad7793_attribute_group,
1abec6ac	386	.validate_trigger = ad_sd_validate_trigger,
88bc3054 MH	387	.driver_module = THIS_MODULE,
	388	};
	389
8c29ecd3	390	#define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \
525e643e	391	const struct iio_chan_spec _name##_channels[] = { \
8c29ecd3 LPC	392	AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \
	393	AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \
	394	AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \
	395	AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \
	396	AD_SD_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \
	397	AD_SD_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \
525e643e LPC	398	IIO_CHAN_SOFT_TIMESTAMP(6), \
	399	}
	400
	401	#define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \
	402	const struct iio_chan_spec _name##_channels[] = { \
	403	AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
	404	AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
	405	AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
	406	AD_SD_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \
	407	AD_SD_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \
	408	AD_SD_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \
	409	AD_SD_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
	410	AD_SD_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \
	411	AD_SD_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
	412	IIO_CHAN_SOFT_TIMESTAMP(9), \
	413	}
	414
8c29ecd3 LPC	415	static DECLARE_AD7793_CHANNELS(ad7785, 20, 32, 4);
	416	static DECLARE_AD7793_CHANNELS(ad7792, 16, 32, 0);
	417	static DECLARE_AD7793_CHANNELS(ad7793, 24, 32, 0);
525e643e LPC	418	static DECLARE_AD7795_CHANNELS(ad7794, 16, 32);
	419	static DECLARE_AD7795_CHANNELS(ad7795, 24, 32);
	420
88bc3054	421	static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
8c29ecd3 LPC	422	[ID_AD7785] = {
	423	.channels = ad7785_channels,
	424	.num_channels = ARRAY_SIZE(ad7785_channels),
	425	},
525e643e LPC	426	[ID_AD7792] = {
	427	.channels = ad7792_channels,
	428	.num_channels = ARRAY_SIZE(ad7792_channels),
	429	},
88bc3054	430	[ID_AD7793] = {
525e643e LPC	431	.channels = ad7793_channels,
525e643e LPC	432	.num_channels = ARRAY_SIZE(ad7793_channels),
88bc3054	433	},
525e643e LPC	434	[ID_AD7794] = {
	435	.channels = ad7794_channels,
	436	.num_channels = ARRAY_SIZE(ad7794_channels),
	437	},
	438	[ID_AD7795] = {
	439	.channels = ad7795_channels,
	440	.num_channels = ARRAY_SIZE(ad7795_channels),
88bc3054 MH	441	},
	442	};
	443
4ae1c61f	444	static int ad7793_probe(struct spi_device *spi)
88bc3054	445	{
c8c194d5	446	const struct ad7793_platform_data *pdata = spi->dev.platform_data;
88bc3054 MH	447	struct ad7793_state *st;
88bc3054 MH	448	struct iio_dev *indio_dev;
8c2c6ba6	449	int ret, voltage_uv = 0;
88bc3054 MH	450
	451	if (!pdata) {
	452	dev_err(&spi->dev, "no platform data?\n");
	453	return -ENODEV;
	454	}
	455
	456	if (!spi->irq) {
	457	dev_err(&spi->dev, "no IRQ?\n");
	458	return -ENODEV;
	459	}
	460
7cbb7537	461	indio_dev = iio_device_alloc(sizeof(*st));
88bc3054 MH	462	if (indio_dev == NULL)
	463	return -ENOMEM;
	464
	465	st = iio_priv(indio_dev);
	466
1abec6ac LPC	467	ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info);
1abec6ac LPC	468
88bc3054 MH	469	st->reg = regulator_get(&spi->dev, "vcc");
	470	if (!IS_ERR(st->reg)) {
	471	ret = regulator_enable(st->reg);
	472	if (ret)
	473	goto error_put_reg;
	474
	475	voltage_uv = regulator_get_voltage(st->reg);
	476	}
	477
	478	st->chip_info =
	479	&ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
	480
88bc3054 MH	481	if (pdata && pdata->vref_mv)
	482	st->int_vref_mv = pdata->vref_mv;
	483	else if (voltage_uv)
	484	st->int_vref_mv = voltage_uv / 1000;
	485	else
87a0c157	486	st->int_vref_mv = 1170; /* Build-in ref */
88bc3054 MH	487
88bc3054 MH	488	spi_set_drvdata(spi, indio_dev);
88bc3054 MH	489
	490	indio_dev->dev.parent = &spi->dev;
	491	indio_dev->name = spi_get_device_id(spi)->name;
	492	indio_dev->modes = INDIO_DIRECT_MODE;
525e643e LPC	493	indio_dev->channels = st->chip_info->channels;
525e643e LPC	494	indio_dev->num_channels = st->chip_info->num_channels;
88bc3054 MH	495	indio_dev->info = &ad7793_info;
88bc3054 MH	496
1abec6ac	497	ret = ad_sd_setup_buffer_and_trigger(indio_dev);
88bc3054 MH	498	if (ret)
	499	goto error_disable_reg;
	500
1abec6ac	501	ret = ad7793_setup(indio_dev, pdata);
88bc3054	502	if (ret)
82796edc	503	goto error_remove_trigger;
88bc3054	504
26d25ae3 JC	505	ret = iio_device_register(indio_dev);
26d25ae3 JC	506	if (ret)
82796edc	507	goto error_remove_trigger;
26d25ae3	508
88bc3054 MH	509	return 0;
88bc3054 MH	510
88bc3054	511	error_remove_trigger:
1abec6ac	512	ad_sd_cleanup_buffer_and_trigger(indio_dev);
88bc3054 MH	513	error_disable_reg:
	514	if (!IS_ERR(st->reg))
	515	regulator_disable(st->reg);
	516	error_put_reg:
	517	if (!IS_ERR(st->reg))
	518	regulator_put(st->reg);
	519
7cbb7537	520	iio_device_free(indio_dev);
88bc3054 MH	521
	522	return ret;
	523	}
	524
447d4f29	525	static int ad7793_remove(struct spi_device *spi)
88bc3054 MH	526	{
	527	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	528	struct ad7793_state *st = iio_priv(indio_dev);
	529
d2fffd6c	530	iio_device_unregister(indio_dev);
1abec6ac	531	ad_sd_cleanup_buffer_and_trigger(indio_dev);
88bc3054 MH	532
	533	if (!IS_ERR(st->reg)) {
	534	regulator_disable(st->reg);
	535	regulator_put(st->reg);
	536	}
	537
7cbb7537	538	iio_device_free(indio_dev);
88bc3054 MH	539
	540	return 0;
	541	}
	542
	543	static const struct spi_device_id ad7793_id[] = {
8c29ecd3	544	{"ad7785", ID_AD7785},
88bc3054 MH	545	{"ad7792", ID_AD7792},
88bc3054 MH	546	{"ad7793", ID_AD7793},
525e643e LPC	547	{"ad7794", ID_AD7794},
525e643e LPC	548	{"ad7795", ID_AD7795},
88bc3054 MH	549	{}
88bc3054 MH	550	};
55e4390c	551	MODULE_DEVICE_TABLE(spi, ad7793_id);
88bc3054 MH	552
	553	static struct spi_driver ad7793_driver = {
	554	.driver = {
	555	.name = "ad7793",
88bc3054 MH	556	.owner = THIS_MODULE,
	557	},
	558	.probe = ad7793_probe,
e543acf0	559	.remove = ad7793_remove,
88bc3054 MH	560	.id_table = ad7793_id,
88bc3054 MH	561	};
ae6ae6fe	562	module_spi_driver(ad7793_driver);
88bc3054 MH	563
88bc3054 MH	564	MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
525e643e	565	MODULE_DESCRIPTION("Analog Devices AD7793 and simialr ADCs");
88bc3054	566	MODULE_LICENSE("GPL v2");