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staging:iio:adis16400_ring: Pass IIO device directly
[linux-2.6-block.git] / drivers / staging / iio / adc / ad7793.c
CommitLineData
88bc3054
MH		 1/*
2 * AD7792/AD7793 SPI ADC driver
3 *
f316983f 4 * Copyright 2011-2012 Analog Devices Inc.
88bc3054
MH		 5 *
6 * Licensed under the GPL-2.
7 */
8
9#include <linux/interrupt.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/sysfs.h>
14#include <linux/spi/spi.h>
15#include <linux/regulator/consumer.h>
16#include <linux/err.h>
17#include <linux/sched.h>
18#include <linux/delay.h>
45296236 19#include <linux/module.h>
88bc3054 20
06458e27
JC		 21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23#include <linux/iio/buffer.h>
f316983f 24#include <linux/iio/kfifo_buf.h>
06458e27
JC		 25#include <linux/iio/trigger.h>
26#include <linux/iio/trigger_consumer.h>
88bc3054
MH		 27
28#include "ad7793.h"
29
30/* NOTE:
31 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
32 * In order to avoid contentions on the SPI bus, it's therefore necessary
33 * to use spi bus locking.
34 *
35 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
36 */
37
38struct ad7793_chip_info {
39 struct iio_chan_spec channel[7];
40};
41
42struct ad7793_state {
43 struct spi_device *spi;
44 struct iio_trigger *trig;
45 const struct ad7793_chip_info *chip_info;
46 struct regulator *reg;
47 struct ad7793_platform_data *pdata;
48 wait_queue_head_t wq_data_avail;
49 bool done;
50 bool irq_dis;
51 u16 int_vref_mv;
52 u16 mode;
53 u16 conf;
54 u32 scale_avail[8][2];
32b5eeca
JC		 55 /* Note this uses fact that 8 the mask always fits in a long */
56 unsigned long available_scan_masks[7];
88bc3054
MH		 57 /*
58 * DMA (thus cache coherency maintenance) requires the
59 * transfer buffers to live in their own cache lines.
60 */
61 u8 data[4] ____cacheline_aligned;
62};
63
64enum ad7793_supported_device_ids {
65 ID_AD7792,
66 ID_AD7793,
67};
68
69static int __ad7793_write_reg(struct ad7793_state *st, bool locked,
70 bool cs_change, unsigned char reg,
71 unsigned size, unsigned val)
72{
73 u8 *data = st->data;
74 struct spi_transfer t = {
75 .tx_buf = data,
76 .len = size + 1,
77 .cs_change = cs_change,
78 };
79 struct spi_message m;
80
81 data[0] = AD7793_COMM_WRITE | AD7793_COMM_ADDR(reg);
82
83 switch (size) {
84 case 3:
85 data[1] = val >> 16;
86 data[2] = val >> 8;
87 data[3] = val;
88 break;
89 case 2:
90 data[1] = val >> 8;
91 data[2] = val;
92 break;
93 case 1:
94 data[1] = val;
95 break;
96 default:
97 return -EINVAL;
98 }
99
100 spi_message_init(&m);
101 spi_message_add_tail(&t, &m);
102
103 if (locked)
104 return spi_sync_locked(st->spi, &m);
105 else
106 return spi_sync(st->spi, &m);
107}
108
109static int ad7793_write_reg(struct ad7793_state *st,
110 unsigned reg, unsigned size, unsigned val)
111{
112 return __ad7793_write_reg(st, false, false, reg, size, val);
113}
114
115static int __ad7793_read_reg(struct ad7793_state *st, bool locked,
116 bool cs_change, unsigned char reg,
117 int *val, unsigned size)
118{
119 u8 *data = st->data;
120 int ret;
121 struct spi_transfer t[] = {
122 {
123 .tx_buf = data,
124 .len = 1,
125 }, {
126 .rx_buf = data,
127 .len = size,
128 .cs_change = cs_change,
129 },
130 };
131 struct spi_message m;
132
133 data[0] = AD7793_COMM_READ | AD7793_COMM_ADDR(reg);
134
135 spi_message_init(&m);
136 spi_message_add_tail(&t[0], &m);
137 spi_message_add_tail(&t[1], &m);
138
139 if (locked)
140 ret = spi_sync_locked(st->spi, &m);
141 else
142 ret = spi_sync(st->spi, &m);
143
144 if (ret < 0)
145 return ret;
146
147 switch (size) {
148 case 3:
149 *val = data[0] << 16 | data[1] << 8 | data[2];
150 break;
151 case 2:
152 *val = data[0] << 8 | data[1];
153 break;
154 case 1:
155 *val = data[0];
156 break;
157 default:
158 return -EINVAL;
159 }
160
161 return 0;
162}
163
164static int ad7793_read_reg(struct ad7793_state *st,
165 unsigned reg, int *val, unsigned size)
166{
167 return __ad7793_read_reg(st, 0, 0, reg, val, size);
168}
169
170static int ad7793_read(struct ad7793_state *st, unsigned ch,
171 unsigned len, int *val)
172{
173 int ret;
174 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch);
175 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
176 AD7793_MODE_SEL(AD7793_MODE_SINGLE);
177
178 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
179
180 spi_bus_lock(st->spi->master);
181 st->done = false;
182
183 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
184 sizeof(st->mode), st->mode);
185 if (ret < 0)
186 goto out;
187
188 st->irq_dis = false;
189 enable_irq(st->spi->irq);
190 wait_event_interruptible(st->wq_data_avail, st->done);
191
192 ret = __ad7793_read_reg(st, 1, 0, AD7793_REG_DATA, val, len);
193out:
194 spi_bus_unlock(st->spi->master);
195
196 return ret;
197}
198
199static int ad7793_calibrate(struct ad7793_state *st, unsigned mode, unsigned ch)
200{
201 int ret;
202
203 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch);
204 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) | AD7793_MODE_SEL(mode);
205
206 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
207
208 spi_bus_lock(st->spi->master);
209 st->done = false;
210
211 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
212 sizeof(st->mode), st->mode);
213 if (ret < 0)
214 goto out;
215
216 st->irq_dis = false;
217 enable_irq(st->spi->irq);
218 wait_event_interruptible(st->wq_data_avail, st->done);
219
220 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
221 AD7793_MODE_SEL(AD7793_MODE_IDLE);
222
223 ret = __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
224 sizeof(st->mode), st->mode);
225out:
226 spi_bus_unlock(st->spi->master);
227
228 return ret;
229}
230
231static const u8 ad7793_calib_arr[6][2] = {
232 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
233 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
234 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
235 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
236 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
237 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
238};
239
240static int ad7793_calibrate_all(struct ad7793_state *st)
241{
242 int i, ret;
243
244 for (i = 0; i < ARRAY_SIZE(ad7793_calib_arr); i++) {
245 ret = ad7793_calibrate(st, ad7793_calib_arr[i][0],
246 ad7793_calib_arr[i][1]);
247 if (ret)
248 goto out;
249 }
250
251 return 0;
252out:
253 dev_err(&st->spi->dev, "Calibration failed\n");
254 return ret;
255}
256
257static int ad7793_setup(struct ad7793_state *st)
258{
259 int i, ret = -1;
260 unsigned long long scale_uv;
261 u32 id;
262
263 /* reset the serial interface */
264 ret = spi_write(st->spi, (u8 *)&ret, sizeof(ret));
265 if (ret < 0)
266 goto out;
267 msleep(1); /* Wait for at least 500us */
268
269 /* write/read test for device presence */
270 ret = ad7793_read_reg(st, AD7793_REG_ID, &id, 1);
271 if (ret)
272 goto out;
273
274 id &= AD7793_ID_MASK;
275
276 if (!((id == AD7792_ID) || (id == AD7793_ID))) {
277 dev_err(&st->spi->dev, "device ID query failed\n");
278 goto out;
279 }
280
281 st->mode = (st->pdata->mode & ~AD7793_MODE_SEL(-1)) |
282 AD7793_MODE_SEL(AD7793_MODE_IDLE);
283 st->conf = st->pdata->conf & ~AD7793_CONF_CHAN(-1);
284
285 ret = ad7793_write_reg(st, AD7793_REG_MODE, sizeof(st->mode), st->mode);
286 if (ret)
287 goto out;
288
289 ret = ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
290 if (ret)
291 goto out;
292
293 ret = ad7793_write_reg(st, AD7793_REG_IO,
294 sizeof(st->pdata->io), st->pdata->io);
295 if (ret)
296 goto out;
297
298 ret = ad7793_calibrate_all(st);
299 if (ret)
300 goto out;
301
302 /* Populate available ADC input ranges */
303 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
304 scale_uv = ((u64)st->int_vref_mv * 100000000)
305 >> (st->chip_info->channel[0].scan_type.realbits -
306 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
307 scale_uv >>= i;
308
309 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
310 st->scale_avail[i][0] = scale_uv;
311 }
312
313 return 0;
314out:
315 dev_err(&st->spi->dev, "setup failed\n");
316 return ret;
317}
318
88bc3054
MH		 319static int ad7793_ring_preenable(struct iio_dev *indio_dev)
320{
321 struct ad7793_state *st = iio_priv(indio_dev);
88bc3054 322 unsigned channel;
81a4fc01 323 int ret;
88bc3054 324
550268ca 325 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
88bc3054 326 return -EINVAL;
81a4fc01
JC		 327 ret = iio_sw_buffer_preenable(indio_dev);
328 if (ret < 0)
329 return ret;
88bc3054 330
550268ca 331 channel = find_first_bit(indio_dev->active_scan_mask,
32b5eeca 332 indio_dev->masklength);
88bc3054 333
88bc3054
MH		 334 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
335 AD7793_MODE_SEL(AD7793_MODE_CONT);
336 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) |
337 AD7793_CONF_CHAN(indio_dev->channels[channel].address);
338
339 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
340
341 spi_bus_lock(st->spi->master);
342 __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
343 sizeof(st->mode), st->mode);
344
345 st->irq_dis = false;
346 enable_irq(st->spi->irq);
347
348 return 0;
349}
350
351static int ad7793_ring_postdisable(struct iio_dev *indio_dev)
352{
353 struct ad7793_state *st = iio_priv(indio_dev);
354
355 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
356 AD7793_MODE_SEL(AD7793_MODE_IDLE);
357
358 st->done = false;
359 wait_event_interruptible(st->wq_data_avail, st->done);
360
361 if (!st->irq_dis)
362 disable_irq_nosync(st->spi->irq);
363
364 __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
365 sizeof(st->mode), st->mode);
366
367 return spi_bus_unlock(st->spi->master);
368}
369
370/**
371 * ad7793_trigger_handler() bh of trigger launched polling to ring buffer
372 **/
373
374static irqreturn_t ad7793_trigger_handler(int irq, void *p)
375{
376 struct iio_poll_func *pf = p;
e65bc6ac 377 struct iio_dev *indio_dev = pf->indio_dev;
14555b14 378 struct iio_buffer *ring = indio_dev->buffer;
88bc3054
MH		 379 struct ad7793_state *st = iio_priv(indio_dev);
380 s64 dat64[2];
381 s32 *dat32 = (s32 *)dat64;
382
550268ca 383 if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
88bc3054
MH		 384 __ad7793_read_reg(st, 1, 1, AD7793_REG_DATA,
385 dat32,
386 indio_dev->channels[0].scan_type.realbits/8);
387
388 /* Guaranteed to be aligned with 8 byte boundary */
fd6487f8 389 if (indio_dev->scan_timestamp)
88bc3054
MH		 390 dat64[1] = pf->timestamp;
391
392 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
393
394 iio_trigger_notify_done(indio_dev->trig);
395 st->irq_dis = false;
396 enable_irq(st->spi->irq);
397
398 return IRQ_HANDLED;
399}
400
14555b14 401static const struct iio_buffer_setup_ops ad7793_ring_setup_ops = {
88bc3054 402 .preenable = &ad7793_ring_preenable,
3b99fb76
JC		 403 .postenable = &iio_triggered_buffer_postenable,
404 .predisable = &iio_triggered_buffer_predisable,
88bc3054
MH		 405 .postdisable = &ad7793_ring_postdisable,
406};
407
408static int ad7793_register_ring_funcs_and_init(struct iio_dev *indio_dev)
409{
410 int ret;
411
f316983f 412 indio_dev->buffer = iio_kfifo_allocate(indio_dev);
14555b14 413 if (!indio_dev->buffer) {
88bc3054
MH		 414 ret = -ENOMEM;
415 goto error_ret;
416 }
88bc3054
MH		 417 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
418 &ad7793_trigger_handler,
419 IRQF_ONESHOT,
420 indio_dev,
421 "ad7793_consumer%d",
422 indio_dev->id);
423 if (indio_dev->pollfunc == NULL) {
424 ret = -ENOMEM;
f316983f 425 goto error_deallocate_kfifo;
88bc3054
MH		 426 }
427
428 /* Ring buffer functions - here trigger setup related */
1612244f 429 indio_dev->setup_ops = &ad7793_ring_setup_ops;
88bc3054
MH		 430
431 /* Flag that polled ring buffering is possible */
ec3afa40 432 indio_dev->modes |= INDIO_BUFFER_TRIGGERED;
88bc3054
MH		 433 return 0;
434
f316983f
MH		 435error_deallocate_kfifo:
436 iio_kfifo_free(indio_dev->buffer);
88bc3054
MH		 437error_ret:
438 return ret;
439}
440
441static void ad7793_ring_cleanup(struct iio_dev *indio_dev)
442{
88bc3054 443 iio_dealloc_pollfunc(indio_dev->pollfunc);
f316983f 444 iio_kfifo_free(indio_dev->buffer);
88bc3054
MH		 445}
446
447/**
448 * ad7793_data_rdy_trig_poll() the event handler for the data rdy trig
449 **/
450static irqreturn_t ad7793_data_rdy_trig_poll(int irq, void *private)
451{
452 struct ad7793_state *st = iio_priv(private);
453
454 st->done = true;
455 wake_up_interruptible(&st->wq_data_avail);
456 disable_irq_nosync(irq);
457 st->irq_dis = true;
458 iio_trigger_poll(st->trig, iio_get_time_ns());
459
460 return IRQ_HANDLED;
461}
462
8324e860
JC		 463static struct iio_trigger_ops ad7793_trigger_ops = {
464 .owner = THIS_MODULE,
465};
466
88bc3054
MH		 467static int ad7793_probe_trigger(struct iio_dev *indio_dev)
468{
469 struct ad7793_state *st = iio_priv(indio_dev);
470 int ret;
471
7cbb7537 472 st->trig = iio_trigger_alloc("%s-dev%d",
88bc3054
MH		 473 spi_get_device_id(st->spi)->name,
474 indio_dev->id);
475 if (st->trig == NULL) {
476 ret = -ENOMEM;
477 goto error_ret;
478 }
8324e860 479 st->trig->ops = &ad7793_trigger_ops;
88bc3054
MH		 480
481 ret = request_irq(st->spi->irq,
482 ad7793_data_rdy_trig_poll,
483 IRQF_TRIGGER_LOW,
484 spi_get_device_id(st->spi)->name,
485 indio_dev);
486 if (ret)
487 goto error_free_trig;
488
489 disable_irq_nosync(st->spi->irq);
490 st->irq_dis = true;
491 st->trig->dev.parent = &st->spi->dev;
88bc3054
MH		 492 st->trig->private_data = indio_dev;
493
494 ret = iio_trigger_register(st->trig);
495
496 /* select default trigger */
497 indio_dev->trig = st->trig;
498 if (ret)
499 goto error_free_irq;
500
501 return 0;
502
503error_free_irq:
504 free_irq(st->spi->irq, indio_dev);
505error_free_trig:
7cbb7537 506 iio_trigger_free(st->trig);
88bc3054
MH		 507error_ret:
508 return ret;
509}
510
511static void ad7793_remove_trigger(struct iio_dev *indio_dev)
512{
513 struct ad7793_state *st = iio_priv(indio_dev);
514
515 iio_trigger_unregister(st->trig);
516 free_irq(st->spi->irq, indio_dev);
7cbb7537 517 iio_trigger_free(st->trig);
88bc3054
MH		 518}
519
520static const u16 sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 33, 19,
521 17, 16, 12, 10, 8, 6, 4};
522
523static ssize_t ad7793_read_frequency(struct device *dev,
524 struct device_attribute *attr,
525 char *buf)
526{
527 struct iio_dev *indio_dev = dev_get_drvdata(dev);
528 struct ad7793_state *st = iio_priv(indio_dev);
529
530 return sprintf(buf, "%d\n",
531 sample_freq_avail[AD7793_MODE_RATE(st->mode)]);
532}
533
534static ssize_t ad7793_write_frequency(struct device *dev,
535 struct device_attribute *attr,
536 const char *buf,
537 size_t len)
538{
539 struct iio_dev *indio_dev = dev_get_drvdata(dev);
540 struct ad7793_state *st = iio_priv(indio_dev);
541 long lval;
542 int i, ret;
543
544 mutex_lock(&indio_dev->mlock);
14555b14 545 if (iio_buffer_enabled(indio_dev)) {
88bc3054
MH		 546 mutex_unlock(&indio_dev->mlock);
547 return -EBUSY;
548 }
549 mutex_unlock(&indio_dev->mlock);
550
551 ret = strict_strtol(buf, 10, &lval);
552 if (ret)
553 return ret;
554
555 ret = -EINVAL;
556
557 for (i = 0; i < ARRAY_SIZE(sample_freq_avail); i++)
558 if (lval == sample_freq_avail[i]) {
559 mutex_lock(&indio_dev->mlock);
560 st->mode &= ~AD7793_MODE_RATE(-1);
561 st->mode |= AD7793_MODE_RATE(i);
562 ad7793_write_reg(st, AD7793_REG_MODE,
563 sizeof(st->mode), st->mode);
564 mutex_unlock(&indio_dev->mlock);
565 ret = 0;
566 }
567
568 return ret ? ret : len;
569}
570
571static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
572 ad7793_read_frequency,
573 ad7793_write_frequency);
574
575static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
576 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
577
578static ssize_t ad7793_show_scale_available(struct device *dev,
579 struct device_attribute *attr, char *buf)
580{
581 struct iio_dev *indio_dev = dev_get_drvdata(dev);
582 struct ad7793_state *st = iio_priv(indio_dev);
583 int i, len = 0;
584
585 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
586 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
587 st->scale_avail[i][1]);
588
589 len += sprintf(buf + len, "\n");
590
591 return len;
592}
593
594static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available, in-in_scale_available,
595 S_IRUGO, ad7793_show_scale_available, NULL, 0);
596
597static struct attribute *ad7793_attributes[] = {
598 &iio_dev_attr_sampling_frequency.dev_attr.attr,
599 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
600 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
601 NULL
602};
603
604static const struct attribute_group ad7793_attribute_group = {
605 .attrs = ad7793_attributes,
606};
607
608static int ad7793_read_raw(struct iio_dev *indio_dev,
609 struct iio_chan_spec const *chan,
610 int *val,
611 int *val2,
612 long m)
613{
614 struct ad7793_state *st = iio_priv(indio_dev);
615 int ret, smpl = 0;
616 unsigned long long scale_uv;
617 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
618
619 switch (m) {
b11f98ff 620 case IIO_CHAN_INFO_RAW:
88bc3054 621 mutex_lock(&indio_dev->mlock);
14555b14 622 if (iio_buffer_enabled(indio_dev))
950935b1 623 ret = -EBUSY;
88bc3054
MH		 624 else
625 ret = ad7793_read(st, chan->address,
626 chan->scan_type.realbits / 8, &smpl);
627 mutex_unlock(&indio_dev->mlock);
628
629 if (ret < 0)
630 return ret;
631
632 *val = (smpl >> chan->scan_type.shift) &
633 ((1 << (chan->scan_type.realbits)) - 1);
634
635 if (!unipolar)
636 *val -= (1 << (chan->scan_type.realbits - 1));
637
638 return IIO_VAL_INT;
639
c8a9f805 640 case IIO_CHAN_INFO_SCALE:
88bc3054 641 switch (chan->type) {
6835cb6b 642 case IIO_VOLTAGE:
c8a9f805
JC		 643 if (chan->differential) {
644 *val = st->
645 scale_avail[(st->conf >> 8) & 0x7][0];
646 *val2 = st->
647 scale_avail[(st->conf >> 8) & 0x7][1];
648 return IIO_VAL_INT_PLUS_NANO;
649 } else {
650 /* 1170mV / 2^23 * 6 */
651 scale_uv = (1170ULL * 100000000ULL * 6ULL)
652 >> (chan->scan_type.realbits -
653 (unipolar ? 0 : 1));
654 }
88bc3054
MH		 655 break;
656 case IIO_TEMP:
657 /* Always uses unity gain and internal ref */
658 scale_uv = (2500ULL * 100000000ULL)
659 >> (chan->scan_type.realbits -
660 (unipolar ? 0 : 1));
661 break;
662 default:
663 return -EINVAL;
664 }
665
666 *val2 = do_div(scale_uv, 100000000) * 10;
667 *val = scale_uv;
668
669 return IIO_VAL_INT_PLUS_NANO;
670 }
671 return -EINVAL;
672}
673
674static int ad7793_write_raw(struct iio_dev *indio_dev,
675 struct iio_chan_spec const *chan,
676 int val,
677 int val2,
678 long mask)
679{
680 struct ad7793_state *st = iio_priv(indio_dev);
681 int ret, i;
682 unsigned int tmp;
683
684 mutex_lock(&indio_dev->mlock);
14555b14 685 if (iio_buffer_enabled(indio_dev)) {
88bc3054
MH		 686 mutex_unlock(&indio_dev->mlock);
687 return -EBUSY;
688 }
689
690 switch (mask) {
c8a9f805 691 case IIO_CHAN_INFO_SCALE:
88bc3054
MH		 692 ret = -EINVAL;
693 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
694 if (val2 == st->scale_avail[i][1]) {
695 tmp = st->conf;
696 st->conf &= ~AD7793_CONF_GAIN(-1);
697 st->conf |= AD7793_CONF_GAIN(i);
698
699 if (tmp != st->conf) {
700 ad7793_write_reg(st, AD7793_REG_CONF,
701 sizeof(st->conf),
702 st->conf);
703 ad7793_calibrate_all(st);
704 }
705 ret = 0;
706 }
707
708 default:
709 ret = -EINVAL;
710 }
711
712 mutex_unlock(&indio_dev->mlock);
713 return ret;
714}
715
716static int ad7793_validate_trigger(struct iio_dev *indio_dev,
717 struct iio_trigger *trig)
718{
719 if (indio_dev->trig != trig)
720 return -EINVAL;
721
722 return 0;
723}
724
725static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
726 struct iio_chan_spec const *chan,
727 long mask)
728{
729 return IIO_VAL_INT_PLUS_NANO;
730}
731
732static const struct iio_info ad7793_info = {
733 .read_raw = &ad7793_read_raw,
734 .write_raw = &ad7793_write_raw,
735 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
736 .attrs = &ad7793_attribute_group,
737 .validate_trigger = ad7793_validate_trigger,
738 .driver_module = THIS_MODULE,
739};
740
741static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
742 [ID_AD7793] = {
ade7ef7b
JC		 743 .channel[0] = {
744 .type = IIO_VOLTAGE,
745 .differential = 1,
746 .indexed = 1,
747 .channel = 0,
748 .channel2 = 0,
749 .address = AD7793_CH_AIN1P_AIN1M,
b11f98ff
JC		 750 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
751 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 752 .scan_index = 0,
753 .scan_type = IIO_ST('s', 24, 32, 0)
754 },
755 .channel[1] = {
756 .type = IIO_VOLTAGE,
757 .differential = 1,
758 .indexed = 1,
759 .channel = 1,
760 .channel2 = 1,
761 .address = AD7793_CH_AIN2P_AIN2M,
b11f98ff
JC		 762 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
763 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 764 .scan_index = 1,
765 .scan_type = IIO_ST('s', 24, 32, 0)
766 },
767 .channel[2] = {
768 .type = IIO_VOLTAGE,
769 .differential = 1,
770 .indexed = 1,
771 .channel = 2,
772 .channel2 = 2,
773 .address = AD7793_CH_AIN3P_AIN3M,
b11f98ff
JC		 774 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
775 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 776 .scan_index = 2,
777 .scan_type = IIO_ST('s', 24, 32, 0)
778 },
779 .channel[3] = {
780 .type = IIO_VOLTAGE,
781 .differential = 1,
782 .extend_name = "shorted",
783 .indexed = 1,
784 .channel = 2,
785 .channel2 = 2,
786 .address = AD7793_CH_AIN1M_AIN1M,
b11f98ff
JC		 787 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
788 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 789 .scan_index = 2,
790 .scan_type = IIO_ST('s', 24, 32, 0)
791 },
792 .channel[4] = {
793 .type = IIO_TEMP,
794 .indexed = 1,
795 .channel = 0,
796 .address = AD7793_CH_TEMP,
b11f98ff
JC		 797 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
798 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
ade7ef7b
JC		 799 .scan_index = 4,
800 .scan_type = IIO_ST('s', 24, 32, 0),
801 },
802 .channel[5] = {
803 .type = IIO_VOLTAGE,
804 .extend_name = "supply",
805 .indexed = 1,
806 .channel = 4,
807 .address = AD7793_CH_AVDD_MONITOR,
b11f98ff
JC		 808 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
809 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
ade7ef7b
JC		 810 .scan_index = 5,
811 .scan_type = IIO_ST('s', 24, 32, 0),
812 },
88bc3054
MH		 813 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
814 },
815 [ID_AD7792] = {
ade7ef7b
JC		 816 .channel[0] = {
817 .type = IIO_VOLTAGE,
818 .differential = 1,
819 .indexed = 1,
820 .channel = 0,
821 .channel2 = 0,
822 .address = AD7793_CH_AIN1P_AIN1M,
b11f98ff
JC		 823 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
824 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 825 .scan_index = 0,
826 .scan_type = IIO_ST('s', 16, 32, 0)
827 },
828 .channel[1] = {
829 .type = IIO_VOLTAGE,
830 .differential = 1,
831 .indexed = 1,
832 .channel = 1,
833 .channel2 = 1,
834 .address = AD7793_CH_AIN2P_AIN2M,
b11f98ff
JC		 835 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
836 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 837 .scan_index = 1,
838 .scan_type = IIO_ST('s', 16, 32, 0)
839 },
840 .channel[2] = {
841 .type = IIO_VOLTAGE,
842 .differential = 1,
843 .indexed = 1,
844 .channel = 2,
845 .channel2 = 2,
846 .address = AD7793_CH_AIN3P_AIN3M,
b11f98ff
JC		 847 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
848 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 849 .scan_index = 2,
850 .scan_type = IIO_ST('s', 16, 32, 0)
851 },
852 .channel[3] = {
853 .type = IIO_VOLTAGE,
854 .differential = 1,
855 .extend_name = "shorted",
856 .indexed = 1,
857 .channel = 2,
858 .channel2 = 2,
859 .address = AD7793_CH_AIN1M_AIN1M,
b11f98ff
JC		 860 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
861 IIO_CHAN_INFO_SCALE_SHARED_BIT,
ade7ef7b
JC		 862 .scan_index = 2,
863 .scan_type = IIO_ST('s', 16, 32, 0)
864 },
865 .channel[4] = {
866 .type = IIO_TEMP,
867 .indexed = 1,
868 .channel = 0,
869 .address = AD7793_CH_TEMP,
b11f98ff
JC		 870 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
871 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
ade7ef7b
JC		 872 .scan_index = 4,
873 .scan_type = IIO_ST('s', 16, 32, 0),
874 },
875 .channel[5] = {
876 .type = IIO_VOLTAGE,
877 .extend_name = "supply",
878 .indexed = 1,
879 .channel = 4,
880 .address = AD7793_CH_AVDD_MONITOR,
b11f98ff
JC		 881 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
882 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
ade7ef7b
JC		 883 .scan_index = 5,
884 .scan_type = IIO_ST('s', 16, 32, 0),
885 },
88bc3054
MH		 886 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
887 },
888};
889
890static int __devinit ad7793_probe(struct spi_device *spi)
891{
892 struct ad7793_platform_data *pdata = spi->dev.platform_data;
893 struct ad7793_state *st;
894 struct iio_dev *indio_dev;
26d25ae3 895 int ret, i, voltage_uv = 0;
88bc3054
MH		 896
897 if (!pdata) {
898 dev_err(&spi->dev, "no platform data?\n");
899 return -ENODEV;
900 }
901
902 if (!spi->irq) {
903 dev_err(&spi->dev, "no IRQ?\n");
904 return -ENODEV;
905 }
906
7cbb7537 907 indio_dev = iio_device_alloc(sizeof(*st));
88bc3054
MH		 908 if (indio_dev == NULL)
909 return -ENOMEM;
910
911 st = iio_priv(indio_dev);
912
913 st->reg = regulator_get(&spi->dev, "vcc");
914 if (!IS_ERR(st->reg)) {
915 ret = regulator_enable(st->reg);
916 if (ret)
917 goto error_put_reg;
918
919 voltage_uv = regulator_get_voltage(st->reg);
920 }
921
922 st->chip_info =
923 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
924
925 st->pdata = pdata;
926
927 if (pdata && pdata->vref_mv)
928 st->int_vref_mv = pdata->vref_mv;
929 else if (voltage_uv)
930 st->int_vref_mv = voltage_uv / 1000;
931 else
932 st->int_vref_mv = 2500; /* Build-in ref */
933
934 spi_set_drvdata(spi, indio_dev);
935 st->spi = spi;
936
937 indio_dev->dev.parent = &spi->dev;
938 indio_dev->name = spi_get_device_id(spi)->name;
939 indio_dev->modes = INDIO_DIRECT_MODE;
940 indio_dev->channels = st->chip_info->channel;
941 indio_dev->available_scan_masks = st->available_scan_masks;
942 indio_dev->num_channels = 7;
943 indio_dev->info = &ad7793_info;
944
32b5eeca
JC		 945 for (i = 0; i < indio_dev->num_channels; i++) {
946 set_bit(i, &st->available_scan_masks[i]);
947 set_bit(indio_dev->
948 channels[indio_dev->num_channels - 1].scan_index,
949 &st->available_scan_masks[i]);
950 }
88bc3054
MH		 951
952 init_waitqueue_head(&st->wq_data_avail);
953
954 ret = ad7793_register_ring_funcs_and_init(indio_dev);
955 if (ret)
956 goto error_disable_reg;
957
88bc3054
MH		 958 ret = ad7793_probe_trigger(indio_dev);
959 if (ret)
960 goto error_unreg_ring;
961
14555b14
JC		 962 ret = iio_buffer_register(indio_dev,
963 indio_dev->channels,
964 indio_dev->num_channels);
88bc3054
MH		 965 if (ret)
966 goto error_remove_trigger;
967
968 ret = ad7793_setup(st);
969 if (ret)
970 goto error_uninitialize_ring;
971
26d25ae3
JC		 972 ret = iio_device_register(indio_dev);
973 if (ret)
974 goto error_uninitialize_ring;
975
88bc3054
MH		 976 return 0;
977
978error_uninitialize_ring:
14555b14 979 iio_buffer_unregister(indio_dev);
88bc3054
MH		 980error_remove_trigger:
981 ad7793_remove_trigger(indio_dev);
982error_unreg_ring:
983 ad7793_ring_cleanup(indio_dev);
984error_disable_reg:
985 if (!IS_ERR(st->reg))
986 regulator_disable(st->reg);
987error_put_reg:
988 if (!IS_ERR(st->reg))
989 regulator_put(st->reg);
990
7cbb7537 991 iio_device_free(indio_dev);
88bc3054
MH		 992
993 return ret;
994}
995
996static int ad7793_remove(struct spi_device *spi)
997{
998 struct iio_dev *indio_dev = spi_get_drvdata(spi);
999 struct ad7793_state *st = iio_priv(indio_dev);
1000
d2fffd6c 1001 iio_device_unregister(indio_dev);
14555b14 1002 iio_buffer_unregister(indio_dev);
88bc3054
MH		 1003 ad7793_remove_trigger(indio_dev);
1004 ad7793_ring_cleanup(indio_dev);
1005
1006 if (!IS_ERR(st->reg)) {
1007 regulator_disable(st->reg);
1008 regulator_put(st->reg);
1009 }
1010
7cbb7537 1011 iio_device_free(indio_dev);
88bc3054
MH		 1012
1013 return 0;
1014}
1015
1016static const struct spi_device_id ad7793_id[] = {
1017 {"ad7792", ID_AD7792},
1018 {"ad7793", ID_AD7793},
1019 {}
1020};
55e4390c 1021MODULE_DEVICE_TABLE(spi, ad7793_id);
88bc3054
MH		 1022
1023static struct spi_driver ad7793_driver = {
1024 .driver = {
1025 .name = "ad7793",
88bc3054
MH		 1026 .owner = THIS_MODULE,
1027 },
1028 .probe = ad7793_probe,
1029 .remove = __devexit_p(ad7793_remove),
1030 .id_table = ad7793_id,
1031};
ae6ae6fe 1032module_spi_driver(ad7793_driver);
88bc3054
MH		 1033
1034MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1035MODULE_DESCRIPTION("Analog Devices AD7792/3 ADC");
1036MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)