projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge 3.6-rc3 into staging-next
[linux-2.6-block.git] / drivers / staging / iio / adc / ad7793.c
CommitLineData
88bc3054
MH		 1/*
2 * AD7792/AD7793 SPI ADC driver
3 *
f316983f 4 * Copyright 2011-2012 Analog Devices Inc.
88bc3054
MH		 5 *
6 * Licensed under the GPL-2.
7 */
8
9#include <linux/interrupt.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/sysfs.h>
14#include <linux/spi/spi.h>
15#include <linux/regulator/consumer.h>
16#include <linux/err.h>
17#include <linux/sched.h>
18#include <linux/delay.h>
45296236 19#include <linux/module.h>
88bc3054 20
06458e27
JC		 21#include <linux/iio/iio.h>
22#include <linux/iio/sysfs.h>
23#include <linux/iio/buffer.h>
06458e27
JC		 24#include <linux/iio/trigger.h>
25#include <linux/iio/trigger_consumer.h>
82796edc 26#include <linux/iio/triggered_buffer.h>
88bc3054
MH		 27
28#include "ad7793.h"
29
30/* NOTE:
31 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
32 * In order to avoid contentions on the SPI bus, it's therefore necessary
33 * to use spi bus locking.
34 *
35 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
36 */
37
38struct ad7793_chip_info {
39 struct iio_chan_spec channel[7];
40};
41
42struct ad7793_state {
43 struct spi_device *spi;
44 struct iio_trigger *trig;
45 const struct ad7793_chip_info *chip_info;
46 struct regulator *reg;
47 struct ad7793_platform_data *pdata;
48 wait_queue_head_t wq_data_avail;
49 bool done;
50 bool irq_dis;
51 u16 int_vref_mv;
52 u16 mode;
53 u16 conf;
54 u32 scale_avail[8][2];
8c2c6ba6 55
88bc3054
MH		 56 /*
57 * DMA (thus cache coherency maintenance) requires the
58 * transfer buffers to live in their own cache lines.
59 */
60 u8 data[4] ____cacheline_aligned;
61};
62
63enum ad7793_supported_device_ids {
64 ID_AD7792,
65 ID_AD7793,
66};
67
68static int __ad7793_write_reg(struct ad7793_state *st, bool locked,
69 bool cs_change, unsigned char reg,
70 unsigned size, unsigned val)
71{
72 u8 *data = st->data;
73 struct spi_transfer t = {
74 .tx_buf = data,
75 .len = size + 1,
76 .cs_change = cs_change,
77 };
78 struct spi_message m;
79
80 data[0] = AD7793_COMM_WRITE | AD7793_COMM_ADDR(reg);
81
82 switch (size) {
83 case 3:
84 data[1] = val >> 16;
85 data[2] = val >> 8;
86 data[3] = val;
87 break;
88 case 2:
89 data[1] = val >> 8;
90 data[2] = val;
91 break;
92 case 1:
93 data[1] = val;
94 break;
95 default:
96 return -EINVAL;
97 }
98
99 spi_message_init(&m);
100 spi_message_add_tail(&t, &m);
101
102 if (locked)
103 return spi_sync_locked(st->spi, &m);
104 else
105 return spi_sync(st->spi, &m);
106}
107
108static int ad7793_write_reg(struct ad7793_state *st,
109 unsigned reg, unsigned size, unsigned val)
110{
111 return __ad7793_write_reg(st, false, false, reg, size, val);
112}
113
114static int __ad7793_read_reg(struct ad7793_state *st, bool locked,
115 bool cs_change, unsigned char reg,
116 int *val, unsigned size)
117{
118 u8 *data = st->data;
119 int ret;
120 struct spi_transfer t[] = {
121 {
122 .tx_buf = data,
123 .len = 1,
124 }, {
125 .rx_buf = data,
126 .len = size,
127 .cs_change = cs_change,
128 },
129 };
130 struct spi_message m;
131
132 data[0] = AD7793_COMM_READ | AD7793_COMM_ADDR(reg);
133
134 spi_message_init(&m);
135 spi_message_add_tail(&t[0], &m);
136 spi_message_add_tail(&t[1], &m);
137
138 if (locked)
139 ret = spi_sync_locked(st->spi, &m);
140 else
141 ret = spi_sync(st->spi, &m);
142
143 if (ret < 0)
144 return ret;
145
146 switch (size) {
147 case 3:
148 *val = data[0] << 16 | data[1] << 8 | data[2];
149 break;
150 case 2:
151 *val = data[0] << 8 | data[1];
152 break;
153 case 1:
154 *val = data[0];
155 break;
156 default:
157 return -EINVAL;
158 }
159
160 return 0;
161}
162
163static int ad7793_read_reg(struct ad7793_state *st,
164 unsigned reg, int *val, unsigned size)
165{
166 return __ad7793_read_reg(st, 0, 0, reg, val, size);
167}
168
169static int ad7793_read(struct ad7793_state *st, unsigned ch,
170 unsigned len, int *val)
171{
172 int ret;
173 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch);
174 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
175 AD7793_MODE_SEL(AD7793_MODE_SINGLE);
176
177 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
178
179 spi_bus_lock(st->spi->master);
180 st->done = false;
181
182 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
183 sizeof(st->mode), st->mode);
184 if (ret < 0)
185 goto out;
186
187 st->irq_dis = false;
188 enable_irq(st->spi->irq);
189 wait_event_interruptible(st->wq_data_avail, st->done);
190
191 ret = __ad7793_read_reg(st, 1, 0, AD7793_REG_DATA, val, len);
192out:
193 spi_bus_unlock(st->spi->master);
194
195 return ret;
196}
197
198static int ad7793_calibrate(struct ad7793_state *st, unsigned mode, unsigned ch)
199{
200 int ret;
201
202 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch);
203 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) | AD7793_MODE_SEL(mode);
204
205 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
206
207 spi_bus_lock(st->spi->master);
208 st->done = false;
209
210 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
211 sizeof(st->mode), st->mode);
212 if (ret < 0)
213 goto out;
214
215 st->irq_dis = false;
216 enable_irq(st->spi->irq);
217 wait_event_interruptible(st->wq_data_avail, st->done);
218
219 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
220 AD7793_MODE_SEL(AD7793_MODE_IDLE);
221
222 ret = __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
223 sizeof(st->mode), st->mode);
224out:
225 spi_bus_unlock(st->spi->master);
226
227 return ret;
228}
229
230static const u8 ad7793_calib_arr[6][2] = {
231 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
232 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
233 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
234 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
235 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
236 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
237};
238
239static int ad7793_calibrate_all(struct ad7793_state *st)
240{
241 int i, ret;
242
243 for (i = 0; i < ARRAY_SIZE(ad7793_calib_arr); i++) {
244 ret = ad7793_calibrate(st, ad7793_calib_arr[i][0],
245 ad7793_calib_arr[i][1]);
246 if (ret)
247 goto out;
248 }
249
250 return 0;
251out:
252 dev_err(&st->spi->dev, "Calibration failed\n");
253 return ret;
254}
255
256static int ad7793_setup(struct ad7793_state *st)
257{
258 int i, ret = -1;
259 unsigned long long scale_uv;
260 u32 id;
261
262 /* reset the serial interface */
263 ret = spi_write(st->spi, (u8 *)&ret, sizeof(ret));
264 if (ret < 0)
265 goto out;
266 msleep(1); /* Wait for at least 500us */
267
268 /* write/read test for device presence */
269 ret = ad7793_read_reg(st, AD7793_REG_ID, &id, 1);
270 if (ret)
271 goto out;
272
273 id &= AD7793_ID_MASK;
274
275 if (!((id == AD7792_ID) || (id == AD7793_ID))) {
276 dev_err(&st->spi->dev, "device ID query failed\n");
277 goto out;
278 }
279
280 st->mode = (st->pdata->mode & ~AD7793_MODE_SEL(-1)) |
281 AD7793_MODE_SEL(AD7793_MODE_IDLE);
282 st->conf = st->pdata->conf & ~AD7793_CONF_CHAN(-1);
283
284 ret = ad7793_write_reg(st, AD7793_REG_MODE, sizeof(st->mode), st->mode);
285 if (ret)
286 goto out;
287
288 ret = ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
289 if (ret)
290 goto out;
291
292 ret = ad7793_write_reg(st, AD7793_REG_IO,
293 sizeof(st->pdata->io), st->pdata->io);
294 if (ret)
295 goto out;
296
297 ret = ad7793_calibrate_all(st);
298 if (ret)
299 goto out;
300
301 /* Populate available ADC input ranges */
302 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
303 scale_uv = ((u64)st->int_vref_mv * 100000000)
304 >> (st->chip_info->channel[0].scan_type.realbits -
305 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
306 scale_uv >>= i;
307
308 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
309 st->scale_avail[i][0] = scale_uv;
310 }
311
312 return 0;
313out:
314 dev_err(&st->spi->dev, "setup failed\n");
315 return ret;
316}
317
88bc3054
MH		 318static int ad7793_ring_preenable(struct iio_dev *indio_dev)
319{
320 struct ad7793_state *st = iio_priv(indio_dev);
88bc3054 321 unsigned channel;
81a4fc01 322 int ret;
88bc3054 323
550268ca 324 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
88bc3054 325 return -EINVAL;
81a4fc01
JC		 326 ret = iio_sw_buffer_preenable(indio_dev);
327 if (ret < 0)
328 return ret;
88bc3054 329
550268ca 330 channel = find_first_bit(indio_dev->active_scan_mask,
32b5eeca 331 indio_dev->masklength);
88bc3054 332
88bc3054
MH		 333 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
334 AD7793_MODE_SEL(AD7793_MODE_CONT);
335 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) |
336 AD7793_CONF_CHAN(indio_dev->channels[channel].address);
337
338 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
339
340 spi_bus_lock(st->spi->master);
341 __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
342 sizeof(st->mode), st->mode);
343
344 st->irq_dis = false;
345 enable_irq(st->spi->irq);
346
347 return 0;
348}
349
350static int ad7793_ring_postdisable(struct iio_dev *indio_dev)
351{
352 struct ad7793_state *st = iio_priv(indio_dev);
353
354 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
355 AD7793_MODE_SEL(AD7793_MODE_IDLE);
356
357 st->done = false;
358 wait_event_interruptible(st->wq_data_avail, st->done);
359
360 if (!st->irq_dis)
361 disable_irq_nosync(st->spi->irq);
362
363 __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
364 sizeof(st->mode), st->mode);
365
366 return spi_bus_unlock(st->spi->master);
367}
368
369/**
370 * ad7793_trigger_handler() bh of trigger launched polling to ring buffer
371 **/
372
373static irqreturn_t ad7793_trigger_handler(int irq, void *p)
374{
375 struct iio_poll_func *pf = p;
e65bc6ac 376 struct iio_dev *indio_dev = pf->indio_dev;
14555b14 377 struct iio_buffer *ring = indio_dev->buffer;
88bc3054
MH		 378 struct ad7793_state *st = iio_priv(indio_dev);
379 s64 dat64[2];
380 s32 *dat32 = (s32 *)dat64;
381
550268ca 382 if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
88bc3054
MH		 383 __ad7793_read_reg(st, 1, 1, AD7793_REG_DATA,
384 dat32,
385 indio_dev->channels[0].scan_type.realbits/8);
386
387 /* Guaranteed to be aligned with 8 byte boundary */
fd6487f8 388 if (indio_dev->scan_timestamp)
88bc3054
MH		 389 dat64[1] = pf->timestamp;
390
391 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
392
393 iio_trigger_notify_done(indio_dev->trig);
394 st->irq_dis = false;
395 enable_irq(st->spi->irq);
396
397 return IRQ_HANDLED;
398}
399
14555b14 400static const struct iio_buffer_setup_ops ad7793_ring_setup_ops = {
88bc3054 401 .preenable = &ad7793_ring_preenable,
3b99fb76
JC		 402 .postenable = &iio_triggered_buffer_postenable,
403 .predisable = &iio_triggered_buffer_predisable,
88bc3054 404 .postdisable = &ad7793_ring_postdisable,
8c2c6ba6 405 .validate_scan_mask = &iio_validate_scan_mask_onehot,
88bc3054
MH		 406};
407
408static int ad7793_register_ring_funcs_and_init(struct iio_dev *indio_dev)
409{
82796edc
LPC		 410 return iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
411 &ad7793_trigger_handler, &ad7793_ring_setup_ops);
88bc3054
MH		 412}
413
414static void ad7793_ring_cleanup(struct iio_dev *indio_dev)
415{
82796edc 416 iio_triggered_buffer_cleanup(indio_dev);
88bc3054
MH		 417}
418
419/**
420 * ad7793_data_rdy_trig_poll() the event handler for the data rdy trig
421 **/
422static irqreturn_t ad7793_data_rdy_trig_poll(int irq, void *private)
423{
424 struct ad7793_state *st = iio_priv(private);
425
426 st->done = true;
427 wake_up_interruptible(&st->wq_data_avail);
428 disable_irq_nosync(irq);
429 st->irq_dis = true;
430 iio_trigger_poll(st->trig, iio_get_time_ns());
431
432 return IRQ_HANDLED;
433}
434
8324e860
JC		 435static struct iio_trigger_ops ad7793_trigger_ops = {
436 .owner = THIS_MODULE,
437};
438
88bc3054
MH		 439static int ad7793_probe_trigger(struct iio_dev *indio_dev)
440{
441 struct ad7793_state *st = iio_priv(indio_dev);
442 int ret;
443
7cbb7537 444 st->trig = iio_trigger_alloc("%s-dev%d",
88bc3054
MH		 445 spi_get_device_id(st->spi)->name,
446 indio_dev->id);
447 if (st->trig == NULL) {
448 ret = -ENOMEM;
449 goto error_ret;
450 }
8324e860 451 st->trig->ops = &ad7793_trigger_ops;
88bc3054
MH		 452
453 ret = request_irq(st->spi->irq,
454 ad7793_data_rdy_trig_poll,
455 IRQF_TRIGGER_LOW,
456 spi_get_device_id(st->spi)->name,
457 indio_dev);
458 if (ret)
459 goto error_free_trig;
460
461 disable_irq_nosync(st->spi->irq);
462 st->irq_dis = true;
463 st->trig->dev.parent = &st->spi->dev;
88bc3054
MH		 464 st->trig->private_data = indio_dev;
465
466 ret = iio_trigger_register(st->trig);
467
468 /* select default trigger */
469 indio_dev->trig = st->trig;
470 if (ret)
471 goto error_free_irq;
472
473 return 0;
474
475error_free_irq:
476 free_irq(st->spi->irq, indio_dev);
477error_free_trig:
7cbb7537 478 iio_trigger_free(st->trig);
88bc3054
MH		 479error_ret:
480 return ret;
481}
482
483static void ad7793_remove_trigger(struct iio_dev *indio_dev)
484{
485 struct ad7793_state *st = iio_priv(indio_dev);
486
487 iio_trigger_unregister(st->trig);
488 free_irq(st->spi->irq, indio_dev);
7cbb7537 489 iio_trigger_free(st->trig);
88bc3054
MH		 490}
491
492static const u16 sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 33, 19,
493 17, 16, 12, 10, 8, 6, 4};
494
495static ssize_t ad7793_read_frequency(struct device *dev,
496 struct device_attribute *attr,
497 char *buf)
498{
62c51839 499 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
88bc3054
MH		 500 struct ad7793_state *st = iio_priv(indio_dev);
501
502 return sprintf(buf, "%d\n",
503 sample_freq_avail[AD7793_MODE_RATE(st->mode)]);
504}
505
506static ssize_t ad7793_write_frequency(struct device *dev,
507 struct device_attribute *attr,
508 const char *buf,
509 size_t len)
510{
62c51839 511 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
88bc3054
MH		 512 struct ad7793_state *st = iio_priv(indio_dev);
513 long lval;
514 int i, ret;
515
516 mutex_lock(&indio_dev->mlock);
14555b14 517 if (iio_buffer_enabled(indio_dev)) {
88bc3054
MH		 518 mutex_unlock(&indio_dev->mlock);
519 return -EBUSY;
520 }
521 mutex_unlock(&indio_dev->mlock);
522
523 ret = strict_strtol(buf, 10, &lval);
524 if (ret)
525 return ret;
526
527 ret = -EINVAL;
528
529 for (i = 0; i < ARRAY_SIZE(sample_freq_avail); i++)
530 if (lval == sample_freq_avail[i]) {
531 mutex_lock(&indio_dev->mlock);
532 st->mode &= ~AD7793_MODE_RATE(-1);
533 st->mode |= AD7793_MODE_RATE(i);
534 ad7793_write_reg(st, AD7793_REG_MODE,
535 sizeof(st->mode), st->mode);
536 mutex_unlock(&indio_dev->mlock);
537 ret = 0;
538 }
539
540 return ret ? ret : len;
541}
542
543static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
544 ad7793_read_frequency,
545 ad7793_write_frequency);
546
547static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
548 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
549
550static ssize_t ad7793_show_scale_available(struct device *dev,
551 struct device_attribute *attr, char *buf)
552{
62c51839 553 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
88bc3054
MH		 554 struct ad7793_state *st = iio_priv(indio_dev);
555 int i, len = 0;
556
557 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
558 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
559 st->scale_avail[i][1]);
560
561 len += sprintf(buf + len, "\n");
562
563 return len;
564}
565
08ca3b78
LPC		 566static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available,
567 in_voltage-voltage_scale_available, S_IRUGO,
568 ad7793_show_scale_available, NULL, 0);
88bc3054
MH		 569
570static struct attribute *ad7793_attributes[] = {
571 &iio_dev_attr_sampling_frequency.dev_attr.attr,
572 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
573 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
574 NULL
575};
576
577static const struct attribute_group ad7793_attribute_group = {
578 .attrs = ad7793_attributes,
579};
580
581static int ad7793_read_raw(struct iio_dev *indio_dev,
582 struct iio_chan_spec const *chan,
583 int *val,
584 int *val2,
585 long m)
586{
587 struct ad7793_state *st = iio_priv(indio_dev);
588 int ret, smpl = 0;
589 unsigned long long scale_uv;
590 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
591
592 switch (m) {
b11f98ff 593 case IIO_CHAN_INFO_RAW:
88bc3054 594 mutex_lock(&indio_dev->mlock);
14555b14 595 if (iio_buffer_enabled(indio_dev))
950935b1 596 ret = -EBUSY;
88bc3054
MH		 597 else
598 ret = ad7793_read(st, chan->address,
599 chan->scan_type.realbits / 8, &smpl);
600 mutex_unlock(&indio_dev->mlock);
601
602 if (ret < 0)
603 return ret;
604
605 *val = (smpl >> chan->scan_type.shift) &
606 ((1 << (chan->scan_type.realbits)) - 1);
607
88bc3054
MH		 608 return IIO_VAL_INT;
609
c8a9f805 610 case IIO_CHAN_INFO_SCALE:
88bc3054 611 switch (chan->type) {
6835cb6b 612 case IIO_VOLTAGE:
c8a9f805
JC		 613 if (chan->differential) {
614 *val = st->
615 scale_avail[(st->conf >> 8) & 0x7][0];
616 *val2 = st->
617 scale_avail[(st->conf >> 8) & 0x7][1];
618 return IIO_VAL_INT_PLUS_NANO;
619 } else {
620 /* 1170mV / 2^23 * 6 */
2a9e0662 621 scale_uv = (1170ULL * 100000000ULL * 6ULL);
c8a9f805 622 }
88bc3054
MH		 623 break;
624 case IIO_TEMP:
2a9e0662
LPC		 625 /* 1170mV / 0.81 mV/C / 2^23 */
626 scale_uv = 1444444444444ULL;
88bc3054
MH		 627 break;
628 default:
629 return -EINVAL;
630 }
631
2a9e0662
LPC		 632 scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1));
633 *val = 0;
634 *val2 = scale_uv;
88bc3054 635 return IIO_VAL_INT_PLUS_NANO;
680f8ea0
LPC		 636 case IIO_CHAN_INFO_OFFSET:
637 if (!unipolar)
2a9e0662 638 *val = -(1 << (chan->scan_type.realbits - 1));
680f8ea0
LPC		 639 else
640 *val = 0;
2a9e0662
LPC		 641
642 /* Kelvin to Celsius */
643 if (chan->type == IIO_TEMP) {
644 unsigned long long offset;
645 unsigned int shift;
646
647 shift = chan->scan_type.realbits - (unipolar ? 0 : 1);
648 offset = 273ULL << shift;
649 do_div(offset, 1444);
650 *val -= offset;
651 }
680f8ea0 652 return IIO_VAL_INT;
88bc3054
MH		 653 }
654 return -EINVAL;
655}
656
657static int ad7793_write_raw(struct iio_dev *indio_dev,
658 struct iio_chan_spec const *chan,
659 int val,
660 int val2,
661 long mask)
662{
663 struct ad7793_state *st = iio_priv(indio_dev);
664 int ret, i;
665 unsigned int tmp;
666
667 mutex_lock(&indio_dev->mlock);
14555b14 668 if (iio_buffer_enabled(indio_dev)) {
88bc3054
MH		 669 mutex_unlock(&indio_dev->mlock);
670 return -EBUSY;
671 }
672
673 switch (mask) {
c8a9f805 674 case IIO_CHAN_INFO_SCALE:
88bc3054
MH		 675 ret = -EINVAL;
676 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
677 if (val2 == st->scale_avail[i][1]) {
678 tmp = st->conf;
679 st->conf &= ~AD7793_CONF_GAIN(-1);
680 st->conf |= AD7793_CONF_GAIN(i);
681
682 if (tmp != st->conf) {
683 ad7793_write_reg(st, AD7793_REG_CONF,
684 sizeof(st->conf),
685 st->conf);
686 ad7793_calibrate_all(st);
687 }
688 ret = 0;
689 }
421afe58 690 break;
88bc3054
MH		 691 default:
692 ret = -EINVAL;
693 }
694
695 mutex_unlock(&indio_dev->mlock);
696 return ret;
697}
698
699static int ad7793_validate_trigger(struct iio_dev *indio_dev,
700 struct iio_trigger *trig)
701{
702 if (indio_dev->trig != trig)
703 return -EINVAL;
704
705 return 0;
706}
707
708static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
709 struct iio_chan_spec const *chan,
710 long mask)
711{
712 return IIO_VAL_INT_PLUS_NANO;
713}
714
715static const struct iio_info ad7793_info = {
716 .read_raw = &ad7793_read_raw,
717 .write_raw = &ad7793_write_raw,
718 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
719 .attrs = &ad7793_attribute_group,
720 .validate_trigger = ad7793_validate_trigger,
721 .driver_module = THIS_MODULE,
722};
723
724static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
725 [ID_AD7793] = {
ade7ef7b
JC		 726 .channel[0] = {
727 .type = IIO_VOLTAGE,
728 .differential = 1,
729 .indexed = 1,
730 .channel = 0,
731 .channel2 = 0,
732 .address = AD7793_CH_AIN1P_AIN1M,
b11f98ff 733 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
680f8ea0
LPC		 734 IIO_CHAN_INFO_SCALE_SHARED_BIT |
735 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
ade7ef7b 736 .scan_index = 0,
e8353909 737 .scan_type = IIO_ST('u', 24, 32, 0)
ade7ef7b
JC		 738 },
739 .channel[1] = {
740 .type = IIO_VOLTAGE,
741 .differential = 1,
742 .indexed = 1,
743 .channel = 1,
744 .channel2 = 1,
745 .address = AD7793_CH_AIN2P_AIN2M,
b11f98ff 746 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
680f8ea0
LPC		 747 IIO_CHAN_INFO_SCALE_SHARED_BIT |
748 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
ade7ef7b 749 .scan_index = 1,
e8353909 750 .scan_type = IIO_ST('u', 24, 32, 0)
ade7ef7b
JC		 751 },
752 .channel[2] = {
753 .type = IIO_VOLTAGE,
754 .differential = 1,
755 .indexed = 1,
756 .channel = 2,
757 .channel2 = 2,
758 .address = AD7793_CH_AIN3P_AIN3M,
b11f98ff 759 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
680f8ea0
LPC		 760 IIO_CHAN_INFO_SCALE_SHARED_BIT |
761 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
ade7ef7b 762 .scan_index = 2,
e8353909 763 .scan_type = IIO_ST('u', 24, 32, 0)
ade7ef7b
JC		 764 },
765 .channel[3] = {
766 .type = IIO_VOLTAGE,
767 .differential = 1,
768 .extend_name = "shorted",
769 .indexed = 1,
770 .channel = 2,
771 .channel2 = 2,
772 .address = AD7793_CH_AIN1M_AIN1M,
b11f98ff 773 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
680f8ea0
LPC		 774 IIO_CHAN_INFO_SCALE_SHARED_BIT |
775 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
05eda67d 776 .scan_index = 3,
e8353909 777 .scan_type = IIO_ST('u', 24, 32, 0)
ade7ef7b
JC		 778 },
779 .channel[4] = {
780 .type = IIO_TEMP,
781 .indexed = 1,
782 .channel = 0,
783 .address = AD7793_CH_TEMP,
b11f98ff
JC		 784 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
785 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
ade7ef7b 786 .scan_index = 4,
e8353909 787 .scan_type = IIO_ST('u', 24, 32, 0),
ade7ef7b
JC		 788 },
789 .channel[5] = {
790 .type = IIO_VOLTAGE,
791 .extend_name = "supply",
792 .indexed = 1,
793 .channel = 4,
794 .address = AD7793_CH_AVDD_MONITOR,
b11f98ff 795 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
680f8ea0
LPC		 796 IIO_CHAN_INFO_SCALE_SEPARATE_BIT |
797 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
ade7ef7b 798 .scan_index = 5,
e8353909 799 .scan_type = IIO_ST('u', 24, 32, 0),
ade7ef7b 800 },
88bc3054
MH		 801 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
802 },
803 [ID_AD7792] = {
ade7ef7b
JC		 804 .channel[0] = {
805 .type = IIO_VOLTAGE,
806 .differential = 1,
807 .indexed = 1,
808 .channel = 0,
809 .channel2 = 0,
810 .address = AD7793_CH_AIN1P_AIN1M,
b11f98ff 811 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
680f8ea0
LPC		 812 IIO_CHAN_INFO_SCALE_SHARED_BIT |
813 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
ade7ef7b 814 .scan_index = 0,
e8353909 815 .scan_type = IIO_ST('u', 16, 32, 0)
ade7ef7b
JC		 816 },
817 .channel[1] = {
818 .type = IIO_VOLTAGE,
819 .differential = 1,
820 .indexed = 1,
821 .channel = 1,
822 .channel2 = 1,
823 .address = AD7793_CH_AIN2P_AIN2M,
b11f98ff 824 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
680f8ea0
LPC		 825 IIO_CHAN_INFO_SCALE_SHARED_BIT |
826 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
ade7ef7b 827 .scan_index = 1,
e8353909 828 .scan_type = IIO_ST('u', 16, 32, 0)
ade7ef7b
JC		 829 },
830 .channel[2] = {
831 .type = IIO_VOLTAGE,
832 .differential = 1,
833 .indexed = 1,
834 .channel = 2,
835 .channel2 = 2,
836 .address = AD7793_CH_AIN3P_AIN3M,
b11f98ff 837 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
680f8ea0
LPC		 838 IIO_CHAN_INFO_SCALE_SHARED_BIT |
839 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
ade7ef7b 840 .scan_index = 2,
e8353909 841 .scan_type = IIO_ST('u', 16, 32, 0)
ade7ef7b
JC		 842 },
843 .channel[3] = {
844 .type = IIO_VOLTAGE,
845 .differential = 1,
846 .extend_name = "shorted",
847 .indexed = 1,
848 .channel = 2,
849 .channel2 = 2,
850 .address = AD7793_CH_AIN1M_AIN1M,
b11f98ff 851 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
680f8ea0
LPC		 852 IIO_CHAN_INFO_SCALE_SHARED_BIT |
853 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
05eda67d 854 .scan_index = 3,
e8353909 855 .scan_type = IIO_ST('u', 16, 32, 0)
ade7ef7b
JC		 856 },
857 .channel[4] = {
858 .type = IIO_TEMP,
859 .indexed = 1,
860 .channel = 0,
861 .address = AD7793_CH_TEMP,
b11f98ff
JC		 862 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
863 IIO_CHAN_INFO_SCALE_SEPARATE_BIT,
ade7ef7b 864 .scan_index = 4,
e8353909 865 .scan_type = IIO_ST('u', 16, 32, 0),
ade7ef7b
JC		 866 },
867 .channel[5] = {
868 .type = IIO_VOLTAGE,
869 .extend_name = "supply",
870 .indexed = 1,
871 .channel = 4,
872 .address = AD7793_CH_AVDD_MONITOR,
b11f98ff 873 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT |
680f8ea0
LPC		 874 IIO_CHAN_INFO_SCALE_SEPARATE_BIT |
875 IIO_CHAN_INFO_OFFSET_SHARED_BIT,
ade7ef7b 876 .scan_index = 5,
e8353909 877 .scan_type = IIO_ST('u', 16, 32, 0),
ade7ef7b 878 },
88bc3054
MH		 879 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
880 },
881};
882
883static int __devinit ad7793_probe(struct spi_device *spi)
884{
885 struct ad7793_platform_data *pdata = spi->dev.platform_data;
886 struct ad7793_state *st;
887 struct iio_dev *indio_dev;
8c2c6ba6 888 int ret, voltage_uv = 0;
88bc3054
MH		 889
890 if (!pdata) {
891 dev_err(&spi->dev, "no platform data?\n");
892 return -ENODEV;
893 }
894
895 if (!spi->irq) {
896 dev_err(&spi->dev, "no IRQ?\n");
897 return -ENODEV;
898 }
899
7cbb7537 900 indio_dev = iio_device_alloc(sizeof(*st));
88bc3054
MH		 901 if (indio_dev == NULL)
902 return -ENOMEM;
903
904 st = iio_priv(indio_dev);
905
906 st->reg = regulator_get(&spi->dev, "vcc");
907 if (!IS_ERR(st->reg)) {
908 ret = regulator_enable(st->reg);
909 if (ret)
910 goto error_put_reg;
911
912 voltage_uv = regulator_get_voltage(st->reg);
913 }
914
915 st->chip_info =
916 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
917
918 st->pdata = pdata;
919
920 if (pdata && pdata->vref_mv)
921 st->int_vref_mv = pdata->vref_mv;
922 else if (voltage_uv)
923 st->int_vref_mv = voltage_uv / 1000;
924 else
87a0c157 925 st->int_vref_mv = 1170; /* Build-in ref */
88bc3054
MH		 926
927 spi_set_drvdata(spi, indio_dev);
928 st->spi = spi;
929
930 indio_dev->dev.parent = &spi->dev;
931 indio_dev->name = spi_get_device_id(spi)->name;
932 indio_dev->modes = INDIO_DIRECT_MODE;
933 indio_dev->channels = st->chip_info->channel;
88bc3054
MH		 934 indio_dev->num_channels = 7;
935 indio_dev->info = &ad7793_info;
936
88bc3054
MH		 937 init_waitqueue_head(&st->wq_data_avail);
938
939 ret = ad7793_register_ring_funcs_and_init(indio_dev);
940 if (ret)
941 goto error_disable_reg;
942
88bc3054
MH		 943 ret = ad7793_probe_trigger(indio_dev);
944 if (ret)
945 goto error_unreg_ring;
946
88bc3054
MH		 947 ret = ad7793_setup(st);
948 if (ret)
82796edc 949 goto error_remove_trigger;
88bc3054 950
26d25ae3
JC		 951 ret = iio_device_register(indio_dev);
952 if (ret)
82796edc 953 goto error_remove_trigger;
26d25ae3 954
88bc3054
MH		 955 return 0;
956
88bc3054
MH		 957error_remove_trigger:
958 ad7793_remove_trigger(indio_dev);
959error_unreg_ring:
960 ad7793_ring_cleanup(indio_dev);
961error_disable_reg:
962 if (!IS_ERR(st->reg))
963 regulator_disable(st->reg);
964error_put_reg:
965 if (!IS_ERR(st->reg))
966 regulator_put(st->reg);
967
7cbb7537 968 iio_device_free(indio_dev);
88bc3054
MH		 969
970 return ret;
971}
972
973static int ad7793_remove(struct spi_device *spi)
974{
975 struct iio_dev *indio_dev = spi_get_drvdata(spi);
976 struct ad7793_state *st = iio_priv(indio_dev);
977
d2fffd6c 978 iio_device_unregister(indio_dev);
88bc3054
MH		 979 ad7793_remove_trigger(indio_dev);
980 ad7793_ring_cleanup(indio_dev);
981
982 if (!IS_ERR(st->reg)) {
983 regulator_disable(st->reg);
984 regulator_put(st->reg);
985 }
986
7cbb7537 987 iio_device_free(indio_dev);
88bc3054
MH		 988
989 return 0;
990}
991
992static const struct spi_device_id ad7793_id[] = {
993 {"ad7792", ID_AD7792},
994 {"ad7793", ID_AD7793},
995 {}
996};
55e4390c 997MODULE_DEVICE_TABLE(spi, ad7793_id);
88bc3054
MH		 998
999static struct spi_driver ad7793_driver = {
1000 .driver = {
1001 .name = "ad7793",
88bc3054
MH		 1002 .owner = THIS_MODULE,
1003 },
1004 .probe = ad7793_probe,
1005 .remove = __devexit_p(ad7793_remove),
1006 .id_table = ad7793_id,
1007};
ae6ae6fe 1008module_spi_driver(ad7793_driver);
88bc3054
MH		 1009
1010MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1011MODULE_DESCRIPTION("Analog Devices AD7792/3 ADC");
1012MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)