#define __NR_fadvise64 413
#endif
-#define nop do { } while (0)
-#define read_barrier() __asm__ __volatile__("mb": : :"memory")
+#define nop do { } while (0)
+#define read_barrier() __asm__ __volatile__("mb": : :"memory")
+#define writer_barrier() __asm__ __volatile__("wmb": : :"memory")
#endif
#define nop asm volatile ("hint @pause" ::: "memory");
#define read_barrier() asm volatile ("mf" ::: "memory")
+#define writebarrier() asm volatile ("mf" ::: "memory")
#define ia64_popcnt(x) \
({ \
#define nop do { } while (0)
#ifdef __powerpc64__
-#define read_barrier() \
- __asm__ __volatile__ ("lwsync" : : : "memory")
+#define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
#else
-#define read_barrier() \
- __asm__ __volatile__ ("sync" : : : "memory")
+#define read_barrier() __asm__ __volatile__ ("sync" : : : "memory")
#endif
+#define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
+
static inline int __ilog2(unsigned long bitmask)
{
int lz;
#define nop asm volatile ("diag 0,0,68" : : : "memory")
#define read_barrier() asm volatile("bcr 15,0" : : : "memory")
+#define write_barrier() asm volatile("bcr 15,0" : : : "memory")
#endif
#define nop do { } while (0)
#define read_barrier() __asm__ __volatile__ ("" : : : "memory")
+#define write_barrier() __asm__ __volatile__ ("" : : : "memory")
#endif
: : : "memory"); \
} while (0)
-#define read_barrier() \
- membar_safe("#LoadLoad")
+#define read_barrier() membar_safe("#LoadLoad")
+#define write_barrier() membar_safe("#StoreStore")
#endif
#define FIO_HAVE_SYSLET
#define nop __asm__ __volatile__("rep;nop": : :"memory")
-#define read_barrier() asm volatile ("": : :"memory")
+#define read_barrier() __asm__ __volatile__("": : :"memory")
+#define write_barrier() __asm__ __volatile__("": : :"memory")
static inline unsigned long arch_ffz(unsigned long bitmask)
{
#define FIO_HAVE_SYSLET
#define nop __asm__ __volatile__("rep;nop": : :"memory")
-#define read_barrier() asm volatile("lfence":::"memory")
+#define read_barrier() __asm__ __volatile__("lfence":::"memory")
+#define write_barrier() __asm__ __volatile__("sfence":::"memory")
static inline unsigned int arch_ffz(unsigned int bitmask)
{
* the ->aio_pending store is seen after the ->aio_events store
*/
sd->aio_events[sd->aio_pending] = io_u;
+ write_barrier();
sd->aio_pending++;
sd->nr--;
}
wait_for_event(&tv);
/*
- * Needs locking here for SIGIO
+ * should be OK without locking, as int operations should be atomic
*/
ret = sd->aio_pending;
- sd->aio_pending = 0;
+ sd->aio_pending -= ret;
return ret;
}
}
/*
- * Set USE_SIGNAL_COMPLETIONS to use SIGIO as completion events. Needs
- * locking around ->aio_pending and ->aio_events, see comment
+ * Set USE_SIGNAL_COMPLETIONS to use SIGIO as completion events.
*/
static void fio_solarisaio_init_sigio(void)
{