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net/mlx5e: Offload TC matching on ip ttl
[linux-2.6-block.git] / drivers / net / ethernet / mellanox / mlx5 / core / en_tc.c
CommitLineData
e8f887ac
AV		 1/*
2 * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
e3a2b7ed 33#include <net/flow_dissector.h>
3f7d0eb4 34#include <net/sch_generic.h>
e3a2b7ed
AV		 35#include <net/pkt_cls.h>
36#include <net/tc_act/tc_gact.h>
12185a9f 37#include <net/tc_act/tc_skbedit.h>
e8f887ac
AV		 38#include <linux/mlx5/fs.h>
39#include <linux/mlx5/device.h>
40#include <linux/rhashtable.h>
03a9d11e
OG		 41#include <net/switchdev.h>
42#include <net/tc_act/tc_mirred.h>
776b12b6 43#include <net/tc_act/tc_vlan.h>
bbd00f7e 44#include <net/tc_act/tc_tunnel_key.h>
d79b6df6 45#include <net/tc_act/tc_pedit.h>
26c02749 46#include <net/tc_act/tc_csum.h>
a54e20b4 47#include <net/vxlan.h>
f6dfb4c3 48#include <net/arp.h>
e8f887ac 49#include "en.h"
1d447a39 50#include "en_rep.h"
232c0013 51#include "en_tc.h"
03a9d11e 52#include "eswitch.h"
bbd00f7e 53#include "vxlan.h"
e8f887ac 54
3bc4b7bf
OG		 55struct mlx5_nic_flow_attr {
56 u32 action;
57 u32 flow_tag;
2f4fe4ca 58 u32 mod_hdr_id;
3bc4b7bf
OG		 59};
60
65ba8fb7
OG		 61enum {
62 MLX5E_TC_FLOW_ESWITCH = BIT(0),
3bc4b7bf 63 MLX5E_TC_FLOW_NIC = BIT(1),
0b67a38f 64 MLX5E_TC_FLOW_OFFLOADED = BIT(2),
65ba8fb7
OG		 65};
66
e8f887ac
AV		 67struct mlx5e_tc_flow {
68 struct rhash_head node;
69 u64 cookie;
65ba8fb7 70 u8 flags;
74491de9 71 struct mlx5_flow_handle *rule;
11c9c548
OG		 72 struct list_head encap; /* flows sharing the same encap ID */
73 struct list_head mod_hdr; /* flows sharing the same mod hdr ID */
3bc4b7bf
OG		 74 union {
75 struct mlx5_esw_flow_attr esw_attr[0];
76 struct mlx5_nic_flow_attr nic_attr[0];
77 };
e8f887ac
AV		 78};
79
17091853
OG		 80struct mlx5e_tc_flow_parse_attr {
81 struct mlx5_flow_spec spec;
d79b6df6
OG		 82 int num_mod_hdr_actions;
83 void *mod_hdr_actions;
17091853
OG		 84};
85
a54e20b4
HHZ		 86enum {
87 MLX5_HEADER_TYPE_VXLAN = 0x0,
88 MLX5_HEADER_TYPE_NVGRE = 0x1,
89};
90
acff797c
MG		 91#define MLX5E_TC_TABLE_NUM_ENTRIES 1024
92#define MLX5E_TC_TABLE_NUM_GROUPS 4
e8f887ac 93
11c9c548
OG		 94struct mod_hdr_key {
95 int num_actions;
96 void *actions;
97};
98
99struct mlx5e_mod_hdr_entry {
100 /* a node of a hash table which keeps all the mod_hdr entries */
101 struct hlist_node mod_hdr_hlist;
102
103 /* flows sharing the same mod_hdr entry */
104 struct list_head flows;
105
106 struct mod_hdr_key key;
107
108 u32 mod_hdr_id;
109};
110
111#define MLX5_MH_ACT_SZ MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto)
112
113static inline u32 hash_mod_hdr_info(struct mod_hdr_key *key)
114{
115 return jhash(key->actions,
116 key->num_actions * MLX5_MH_ACT_SZ, 0);
117}
118
119static inline int cmp_mod_hdr_info(struct mod_hdr_key *a,
120 struct mod_hdr_key *b)
121{
122 if (a->num_actions != b->num_actions)
123 return 1;
124
125 return memcmp(a->actions, b->actions, a->num_actions * MLX5_MH_ACT_SZ);
126}
127
128static int mlx5e_attach_mod_hdr(struct mlx5e_priv *priv,
129 struct mlx5e_tc_flow *flow,
130 struct mlx5e_tc_flow_parse_attr *parse_attr)
131{
132 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
133 int num_actions, actions_size, namespace, err;
134 struct mlx5e_mod_hdr_entry *mh;
135 struct mod_hdr_key key;
136 bool found = false;
137 u32 hash_key;
138
139 num_actions = parse_attr->num_mod_hdr_actions;
140 actions_size = MLX5_MH_ACT_SZ * num_actions;
141
142 key.actions = parse_attr->mod_hdr_actions;
143 key.num_actions = num_actions;
144
145 hash_key = hash_mod_hdr_info(&key);
146
147 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
148 namespace = MLX5_FLOW_NAMESPACE_FDB;
149 hash_for_each_possible(esw->offloads.mod_hdr_tbl, mh,
150 mod_hdr_hlist, hash_key) {
151 if (!cmp_mod_hdr_info(&mh->key, &key)) {
152 found = true;
153 break;
154 }
155 }
156 } else {
157 namespace = MLX5_FLOW_NAMESPACE_KERNEL;
158 hash_for_each_possible(priv->fs.tc.mod_hdr_tbl, mh,
159 mod_hdr_hlist, hash_key) {
160 if (!cmp_mod_hdr_info(&mh->key, &key)) {
161 found = true;
162 break;
163 }
164 }
165 }
166
167 if (found)
168 goto attach_flow;
169
170 mh = kzalloc(sizeof(*mh) + actions_size, GFP_KERNEL);
171 if (!mh)
172 return -ENOMEM;
173
174 mh->key.actions = (void *)mh + sizeof(*mh);
175 memcpy(mh->key.actions, key.actions, actions_size);
176 mh->key.num_actions = num_actions;
177 INIT_LIST_HEAD(&mh->flows);
178
179 err = mlx5_modify_header_alloc(priv->mdev, namespace,
180 mh->key.num_actions,
181 mh->key.actions,
182 &mh->mod_hdr_id);
183 if (err)
184 goto out_err;
185
186 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
187 hash_add(esw->offloads.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
188 else
189 hash_add(priv->fs.tc.mod_hdr_tbl, &mh->mod_hdr_hlist, hash_key);
190
191attach_flow:
192 list_add(&flow->mod_hdr, &mh->flows);
193 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
194 flow->esw_attr->mod_hdr_id = mh->mod_hdr_id;
195 else
196 flow->nic_attr->mod_hdr_id = mh->mod_hdr_id;
197
198 return 0;
199
200out_err:
201 kfree(mh);
202 return err;
203}
204
205static void mlx5e_detach_mod_hdr(struct mlx5e_priv *priv,
206 struct mlx5e_tc_flow *flow)
207{
208 struct list_head *next = flow->mod_hdr.next;
209
210 list_del(&flow->mod_hdr);
211
212 if (list_empty(next)) {
213 struct mlx5e_mod_hdr_entry *mh;
214
215 mh = list_entry(next, struct mlx5e_mod_hdr_entry, flows);
216
217 mlx5_modify_header_dealloc(priv->mdev, mh->mod_hdr_id);
218 hash_del(&mh->mod_hdr_hlist);
219 kfree(mh);
220 }
221}
222
74491de9
MB		 223static struct mlx5_flow_handle *
224mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
17091853 225 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 226 struct mlx5e_tc_flow *flow)
e8f887ac 227{
aa0cbbae 228 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
aad7e08d 229 struct mlx5_core_dev *dev = priv->mdev;
aa0cbbae 230 struct mlx5_flow_destination dest = {};
66958ed9 231 struct mlx5_flow_act flow_act = {
3bc4b7bf
OG		 232 .action = attr->action,
233 .flow_tag = attr->flow_tag,
66958ed9
HHZ		 234 .encap_id = 0,
235 };
aad7e08d 236 struct mlx5_fc *counter = NULL;
74491de9 237 struct mlx5_flow_handle *rule;
e8f887ac 238 bool table_created = false;
2f4fe4ca 239 int err;
e8f887ac 240
3bc4b7bf 241 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
aad7e08d
AV		 242 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
243 dest.ft = priv->fs.vlan.ft.t;
3bc4b7bf 244 } else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
aad7e08d
AV		 245 counter = mlx5_fc_create(dev, true);
246 if (IS_ERR(counter))
247 return ERR_CAST(counter);
248
249 dest.type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
250 dest.counter = counter;
251 }
252
2f4fe4ca 253 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
3099eb5a 254 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32 255 flow_act.modify_id = attr->mod_hdr_id;
2f4fe4ca
OG		 256 kfree(parse_attr->mod_hdr_actions);
257 if (err) {
258 rule = ERR_PTR(err);
259 goto err_create_mod_hdr_id;
260 }
261 }
262
acff797c
MG		 263 if (IS_ERR_OR_NULL(priv->fs.tc.t)) {
264 priv->fs.tc.t =
265 mlx5_create_auto_grouped_flow_table(priv->fs.ns,
266 MLX5E_TC_PRIO,
267 MLX5E_TC_TABLE_NUM_ENTRIES,
268 MLX5E_TC_TABLE_NUM_GROUPS,
c9f1b073 269 0, 0);
acff797c 270 if (IS_ERR(priv->fs.tc.t)) {
e8f887ac
AV		 271 netdev_err(priv->netdev,
272 "Failed to create tc offload table\n");
aad7e08d
AV		 273 rule = ERR_CAST(priv->fs.tc.t);
274 goto err_create_ft;
e8f887ac
AV		 275 }
276
277 table_created = true;
278 }
279
17091853
OG		 280 parse_attr->spec.match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
281 rule = mlx5_add_flow_rules(priv->fs.tc.t, &parse_attr->spec,
282 &flow_act, &dest, 1);
aad7e08d
AV		 283
284 if (IS_ERR(rule))
285 goto err_add_rule;
286
287 return rule;
e8f887ac 288
aad7e08d
AV		 289err_add_rule:
290 if (table_created) {
acff797c
MG		 291 mlx5_destroy_flow_table(priv->fs.tc.t);
292 priv->fs.tc.t = NULL;
e8f887ac 293 }
aad7e08d 294err_create_ft:
2f4fe4ca 295 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 296 mlx5e_detach_mod_hdr(priv, flow);
2f4fe4ca 297err_create_mod_hdr_id:
aad7e08d 298 mlx5_fc_destroy(dev, counter);
e8f887ac
AV		 299
300 return rule;
301}
302
d85cdccb
OG		 303static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
304 struct mlx5e_tc_flow *flow)
305{
513f8f7f 306 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
d85cdccb
OG		 307 struct mlx5_fc *counter = NULL;
308
aa0cbbae
OG		 309 counter = mlx5_flow_rule_counter(flow->rule);
310 mlx5_del_flow_rules(flow->rule);
311 mlx5_fc_destroy(priv->mdev, counter);
d85cdccb
OG		 312
313 if (!mlx5e_tc_num_filters(priv) && (priv->fs.tc.t)) {
314 mlx5_destroy_flow_table(priv->fs.tc.t);
315 priv->fs.tc.t = NULL;
316 }
2f4fe4ca 317
513f8f7f 318 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
3099eb5a 319 mlx5e_detach_mod_hdr(priv, flow);
d85cdccb
OG		 320}
321
aa0cbbae
OG		 322static void mlx5e_detach_encap(struct mlx5e_priv *priv,
323 struct mlx5e_tc_flow *flow);
324
74491de9
MB		 325static struct mlx5_flow_handle *
326mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
17091853 327 struct mlx5e_tc_flow_parse_attr *parse_attr,
aa0cbbae 328 struct mlx5e_tc_flow *flow)
adb4c123
OG		 329{
330 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
aa0cbbae
OG		 331 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
332 struct mlx5_flow_handle *rule;
8b32580d
OG		 333 int err;
334
335 err = mlx5_eswitch_add_vlan_action(esw, attr);
aa0cbbae
OG		 336 if (err) {
337 rule = ERR_PTR(err);
338 goto err_add_vlan;
339 }
adb4c123 340
d7e75a32 341 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1a9527bb 342 err = mlx5e_attach_mod_hdr(priv, flow, parse_attr);
d7e75a32
OG		 343 kfree(parse_attr->mod_hdr_actions);
344 if (err) {
345 rule = ERR_PTR(err);
346 goto err_mod_hdr;
347 }
348 }
349
aa0cbbae
OG		 350 rule = mlx5_eswitch_add_offloaded_rule(esw, &parse_attr->spec, attr);
351 if (IS_ERR(rule))
352 goto err_add_rule;
adb4c123 353
aa0cbbae
OG		 354 return rule;
355
356err_add_rule:
513f8f7f 357 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 358 mlx5e_detach_mod_hdr(priv, flow);
d7e75a32 359err_mod_hdr:
aa0cbbae
OG		 360 mlx5_eswitch_del_vlan_action(esw, attr);
361err_add_vlan:
362 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP)
363 mlx5e_detach_encap(priv, flow);
aa0cbbae
OG		 364 return rule;
365}
d85cdccb
OG		 366
367static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
368 struct mlx5e_tc_flow *flow)
369{
370 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
d7e75a32 371 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
d85cdccb 372
232c0013
HHZ		 373 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
374 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
513f8f7f 375 mlx5_eswitch_del_offloaded_rule(esw, flow->rule, attr);
232c0013 376 }
d85cdccb 377
513f8f7f 378 mlx5_eswitch_del_vlan_action(esw, attr);
d85cdccb 379
513f8f7f 380 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP) {
d85cdccb 381 mlx5e_detach_encap(priv, flow);
513f8f7f 382 kvfree(attr->parse_attr);
232c0013 383 }
d7e75a32 384
513f8f7f 385 if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1a9527bb 386 mlx5e_detach_mod_hdr(priv, flow);
d85cdccb
OG		 387}
388
232c0013
HHZ		 389void mlx5e_tc_encap_flows_add(struct mlx5e_priv *priv,
390 struct mlx5e_encap_entry *e)
391{
392 struct mlx5e_tc_flow *flow;
393 int err;
394
395 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
396 e->encap_size, e->encap_header,
397 &e->encap_id);
398 if (err) {
399 mlx5_core_warn(priv->mdev, "Failed to offload cached encapsulation header, %d\n",
400 err);
401 return;
402 }
403 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 404 mlx5e_rep_queue_neigh_stats_work(priv);
232c0013
HHZ		 405
406 list_for_each_entry(flow, &e->flows, encap) {
407 flow->esw_attr->encap_id = e->encap_id;
408 flow->rule = mlx5e_tc_add_fdb_flow(priv,
409 flow->esw_attr->parse_attr,
410 flow);
411 if (IS_ERR(flow->rule)) {
412 err = PTR_ERR(flow->rule);
413 mlx5_core_warn(priv->mdev, "Failed to update cached encapsulation flow, %d\n",
414 err);
415 continue;
416 }
417 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
418 }
419}
420
421void mlx5e_tc_encap_flows_del(struct mlx5e_priv *priv,
422 struct mlx5e_encap_entry *e)
423{
424 struct mlx5e_tc_flow *flow;
425 struct mlx5_fc *counter;
426
427 list_for_each_entry(flow, &e->flows, encap) {
428 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
429 flow->flags &= ~MLX5E_TC_FLOW_OFFLOADED;
430 counter = mlx5_flow_rule_counter(flow->rule);
431 mlx5_del_flow_rules(flow->rule);
432 mlx5_fc_destroy(priv->mdev, counter);
433 }
434 }
435
436 if (e->flags & MLX5_ENCAP_ENTRY_VALID) {
437 e->flags &= ~MLX5_ENCAP_ENTRY_VALID;
438 mlx5_encap_dealloc(priv->mdev, e->encap_id);
439 }
440}
441
f6dfb4c3
HHZ		 442void mlx5e_tc_update_neigh_used_value(struct mlx5e_neigh_hash_entry *nhe)
443{
444 struct mlx5e_neigh *m_neigh = &nhe->m_neigh;
445 u64 bytes, packets, lastuse = 0;
446 struct mlx5e_tc_flow *flow;
447 struct mlx5e_encap_entry *e;
448 struct mlx5_fc *counter;
449 struct neigh_table *tbl;
450 bool neigh_used = false;
451 struct neighbour *n;
452
453 if (m_neigh->family == AF_INET)
454 tbl = &arp_tbl;
455#if IS_ENABLED(CONFIG_IPV6)
456 else if (m_neigh->family == AF_INET6)
457 tbl = ipv6_stub->nd_tbl;
458#endif
459 else
460 return;
461
462 list_for_each_entry(e, &nhe->encap_list, encap_list) {
463 if (!(e->flags & MLX5_ENCAP_ENTRY_VALID))
464 continue;
465 list_for_each_entry(flow, &e->flows, encap) {
466 if (flow->flags & MLX5E_TC_FLOW_OFFLOADED) {
467 counter = mlx5_flow_rule_counter(flow->rule);
468 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
469 if (time_after((unsigned long)lastuse, nhe->reported_lastuse)) {
470 neigh_used = true;
471 break;
472 }
473 }
474 }
475 }
476
477 if (neigh_used) {
478 nhe->reported_lastuse = jiffies;
479
480 /* find the relevant neigh according to the cached device and
481 * dst ip pair
482 */
483 n = neigh_lookup(tbl, &m_neigh->dst_ip, m_neigh->dev);
484 if (!n) {
485 WARN(1, "The neighbour already freed\n");
486 return;
487 }
488
489 neigh_event_send(n, NULL);
490 neigh_release(n);
491 }
492}
493
d85cdccb
OG		 494static void mlx5e_detach_encap(struct mlx5e_priv *priv,
495 struct mlx5e_tc_flow *flow)
496{
5067b602
RD		 497 struct list_head *next = flow->encap.next;
498
499 list_del(&flow->encap);
500 if (list_empty(next)) {
c1ae1152 501 struct mlx5e_encap_entry *e;
5067b602 502
c1ae1152 503 e = list_entry(next, struct mlx5e_encap_entry, flows);
232c0013
HHZ		 504 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
505
506 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
5067b602 507 mlx5_encap_dealloc(priv->mdev, e->encap_id);
232c0013 508
cdc5a7f3 509 hash_del_rcu(&e->encap_hlist);
232c0013 510 kfree(e->encap_header);
5067b602
RD		 511 kfree(e);
512 }
513}
514
e8f887ac 515static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
961e8979 516 struct mlx5e_tc_flow *flow)
e8f887ac 517{
d85cdccb
OG		 518 if (flow->flags & MLX5E_TC_FLOW_ESWITCH)
519 mlx5e_tc_del_fdb_flow(priv, flow);
520 else
521 mlx5e_tc_del_nic_flow(priv, flow);
e8f887ac
AV		 522}
523
bbd00f7e
HHZ		 524static void parse_vxlan_attr(struct mlx5_flow_spec *spec,
525 struct tc_cls_flower_offload *f)
526{
527 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
528 outer_headers);
529 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
530 outer_headers);
531 void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
532 misc_parameters);
533 void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
534 misc_parameters);
535
536 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_protocol);
537 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, IPPROTO_UDP);
538
539 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
540 struct flow_dissector_key_keyid *key =
541 skb_flow_dissector_target(f->dissector,
542 FLOW_DISSECTOR_KEY_ENC_KEYID,
543 f->key);
544 struct flow_dissector_key_keyid *mask =
545 skb_flow_dissector_target(f->dissector,
546 FLOW_DISSECTOR_KEY_ENC_KEYID,
547 f->mask);
548 MLX5_SET(fte_match_set_misc, misc_c, vxlan_vni,
549 be32_to_cpu(mask->keyid));
550 MLX5_SET(fte_match_set_misc, misc_v, vxlan_vni,
551 be32_to_cpu(key->keyid));
552 }
553}
554
555static int parse_tunnel_attr(struct mlx5e_priv *priv,
556 struct mlx5_flow_spec *spec,
557 struct tc_cls_flower_offload *f)
558{
559 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
560 outer_headers);
561 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
562 outer_headers);
563
2e72eb43
OG		 564 struct flow_dissector_key_control *enc_control =
565 skb_flow_dissector_target(f->dissector,
566 FLOW_DISSECTOR_KEY_ENC_CONTROL,
567 f->key);
568
bbd00f7e
HHZ		 569 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) {
570 struct flow_dissector_key_ports *key =
571 skb_flow_dissector_target(f->dissector,
572 FLOW_DISSECTOR_KEY_ENC_PORTS,
573 f->key);
574 struct flow_dissector_key_ports *mask =
575 skb_flow_dissector_target(f->dissector,
576 FLOW_DISSECTOR_KEY_ENC_PORTS,
577 f->mask);
1ad9a00a
PB		 578 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
579 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
580 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
bbd00f7e
HHZ		 581
582 /* Full udp dst port must be given */
583 if (memchr_inv(&mask->dst, 0xff, sizeof(mask->dst)))
2fcd82e9 584 goto vxlan_match_offload_err;
bbd00f7e 585
1ad9a00a 586 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->dst)) &&
bbd00f7e
HHZ		 587 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap))
588 parse_vxlan_attr(spec, f);
2fcd82e9
OG		 589 else {
590 netdev_warn(priv->netdev,
591 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->dst));
bbd00f7e 592 return -EOPNOTSUPP;
2fcd82e9 593 }
bbd00f7e
HHZ		 594
595 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
596 udp_dport, ntohs(mask->dst));
597 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
598 udp_dport, ntohs(key->dst));
599
cd377663
OG		 600 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
601 udp_sport, ntohs(mask->src));
602 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
603 udp_sport, ntohs(key->src));
bbd00f7e 604 } else { /* udp dst port must be given */
2fcd82e9
OG		 605vxlan_match_offload_err:
606 netdev_warn(priv->netdev,
607 "IP tunnel decap offload supported only for vxlan, must set UDP dport\n");
608 return -EOPNOTSUPP;
bbd00f7e
HHZ		 609 }
610
2e72eb43 611 if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
bbd00f7e
HHZ		 612 struct flow_dissector_key_ipv4_addrs *key =
613 skb_flow_dissector_target(f->dissector,
614 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
615 f->key);
616 struct flow_dissector_key_ipv4_addrs *mask =
617 skb_flow_dissector_target(f->dissector,
618 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
619 f->mask);
620 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
621 src_ipv4_src_ipv6.ipv4_layout.ipv4,
622 ntohl(mask->src));
623 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
624 src_ipv4_src_ipv6.ipv4_layout.ipv4,
625 ntohl(key->src));
626
627 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
628 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
629 ntohl(mask->dst));
630 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
631 dst_ipv4_dst_ipv6.ipv4_layout.ipv4,
632 ntohl(key->dst));
bbd00f7e 633
2e72eb43
OG		 634 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
635 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IP);
19f44401
OG		 636 } else if (enc_control->addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
637 struct flow_dissector_key_ipv6_addrs *key =
638 skb_flow_dissector_target(f->dissector,
639 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
640 f->key);
641 struct flow_dissector_key_ipv6_addrs *mask =
642 skb_flow_dissector_target(f->dissector,
643 FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
644 f->mask);
645
646 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
647 src_ipv4_src_ipv6.ipv6_layout.ipv6),
648 &mask->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
649 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
650 src_ipv4_src_ipv6.ipv6_layout.ipv6),
651 &key->src, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
652
653 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
654 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
655 &mask->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
656 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
657 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
658 &key->dst, MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6));
659
660 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ethertype);
661 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype, ETH_P_IPV6);
2e72eb43 662 }
bbd00f7e
HHZ		 663
664 /* Enforce DMAC when offloading incoming tunneled flows.
665 * Flow counters require a match on the DMAC.
666 */
667 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_47_16);
668 MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, dmac_15_0);
669 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
670 dmac_47_16), priv->netdev->dev_addr);
671
672 /* let software handle IP fragments */
673 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
674 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag, 0);
675
676 return 0;
677}
678
de0af0bf
RD		 679static int __parse_cls_flower(struct mlx5e_priv *priv,
680 struct mlx5_flow_spec *spec,
681 struct tc_cls_flower_offload *f,
682 u8 *min_inline)
e3a2b7ed 683{
c5bb1730
MG		 684 void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
685 outer_headers);
686 void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
687 outer_headers);
e3a2b7ed
AV		 688 u16 addr_type = 0;
689 u8 ip_proto = 0;
690
de0af0bf
RD		 691 *min_inline = MLX5_INLINE_MODE_L2;
692
e3a2b7ed
AV		 693 if (f->dissector->used_keys &
694 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
695 BIT(FLOW_DISSECTOR_KEY_BASIC) |
696 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
095b6cfd 697 BIT(FLOW_DISSECTOR_KEY_VLAN) |
e3a2b7ed
AV		 698 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
699 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
bbd00f7e
HHZ		 700 BIT(FLOW_DISSECTOR_KEY_PORTS) |
701 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID) |
702 BIT(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
703 BIT(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
704 BIT(FLOW_DISSECTOR_KEY_ENC_PORTS) |
e77834ec 705 BIT(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
fd7da28b
OG		 706 BIT(FLOW_DISSECTOR_KEY_TCP) |
707 BIT(FLOW_DISSECTOR_KEY_IP))) {
e3a2b7ed
AV		 708 netdev_warn(priv->netdev, "Unsupported key used: 0x%x\n",
709 f->dissector->used_keys);
710 return -EOPNOTSUPP;
711 }
712
bbd00f7e
HHZ		 713 if ((dissector_uses_key(f->dissector,
714 FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) ||
715 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID) ||
716 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_PORTS)) &&
717 dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_CONTROL)) {
718 struct flow_dissector_key_control *key =
719 skb_flow_dissector_target(f->dissector,
720 FLOW_DISSECTOR_KEY_ENC_CONTROL,
721 f->key);
722 switch (key->addr_type) {
723 case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
19f44401 724 case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
bbd00f7e
HHZ		 725 if (parse_tunnel_attr(priv, spec, f))
726 return -EOPNOTSUPP;
727 break;
728 default:
729 return -EOPNOTSUPP;
730 }
731
732 /* In decap flow, header pointers should point to the inner
733 * headers, outer header were already set by parse_tunnel_attr
734 */
735 headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
736 inner_headers);
737 headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
738 inner_headers);
739 }
740
e3a2b7ed
AV		 741 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
742 struct flow_dissector_key_control *key =
743 skb_flow_dissector_target(f->dissector,
1dbd0d37 744 FLOW_DISSECTOR_KEY_CONTROL,
e3a2b7ed 745 f->key);
3f7d0eb4
OG		 746
747 struct flow_dissector_key_control *mask =
748 skb_flow_dissector_target(f->dissector,
749 FLOW_DISSECTOR_KEY_CONTROL,
750 f->mask);
e3a2b7ed 751 addr_type = key->addr_type;
3f7d0eb4
OG		 752
753 if (mask->flags & FLOW_DIS_IS_FRAGMENT) {
754 MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
755 MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
756 key->flags & FLOW_DIS_IS_FRAGMENT);
0827444d
OG		 757
758 /* the HW doesn't need L3 inline to match on frag=no */
759 if (key->flags & FLOW_DIS_IS_FRAGMENT)
760 *min_inline = MLX5_INLINE_MODE_IP;
3f7d0eb4 761 }
e3a2b7ed
AV		 762 }
763
764 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
765 struct flow_dissector_key_basic *key =
766 skb_flow_dissector_target(f->dissector,
767 FLOW_DISSECTOR_KEY_BASIC,
768 f->key);
769 struct flow_dissector_key_basic *mask =
770 skb_flow_dissector_target(f->dissector,
771 FLOW_DISSECTOR_KEY_BASIC,
772 f->mask);
773 ip_proto = key->ip_proto;
774
775 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
776 ntohs(mask->n_proto));
777 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
778 ntohs(key->n_proto));
779
780 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
781 mask->ip_proto);
782 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
783 key->ip_proto);
de0af0bf
RD		 784
785 if (mask->ip_proto)
786 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 787 }
788
789 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
790 struct flow_dissector_key_eth_addrs *key =
791 skb_flow_dissector_target(f->dissector,
792 FLOW_DISSECTOR_KEY_ETH_ADDRS,
793 f->key);
794 struct flow_dissector_key_eth_addrs *mask =
795 skb_flow_dissector_target(f->dissector,
796 FLOW_DISSECTOR_KEY_ETH_ADDRS,
797 f->mask);
798
799 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
800 dmac_47_16),
801 mask->dst);
802 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
803 dmac_47_16),
804 key->dst);
805
806 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
807 smac_47_16),
808 mask->src);
809 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
810 smac_47_16),
811 key->src);
812 }
813
095b6cfd
OG		 814 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
815 struct flow_dissector_key_vlan *key =
816 skb_flow_dissector_target(f->dissector,
817 FLOW_DISSECTOR_KEY_VLAN,
818 f->key);
819 struct flow_dissector_key_vlan *mask =
820 skb_flow_dissector_target(f->dissector,
821 FLOW_DISSECTOR_KEY_VLAN,
822 f->mask);
358d79a4 823 if (mask->vlan_id || mask->vlan_priority) {
10543365
MHY		 824 MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
825 MLX5_SET(fte_match_set_lyr_2_4, headers_v, cvlan_tag, 1);
095b6cfd
OG		 826
827 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid, mask->vlan_id);
828 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid, key->vlan_id);
358d79a4
OG		 829
830 MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio, mask->vlan_priority);
831 MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio, key->vlan_priority);
095b6cfd
OG		 832 }
833 }
834
e3a2b7ed
AV		 835 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
836 struct flow_dissector_key_ipv4_addrs *key =
837 skb_flow_dissector_target(f->dissector,
838 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
839 f->key);
840 struct flow_dissector_key_ipv4_addrs *mask =
841 skb_flow_dissector_target(f->dissector,
842 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
843 f->mask);
844
845 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
846 src_ipv4_src_ipv6.ipv4_layout.ipv4),
847 &mask->src, sizeof(mask->src));
848 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
849 src_ipv4_src_ipv6.ipv4_layout.ipv4),
850 &key->src, sizeof(key->src));
851 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
852 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
853 &mask->dst, sizeof(mask->dst));
854 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
855 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
856 &key->dst, sizeof(key->dst));
de0af0bf
RD		 857
858 if (mask->src || mask->dst)
859 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 860 }
861
862 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
863 struct flow_dissector_key_ipv6_addrs *key =
864 skb_flow_dissector_target(f->dissector,
865 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
866 f->key);
867 struct flow_dissector_key_ipv6_addrs *mask =
868 skb_flow_dissector_target(f->dissector,
869 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
870 f->mask);
871
872 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
873 src_ipv4_src_ipv6.ipv6_layout.ipv6),
874 &mask->src, sizeof(mask->src));
875 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
876 src_ipv4_src_ipv6.ipv6_layout.ipv6),
877 &key->src, sizeof(key->src));
878
879 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
880 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
881 &mask->dst, sizeof(mask->dst));
882 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
883 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
884 &key->dst, sizeof(key->dst));
de0af0bf
RD		 885
886 if (ipv6_addr_type(&mask->src) != IPV6_ADDR_ANY ||
887 ipv6_addr_type(&mask->dst) != IPV6_ADDR_ANY)
888 *min_inline = MLX5_INLINE_MODE_IP;
e3a2b7ed
AV		 889 }
890
1f97a526
OG		 891 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_IP)) {
892 struct flow_dissector_key_ip *key =
893 skb_flow_dissector_target(f->dissector,
894 FLOW_DISSECTOR_KEY_IP,
895 f->key);
896 struct flow_dissector_key_ip *mask =
897 skb_flow_dissector_target(f->dissector,
898 FLOW_DISSECTOR_KEY_IP,
899 f->mask);
900
901 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn, mask->tos & 0x3);
902 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn, key->tos & 0x3);
903
904 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp, mask->tos >> 2);
905 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp, key->tos >> 2);
906
a8ade55f
OG		 907 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit, mask->ttl);
908 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit, key->ttl);
1f97a526 909
a8ade55f
OG		 910 if (mask->ttl &&
911 !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
912 ft_field_support.outer_ipv4_ttl))
1f97a526 913 return -EOPNOTSUPP;
a8ade55f
OG		 914
915 if (mask->tos || mask->ttl)
916 *min_inline = MLX5_INLINE_MODE_IP;
1f97a526
OG		 917 }
918
e3a2b7ed
AV		 919 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
920 struct flow_dissector_key_ports *key =
921 skb_flow_dissector_target(f->dissector,
922 FLOW_DISSECTOR_KEY_PORTS,
923 f->key);
924 struct flow_dissector_key_ports *mask =
925 skb_flow_dissector_target(f->dissector,
926 FLOW_DISSECTOR_KEY_PORTS,
927 f->mask);
928 switch (ip_proto) {
929 case IPPROTO_TCP:
930 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
931 tcp_sport, ntohs(mask->src));
932 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
933 tcp_sport, ntohs(key->src));
934
935 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
936 tcp_dport, ntohs(mask->dst));
937 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
938 tcp_dport, ntohs(key->dst));
939 break;
940
941 case IPPROTO_UDP:
942 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
943 udp_sport, ntohs(mask->src));
944 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
945 udp_sport, ntohs(key->src));
946
947 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
948 udp_dport, ntohs(mask->dst));
949 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
950 udp_dport, ntohs(key->dst));
951 break;
952 default:
953 netdev_err(priv->netdev,
954 "Only UDP and TCP transport are supported\n");
955 return -EINVAL;
956 }
de0af0bf
RD		 957
958 if (mask->src || mask->dst)
959 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
e3a2b7ed
AV		 960 }
961
e77834ec
OG		 962 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_TCP)) {
963 struct flow_dissector_key_tcp *key =
964 skb_flow_dissector_target(f->dissector,
965 FLOW_DISSECTOR_KEY_TCP,
966 f->key);
967 struct flow_dissector_key_tcp *mask =
968 skb_flow_dissector_target(f->dissector,
969 FLOW_DISSECTOR_KEY_TCP,
970 f->mask);
971
972 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
973 ntohs(mask->flags));
974 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
975 ntohs(key->flags));
976
977 if (mask->flags)
978 *min_inline = MLX5_INLINE_MODE_TCP_UDP;
979 }
980
e3a2b7ed
AV		 981 return 0;
982}
983
de0af0bf 984static int parse_cls_flower(struct mlx5e_priv *priv,
65ba8fb7 985 struct mlx5e_tc_flow *flow,
de0af0bf
RD		 986 struct mlx5_flow_spec *spec,
987 struct tc_cls_flower_offload *f)
988{
989 struct mlx5_core_dev *dev = priv->mdev;
990 struct mlx5_eswitch *esw = dev->priv.eswitch;
1d447a39
SM		 991 struct mlx5e_rep_priv *rpriv = priv->ppriv;
992 struct mlx5_eswitch_rep *rep;
de0af0bf
RD		 993 u8 min_inline;
994 int err;
995
996 err = __parse_cls_flower(priv, spec, f, &min_inline);
997
1d447a39
SM		 998 if (!err && (flow->flags & MLX5E_TC_FLOW_ESWITCH)) {
999 rep = rpriv->rep;
1000 if (rep->vport != FDB_UPLINK_VPORT &&
1001 (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
1002 esw->offloads.inline_mode < min_inline)) {
de0af0bf
RD		 1003 netdev_warn(priv->netdev,
1004 "Flow is not offloaded due to min inline setting, required %d actual %d\n",
1005 min_inline, esw->offloads.inline_mode);
1006 return -EOPNOTSUPP;
1007 }
1008 }
1009
1010 return err;
1011}
1012
d79b6df6
OG		 1013struct pedit_headers {
1014 struct ethhdr eth;
1015 struct iphdr ip4;
1016 struct ipv6hdr ip6;
1017 struct tcphdr tcp;
1018 struct udphdr udp;
1019};
1020
1021static int pedit_header_offsets[] = {
1022 [TCA_PEDIT_KEY_EX_HDR_TYPE_ETH] = offsetof(struct pedit_headers, eth),
1023 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP4] = offsetof(struct pedit_headers, ip4),
1024 [TCA_PEDIT_KEY_EX_HDR_TYPE_IP6] = offsetof(struct pedit_headers, ip6),
1025 [TCA_PEDIT_KEY_EX_HDR_TYPE_TCP] = offsetof(struct pedit_headers, tcp),
1026 [TCA_PEDIT_KEY_EX_HDR_TYPE_UDP] = offsetof(struct pedit_headers, udp),
1027};
1028
1029#define pedit_header(_ph, _htype) ((void *)(_ph) + pedit_header_offsets[_htype])
1030
1031static int set_pedit_val(u8 hdr_type, u32 mask, u32 val, u32 offset,
1032 struct pedit_headers *masks,
1033 struct pedit_headers *vals)
1034{
1035 u32 *curr_pmask, *curr_pval;
1036
1037 if (hdr_type >= __PEDIT_HDR_TYPE_MAX)
1038 goto out_err;
1039
1040 curr_pmask = (u32 *)(pedit_header(masks, hdr_type) + offset);
1041 curr_pval = (u32 *)(pedit_header(vals, hdr_type) + offset);
1042
1043 if (*curr_pmask & mask) /* disallow acting twice on the same location */
1044 goto out_err;
1045
1046 *curr_pmask |= mask;
1047 *curr_pval |= (val & mask);
1048
1049 return 0;
1050
1051out_err:
1052 return -EOPNOTSUPP;
1053}
1054
1055struct mlx5_fields {
1056 u8 field;
1057 u8 size;
1058 u32 offset;
1059};
1060
1061static struct mlx5_fields fields[] = {
1062 {MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_dest[0])},
1063 {MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_dest[4])},
1064 {MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16, 4, offsetof(struct pedit_headers, eth.h_source[0])},
1065 {MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0, 2, offsetof(struct pedit_headers, eth.h_source[4])},
1066 {MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE, 2, offsetof(struct pedit_headers, eth.h_proto)},
1067
d79b6df6
OG		 1068 {MLX5_ACTION_IN_FIELD_OUT_IP_TTL, 1, offsetof(struct pedit_headers, ip4.ttl)},
1069 {MLX5_ACTION_IN_FIELD_OUT_SIPV4, 4, offsetof(struct pedit_headers, ip4.saddr)},
1070 {MLX5_ACTION_IN_FIELD_OUT_DIPV4, 4, offsetof(struct pedit_headers, ip4.daddr)},
1071
1072 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[0])},
1073 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[1])},
1074 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[2])},
1075 {MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.saddr.s6_addr32[3])},
1076 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[0])},
1077 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[1])},
1078 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[2])},
1079 {MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0, 4, offsetof(struct pedit_headers, ip6.daddr.s6_addr32[3])},
1080
1081 {MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT, 2, offsetof(struct pedit_headers, tcp.source)},
1082 {MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT, 2, offsetof(struct pedit_headers, tcp.dest)},
1083 {MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS, 1, offsetof(struct pedit_headers, tcp.ack_seq) + 5},
1084
1085 {MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT, 2, offsetof(struct pedit_headers, udp.source)},
1086 {MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT, 2, offsetof(struct pedit_headers, udp.dest)},
1087};
1088
1089/* On input attr->num_mod_hdr_actions tells how many HW actions can be parsed at
1090 * max from the SW pedit action. On success, it says how many HW actions were
1091 * actually parsed.
1092 */
1093static int offload_pedit_fields(struct pedit_headers *masks,
1094 struct pedit_headers *vals,
1095 struct mlx5e_tc_flow_parse_attr *parse_attr)
1096{
1097 struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
2b64beba 1098 int i, action_size, nactions, max_actions, first, last, next_z;
d79b6df6 1099 void *s_masks_p, *a_masks_p, *vals_p;
d79b6df6
OG		 1100 struct mlx5_fields *f;
1101 u8 cmd, field_bsize;
e3ca4e05 1102 u32 s_mask, a_mask;
d79b6df6 1103 unsigned long mask;
2b64beba
OG		 1104 __be32 mask_be32;
1105 __be16 mask_be16;
d79b6df6
OG		 1106 void *action;
1107
1108 set_masks = &masks[TCA_PEDIT_KEY_EX_CMD_SET];
1109 add_masks = &masks[TCA_PEDIT_KEY_EX_CMD_ADD];
1110 set_vals = &vals[TCA_PEDIT_KEY_EX_CMD_SET];
1111 add_vals = &vals[TCA_PEDIT_KEY_EX_CMD_ADD];
1112
1113 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1114 action = parse_attr->mod_hdr_actions;
1115 max_actions = parse_attr->num_mod_hdr_actions;
1116 nactions = 0;
1117
1118 for (i = 0; i < ARRAY_SIZE(fields); i++) {
1119 f = &fields[i];
1120 /* avoid seeing bits set from previous iterations */
e3ca4e05
OG		 1121 s_mask = 0;
1122 a_mask = 0;
d79b6df6
OG		 1123
1124 s_masks_p = (void *)set_masks + f->offset;
1125 a_masks_p = (void *)add_masks + f->offset;
1126
1127 memcpy(&s_mask, s_masks_p, f->size);
1128 memcpy(&a_mask, a_masks_p, f->size);
1129
1130 if (!s_mask && !a_mask) /* nothing to offload here */
1131 continue;
1132
1133 if (s_mask && a_mask) {
1134 printk(KERN_WARNING "mlx5: can't set and add to the same HW field (%x)\n", f->field);
1135 return -EOPNOTSUPP;
1136 }
1137
1138 if (nactions == max_actions) {
1139 printk(KERN_WARNING "mlx5: parsed %d pedit actions, can't do more\n", nactions);
1140 return -EOPNOTSUPP;
1141 }
1142
1143 if (s_mask) {
1144 cmd = MLX5_ACTION_TYPE_SET;
1145 mask = s_mask;
1146 vals_p = (void *)set_vals + f->offset;
1147 /* clear to denote we consumed this field */
1148 memset(s_masks_p, 0, f->size);
1149 } else {
1150 cmd = MLX5_ACTION_TYPE_ADD;
1151 mask = a_mask;
1152 vals_p = (void *)add_vals + f->offset;
1153 /* clear to denote we consumed this field */
1154 memset(a_masks_p, 0, f->size);
1155 }
1156
d79b6df6 1157 field_bsize = f->size * BITS_PER_BYTE;
e3ca4e05 1158
2b64beba
OG		 1159 if (field_bsize == 32) {
1160 mask_be32 = *(__be32 *)&mask;
1161 mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
1162 } else if (field_bsize == 16) {
1163 mask_be16 = *(__be16 *)&mask;
1164 mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
1165 }
1166
d79b6df6 1167 first = find_first_bit(&mask, field_bsize);
2b64beba 1168 next_z = find_next_zero_bit(&mask, field_bsize, first);
d79b6df6 1169 last = find_last_bit(&mask, field_bsize);
2b64beba
OG		 1170 if (first < next_z && next_z < last) {
1171 printk(KERN_WARNING "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
d79b6df6
OG		 1172 mask);
1173 return -EOPNOTSUPP;
1174 }
1175
1176 MLX5_SET(set_action_in, action, action_type, cmd);
1177 MLX5_SET(set_action_in, action, field, f->field);
1178
1179 if (cmd == MLX5_ACTION_TYPE_SET) {
2b64beba 1180 MLX5_SET(set_action_in, action, offset, first);
d79b6df6 1181 /* length is num of bits to be written, zero means length of 32 */
2b64beba 1182 MLX5_SET(set_action_in, action, length, (last - first + 1));
d79b6df6
OG		 1183 }
1184
1185 if (field_bsize == 32)
2b64beba 1186 MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
d79b6df6 1187 else if (field_bsize == 16)
2b64beba 1188 MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
d79b6df6 1189 else if (field_bsize == 8)
2b64beba 1190 MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
d79b6df6
OG		 1191
1192 action += action_size;
1193 nactions++;
1194 }
1195
1196 parse_attr->num_mod_hdr_actions = nactions;
1197 return 0;
1198}
1199
1200static int alloc_mod_hdr_actions(struct mlx5e_priv *priv,
1201 const struct tc_action *a, int namespace,
1202 struct mlx5e_tc_flow_parse_attr *parse_attr)
1203{
1204 int nkeys, action_size, max_actions;
1205
1206 nkeys = tcf_pedit_nkeys(a);
1207 action_size = MLX5_UN_SZ_BYTES(set_action_in_add_action_in_auto);
1208
1209 if (namespace == MLX5_FLOW_NAMESPACE_FDB) /* FDB offloading */
1210 max_actions = MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev, max_modify_header_actions);
1211 else /* namespace is MLX5_FLOW_NAMESPACE_KERNEL - NIC offloading */
1212 max_actions = MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, max_modify_header_actions);
1213
1214 /* can get up to crazingly 16 HW actions in 32 bits pedit SW key */
1215 max_actions = min(max_actions, nkeys * 16);
1216
1217 parse_attr->mod_hdr_actions = kcalloc(max_actions, action_size, GFP_KERNEL);
1218 if (!parse_attr->mod_hdr_actions)
1219 return -ENOMEM;
1220
1221 parse_attr->num_mod_hdr_actions = max_actions;
1222 return 0;
1223}
1224
1225static const struct pedit_headers zero_masks = {};
1226
1227static int parse_tc_pedit_action(struct mlx5e_priv *priv,
1228 const struct tc_action *a, int namespace,
1229 struct mlx5e_tc_flow_parse_attr *parse_attr)
1230{
1231 struct pedit_headers masks[__PEDIT_CMD_MAX], vals[__PEDIT_CMD_MAX], *cmd_masks;
1232 int nkeys, i, err = -EOPNOTSUPP;
1233 u32 mask, val, offset;
1234 u8 cmd, htype;
1235
1236 nkeys = tcf_pedit_nkeys(a);
1237
1238 memset(masks, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1239 memset(vals, 0, sizeof(struct pedit_headers) * __PEDIT_CMD_MAX);
1240
1241 for (i = 0; i < nkeys; i++) {
1242 htype = tcf_pedit_htype(a, i);
1243 cmd = tcf_pedit_cmd(a, i);
1244 err = -EOPNOTSUPP; /* can't be all optimistic */
1245
1246 if (htype == TCA_PEDIT_KEY_EX_HDR_TYPE_NETWORK) {
1247 printk(KERN_WARNING "mlx5: legacy pedit isn't offloaded\n");
1248 goto out_err;
1249 }
1250
1251 if (cmd != TCA_PEDIT_KEY_EX_CMD_SET && cmd != TCA_PEDIT_KEY_EX_CMD_ADD) {
1252 printk(KERN_WARNING "mlx5: pedit cmd %d isn't offloaded\n", cmd);
1253 goto out_err;
1254 }
1255
1256 mask = tcf_pedit_mask(a, i);
1257 val = tcf_pedit_val(a, i);
1258 offset = tcf_pedit_offset(a, i);
1259
1260 err = set_pedit_val(htype, ~mask, val, offset, &masks[cmd], &vals[cmd]);
1261 if (err)
1262 goto out_err;
1263 }
1264
1265 err = alloc_mod_hdr_actions(priv, a, namespace, parse_attr);
1266 if (err)
1267 goto out_err;
1268
1269 err = offload_pedit_fields(masks, vals, parse_attr);
1270 if (err < 0)
1271 goto out_dealloc_parsed_actions;
1272
1273 for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
1274 cmd_masks = &masks[cmd];
1275 if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
1276 printk(KERN_WARNING "mlx5: attempt to offload an unsupported field (cmd %d)\n",
1277 cmd);
1278 print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
1279 16, 1, cmd_masks, sizeof(zero_masks), true);
1280 err = -EOPNOTSUPP;
1281 goto out_dealloc_parsed_actions;
1282 }
1283 }
1284
1285 return 0;
1286
1287out_dealloc_parsed_actions:
1288 kfree(parse_attr->mod_hdr_actions);
1289out_err:
1290 return err;
1291}
1292
26c02749
OG		 1293static bool csum_offload_supported(struct mlx5e_priv *priv, u32 action, u32 update_flags)
1294{
1295 u32 prot_flags = TCA_CSUM_UPDATE_FLAG_IPV4HDR | TCA_CSUM_UPDATE_FLAG_TCP |
1296 TCA_CSUM_UPDATE_FLAG_UDP;
1297
1298 /* The HW recalcs checksums only if re-writing headers */
1299 if (!(action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)) {
1300 netdev_warn(priv->netdev,
1301 "TC csum action is only offloaded with pedit\n");
1302 return false;
1303 }
1304
1305 if (update_flags & ~prot_flags) {
1306 netdev_warn(priv->netdev,
1307 "can't offload TC csum action for some header/s - flags %#x\n",
1308 update_flags);
1309 return false;
1310 }
1311
1312 return true;
1313}
1314
5c40348c 1315static int parse_tc_nic_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
aa0cbbae
OG		 1316 struct mlx5e_tc_flow_parse_attr *parse_attr,
1317 struct mlx5e_tc_flow *flow)
e3a2b7ed 1318{
aa0cbbae 1319 struct mlx5_nic_flow_attr *attr = flow->nic_attr;
e3a2b7ed 1320 const struct tc_action *a;
22dc13c8 1321 LIST_HEAD(actions);
2f4fe4ca 1322 int err;
e3a2b7ed
AV		 1323
1324 if (tc_no_actions(exts))
1325 return -EINVAL;
1326
3bc4b7bf
OG		 1327 attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
1328 attr->action = 0;
e3a2b7ed 1329
22dc13c8
WC		 1330 tcf_exts_to_list(exts, &actions);
1331 list_for_each_entry(a, &actions, list) {
e3a2b7ed 1332 if (is_tcf_gact_shot(a)) {
3bc4b7bf 1333 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
aad7e08d
AV		 1334 if (MLX5_CAP_FLOWTABLE(priv->mdev,
1335 flow_table_properties_nic_receive.flow_counter))
3bc4b7bf 1336 attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
e3a2b7ed
AV		 1337 continue;
1338 }
1339
2f4fe4ca
OG		 1340 if (is_tcf_pedit(a)) {
1341 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_KERNEL,
1342 parse_attr);
1343 if (err)
1344 return err;
1345
1346 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR |
1347 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1348 continue;
1349 }
1350
26c02749
OG		 1351 if (is_tcf_csum(a)) {
1352 if (csum_offload_supported(priv, attr->action,
1353 tcf_csum_update_flags(a)))
1354 continue;
1355
1356 return -EOPNOTSUPP;
1357 }
1358
e3a2b7ed
AV		 1359 if (is_tcf_skbedit_mark(a)) {
1360 u32 mark = tcf_skbedit_mark(a);
1361
1362 if (mark & ~MLX5E_TC_FLOW_ID_MASK) {
1363 netdev_warn(priv->netdev, "Bad flow mark - only 16 bit is supported: 0x%x\n",
1364 mark);
1365 return -EINVAL;
1366 }
1367
3bc4b7bf
OG		 1368 attr->flow_tag = mark;
1369 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
e3a2b7ed
AV		 1370 continue;
1371 }
1372
1373 return -EINVAL;
1374 }
1375
1376 return 0;
1377}
1378
76f7444d
OG		 1379static inline int cmp_encap_info(struct ip_tunnel_key *a,
1380 struct ip_tunnel_key *b)
a54e20b4
HHZ		 1381{
1382 return memcmp(a, b, sizeof(*a));
1383}
1384
76f7444d 1385static inline int hash_encap_info(struct ip_tunnel_key *key)
a54e20b4 1386{
76f7444d 1387 return jhash(key, sizeof(*key), 0);
a54e20b4
HHZ		 1388}
1389
1390static int mlx5e_route_lookup_ipv4(struct mlx5e_priv *priv,
1391 struct net_device *mirred_dev,
1392 struct net_device **out_dev,
1393 struct flowi4 *fl4,
1394 struct neighbour **out_n,
a54e20b4
HHZ		 1395 int *out_ttl)
1396{
3e621b19 1397 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
a54e20b4
HHZ		 1398 struct rtable *rt;
1399 struct neighbour *n = NULL;
a54e20b4
HHZ		 1400
1401#if IS_ENABLED(CONFIG_INET)
abeffce9
AB		 1402 int ret;
1403
a54e20b4 1404 rt = ip_route_output_key(dev_net(mirred_dev), fl4);
abeffce9
AB		 1405 ret = PTR_ERR_OR_ZERO(rt);
1406 if (ret)
1407 return ret;
a54e20b4
HHZ		 1408#else
1409 return -EOPNOTSUPP;
1410#endif
3e621b19
HHZ		 1411 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1412 if (!switchdev_port_same_parent_id(priv->netdev, rt->dst.dev))
1413 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1414 else
1415 *out_dev = rt->dst.dev;
a54e20b4 1416
75c33da8 1417 *out_ttl = ip4_dst_hoplimit(&rt->dst);
a54e20b4
HHZ		 1418 n = dst_neigh_lookup(&rt->dst, &fl4->daddr);
1419 ip_rt_put(rt);
1420 if (!n)
1421 return -ENOMEM;
1422
1423 *out_n = n;
a54e20b4
HHZ		 1424 return 0;
1425}
1426
ce99f6b9
OG		 1427static int mlx5e_route_lookup_ipv6(struct mlx5e_priv *priv,
1428 struct net_device *mirred_dev,
1429 struct net_device **out_dev,
1430 struct flowi6 *fl6,
1431 struct neighbour **out_n,
1432 int *out_ttl)
1433{
1434 struct neighbour *n = NULL;
1435 struct dst_entry *dst;
1436
1437#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
1438 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1439 int ret;
1440
1441 dst = ip6_route_output(dev_net(mirred_dev), NULL, fl6);
321fa4ff
AB		 1442 ret = dst->error;
1443 if (ret) {
ce99f6b9
OG		 1444 dst_release(dst);
1445 return ret;
1446 }
1447
1448 *out_ttl = ip6_dst_hoplimit(dst);
1449
1450 /* if the egress device isn't on the same HW e-switch, we use the uplink */
1451 if (!switchdev_port_same_parent_id(priv->netdev, dst->dev))
1452 *out_dev = mlx5_eswitch_get_uplink_netdev(esw);
1453 else
1454 *out_dev = dst->dev;
1455#else
1456 return -EOPNOTSUPP;
1457#endif
1458
1459 n = dst_neigh_lookup(dst, &fl6->daddr);
1460 dst_release(dst);
1461 if (!n)
1462 return -ENOMEM;
1463
1464 *out_n = n;
1465 return 0;
1466}
1467
32f3671f
OG		 1468static void gen_vxlan_header_ipv4(struct net_device *out_dev,
1469 char buf[], int encap_size,
1470 unsigned char h_dest[ETH_ALEN],
1471 int ttl,
1472 __be32 daddr,
1473 __be32 saddr,
1474 __be16 udp_dst_port,
1475 __be32 vx_vni)
a54e20b4 1476{
a54e20b4
HHZ		 1477 struct ethhdr *eth = (struct ethhdr *)buf;
1478 struct iphdr *ip = (struct iphdr *)((char *)eth + sizeof(struct ethhdr));
1479 struct udphdr *udp = (struct udphdr *)((char *)ip + sizeof(struct iphdr));
1480 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1481
1482 memset(buf, 0, encap_size);
1483
1484 ether_addr_copy(eth->h_dest, h_dest);
1485 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1486 eth->h_proto = htons(ETH_P_IP);
1487
1488 ip->daddr = daddr;
1489 ip->saddr = saddr;
1490
1491 ip->ttl = ttl;
1492 ip->protocol = IPPROTO_UDP;
1493 ip->version = 0x4;
1494 ip->ihl = 0x5;
1495
1496 udp->dest = udp_dst_port;
1497 vxh->vx_flags = VXLAN_HF_VNI;
1498 vxh->vx_vni = vxlan_vni_field(vx_vni);
a54e20b4
HHZ		 1499}
1500
225aabaf
OG		 1501static void gen_vxlan_header_ipv6(struct net_device *out_dev,
1502 char buf[], int encap_size,
1503 unsigned char h_dest[ETH_ALEN],
1504 int ttl,
1505 struct in6_addr *daddr,
1506 struct in6_addr *saddr,
1507 __be16 udp_dst_port,
1508 __be32 vx_vni)
ce99f6b9 1509{
ce99f6b9
OG		 1510 struct ethhdr *eth = (struct ethhdr *)buf;
1511 struct ipv6hdr *ip6h = (struct ipv6hdr *)((char *)eth + sizeof(struct ethhdr));
1512 struct udphdr *udp = (struct udphdr *)((char *)ip6h + sizeof(struct ipv6hdr));
1513 struct vxlanhdr *vxh = (struct vxlanhdr *)((char *)udp + sizeof(struct udphdr));
1514
1515 memset(buf, 0, encap_size);
1516
1517 ether_addr_copy(eth->h_dest, h_dest);
1518 ether_addr_copy(eth->h_source, out_dev->dev_addr);
1519 eth->h_proto = htons(ETH_P_IPV6);
1520
1521 ip6_flow_hdr(ip6h, 0, 0);
1522 /* the HW fills up ipv6 payload len */
1523 ip6h->nexthdr = IPPROTO_UDP;
1524 ip6h->hop_limit = ttl;
1525 ip6h->daddr = *daddr;
1526 ip6h->saddr = *saddr;
1527
1528 udp->dest = udp_dst_port;
1529 vxh->vx_flags = VXLAN_HF_VNI;
1530 vxh->vx_vni = vxlan_vni_field(vx_vni);
ce99f6b9
OG		 1531}
1532
a54e20b4
HHZ		 1533static int mlx5e_create_encap_header_ipv4(struct mlx5e_priv *priv,
1534 struct net_device *mirred_dev,
1a8552bd 1535 struct mlx5e_encap_entry *e)
a54e20b4
HHZ		 1536{
1537 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
32f3671f 1538 int ipv4_encap_size = ETH_HLEN + sizeof(struct iphdr) + VXLAN_HLEN;
76f7444d 1539 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1540 struct net_device *out_dev;
a42485eb 1541 struct neighbour *n = NULL;
a54e20b4 1542 struct flowi4 fl4 = {};
a54e20b4 1543 char *encap_header;
32f3671f 1544 int ttl, err;
033354d5 1545 u8 nud_state;
32f3671f
OG		 1546
1547 if (max_encap_size < ipv4_encap_size) {
1548 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1549 ipv4_encap_size, max_encap_size);
1550 return -EOPNOTSUPP;
1551 }
a54e20b4 1552
32f3671f 1553 encap_header = kzalloc(ipv4_encap_size, GFP_KERNEL);
a54e20b4
HHZ		 1554 if (!encap_header)
1555 return -ENOMEM;
1556
1557 switch (e->tunnel_type) {
1558 case MLX5_HEADER_TYPE_VXLAN:
1559 fl4.flowi4_proto = IPPROTO_UDP;
76f7444d 1560 fl4.fl4_dport = tun_key->tp_dst;
a54e20b4
HHZ		 1561 break;
1562 default:
1563 err = -EOPNOTSUPP;
1564 goto out;
1565 }
9a941117 1566 fl4.flowi4_tos = tun_key->tos;
76f7444d 1567 fl4.daddr = tun_key->u.ipv4.dst;
9a941117 1568 fl4.saddr = tun_key->u.ipv4.src;
a54e20b4 1569
1a8552bd 1570 err = mlx5e_route_lookup_ipv4(priv, mirred_dev, &out_dev,
9a941117 1571 &fl4, &n, &ttl);
a54e20b4
HHZ		 1572 if (err)
1573 goto out;
1574
232c0013
HHZ		 1575 /* used by mlx5e_detach_encap to lookup a neigh hash table
1576 * entry in the neigh hash table when a user deletes a rule
1577 */
1578 e->m_neigh.dev = n->dev;
f6dfb4c3 1579 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 1580 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1581 e->out_dev = out_dev;
1582
1583 /* It's importent to add the neigh to the hash table before checking
1584 * the neigh validity state. So if we'll get a notification, in case the
1585 * neigh changes it's validity state, we would find the relevant neigh
1586 * in the hash.
1587 */
1588 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1589 if (err)
1590 goto out;
1591
033354d5
HHZ		 1592 read_lock_bh(&n->lock);
1593 nud_state = n->nud_state;
1594 ether_addr_copy(e->h_dest, n->ha);
1595 read_unlock_bh(&n->lock);
1596
a54e20b4
HHZ		 1597 switch (e->tunnel_type) {
1598 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1599 gen_vxlan_header_ipv4(out_dev, encap_header,
32f3671f
OG		 1600 ipv4_encap_size, e->h_dest, ttl,
1601 fl4.daddr,
1602 fl4.saddr, tun_key->tp_dst,
1603 tunnel_id_to_key32(tun_key->tun_id));
a54e20b4
HHZ		 1604 break;
1605 default:
1606 err = -EOPNOTSUPP;
232c0013
HHZ		 1607 goto destroy_neigh_entry;
1608 }
1609 e->encap_size = ipv4_encap_size;
1610 e->encap_header = encap_header;
1611
1612 if (!(nud_state & NUD_VALID)) {
1613 neigh_event_send(n, NULL);
27902f08
WY		 1614 err = -EAGAIN;
1615 goto out;
a54e20b4
HHZ		 1616 }
1617
1618 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
32f3671f 1619 ipv4_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 1620 if (err)
1621 goto destroy_neigh_entry;
1622
1623 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1624 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 1625 neigh_release(n);
1626 return err;
1627
1628destroy_neigh_entry:
1629 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
a54e20b4
HHZ		 1630out:
1631 kfree(encap_header);
232c0013
HHZ		 1632 if (n)
1633 neigh_release(n);
a54e20b4
HHZ		 1634 return err;
1635}
1636
ce99f6b9
OG		 1637static int mlx5e_create_encap_header_ipv6(struct mlx5e_priv *priv,
1638 struct net_device *mirred_dev,
1a8552bd 1639 struct mlx5e_encap_entry *e)
ce99f6b9
OG		 1640{
1641 int max_encap_size = MLX5_CAP_ESW(priv->mdev, max_encap_header_size);
225aabaf 1642 int ipv6_encap_size = ETH_HLEN + sizeof(struct ipv6hdr) + VXLAN_HLEN;
ce99f6b9 1643 struct ip_tunnel_key *tun_key = &e->tun_info.key;
1a8552bd 1644 struct net_device *out_dev;
ce99f6b9
OG		 1645 struct neighbour *n = NULL;
1646 struct flowi6 fl6 = {};
1647 char *encap_header;
225aabaf 1648 int err, ttl = 0;
033354d5 1649 u8 nud_state;
ce99f6b9 1650
225aabaf
OG		 1651 if (max_encap_size < ipv6_encap_size) {
1652 mlx5_core_warn(priv->mdev, "encap size %d too big, max supported is %d\n",
1653 ipv6_encap_size, max_encap_size);
1654 return -EOPNOTSUPP;
1655 }
ce99f6b9 1656
225aabaf 1657 encap_header = kzalloc(ipv6_encap_size, GFP_KERNEL);
ce99f6b9
OG		 1658 if (!encap_header)
1659 return -ENOMEM;
1660
1661 switch (e->tunnel_type) {
1662 case MLX5_HEADER_TYPE_VXLAN:
1663 fl6.flowi6_proto = IPPROTO_UDP;
1664 fl6.fl6_dport = tun_key->tp_dst;
1665 break;
1666 default:
1667 err = -EOPNOTSUPP;
1668 goto out;
1669 }
1670
1671 fl6.flowlabel = ip6_make_flowinfo(RT_TOS(tun_key->tos), tun_key->label);
1672 fl6.daddr = tun_key->u.ipv6.dst;
1673 fl6.saddr = tun_key->u.ipv6.src;
1674
1a8552bd 1675 err = mlx5e_route_lookup_ipv6(priv, mirred_dev, &out_dev,
ce99f6b9
OG		 1676 &fl6, &n, &ttl);
1677 if (err)
1678 goto out;
1679
232c0013
HHZ		 1680 /* used by mlx5e_detach_encap to lookup a neigh hash table
1681 * entry in the neigh hash table when a user deletes a rule
1682 */
1683 e->m_neigh.dev = n->dev;
f6dfb4c3 1684 e->m_neigh.family = n->ops->family;
232c0013
HHZ		 1685 memcpy(&e->m_neigh.dst_ip, n->primary_key, n->tbl->key_len);
1686 e->out_dev = out_dev;
1687
1688 /* It's importent to add the neigh to the hash table before checking
1689 * the neigh validity state. So if we'll get a notification, in case the
1690 * neigh changes it's validity state, we would find the relevant neigh
1691 * in the hash.
1692 */
1693 err = mlx5e_rep_encap_entry_attach(netdev_priv(out_dev), e);
1694 if (err)
1695 goto out;
1696
033354d5
HHZ		 1697 read_lock_bh(&n->lock);
1698 nud_state = n->nud_state;
1699 ether_addr_copy(e->h_dest, n->ha);
1700 read_unlock_bh(&n->lock);
1701
ce99f6b9
OG		 1702 switch (e->tunnel_type) {
1703 case MLX5_HEADER_TYPE_VXLAN:
1a8552bd 1704 gen_vxlan_header_ipv6(out_dev, encap_header,
225aabaf
OG		 1705 ipv6_encap_size, e->h_dest, ttl,
1706 &fl6.daddr,
1707 &fl6.saddr, tun_key->tp_dst,
1708 tunnel_id_to_key32(tun_key->tun_id));
ce99f6b9
OG		 1709 break;
1710 default:
1711 err = -EOPNOTSUPP;
232c0013
HHZ		 1712 goto destroy_neigh_entry;
1713 }
1714
1715 e->encap_size = ipv6_encap_size;
1716 e->encap_header = encap_header;
1717
1718 if (!(nud_state & NUD_VALID)) {
1719 neigh_event_send(n, NULL);
27902f08
WY		 1720 err = -EAGAIN;
1721 goto out;
ce99f6b9
OG		 1722 }
1723
1724 err = mlx5_encap_alloc(priv->mdev, e->tunnel_type,
225aabaf 1725 ipv6_encap_size, encap_header, &e->encap_id);
232c0013
HHZ		 1726 if (err)
1727 goto destroy_neigh_entry;
1728
1729 e->flags |= MLX5_ENCAP_ENTRY_VALID;
f6dfb4c3 1730 mlx5e_rep_queue_neigh_stats_work(netdev_priv(out_dev));
232c0013
HHZ		 1731 neigh_release(n);
1732 return err;
1733
1734destroy_neigh_entry:
1735 mlx5e_rep_encap_entry_detach(netdev_priv(e->out_dev), e);
ce99f6b9 1736out:
ce99f6b9 1737 kfree(encap_header);
232c0013
HHZ		 1738 if (n)
1739 neigh_release(n);
ce99f6b9
OG		 1740 return err;
1741}
1742
a54e20b4
HHZ		 1743static int mlx5e_attach_encap(struct mlx5e_priv *priv,
1744 struct ip_tunnel_info *tun_info,
1745 struct net_device *mirred_dev,
45247bf2
OG		 1746 struct net_device **encap_dev,
1747 struct mlx5e_tc_flow *flow)
a54e20b4
HHZ		 1748{
1749 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1ad9a00a 1750 struct net_device *up_dev = mlx5_eswitch_get_uplink_netdev(esw);
a54e20b4 1751 unsigned short family = ip_tunnel_info_af(tun_info);
45247bf2
OG		 1752 struct mlx5e_priv *up_priv = netdev_priv(up_dev);
1753 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
a54e20b4 1754 struct ip_tunnel_key *key = &tun_info->key;
c1ae1152 1755 struct mlx5e_encap_entry *e;
45247bf2 1756 int tunnel_type, err = 0;
a54e20b4
HHZ		 1757 uintptr_t hash_key;
1758 bool found = false;
a54e20b4 1759
2fcd82e9 1760 /* udp dst port must be set */
a54e20b4 1761 if (!memchr_inv(&key->tp_dst, 0, sizeof(key->tp_dst)))
2fcd82e9 1762 goto vxlan_encap_offload_err;
a54e20b4 1763
cd377663 1764 /* setting udp src port isn't supported */
2fcd82e9
OG		 1765 if (memchr_inv(&key->tp_src, 0, sizeof(key->tp_src))) {
1766vxlan_encap_offload_err:
1767 netdev_warn(priv->netdev,
1768 "must set udp dst port and not set udp src port\n");
cd377663 1769 return -EOPNOTSUPP;
2fcd82e9 1770 }
cd377663 1771
1ad9a00a 1772 if (mlx5e_vxlan_lookup_port(up_priv, be16_to_cpu(key->tp_dst)) &&
a54e20b4 1773 MLX5_CAP_ESW(priv->mdev, vxlan_encap_decap)) {
a54e20b4
HHZ		 1774 tunnel_type = MLX5_HEADER_TYPE_VXLAN;
1775 } else {
2fcd82e9
OG		 1776 netdev_warn(priv->netdev,
1777 "%d isn't an offloaded vxlan udp dport\n", be16_to_cpu(key->tp_dst));
a54e20b4
HHZ		 1778 return -EOPNOTSUPP;
1779 }
1780
76f7444d 1781 hash_key = hash_encap_info(key);
a54e20b4
HHZ		 1782
1783 hash_for_each_possible_rcu(esw->offloads.encap_tbl, e,
1784 encap_hlist, hash_key) {
76f7444d 1785 if (!cmp_encap_info(&e->tun_info.key, key)) {
a54e20b4
HHZ		 1786 found = true;
1787 break;
1788 }
1789 }
1790
45247bf2
OG		 1791 if (found)
1792 goto attach_flow;
a54e20b4
HHZ		 1793
1794 e = kzalloc(sizeof(*e), GFP_KERNEL);
1795 if (!e)
1796 return -ENOMEM;
1797
76f7444d 1798 e->tun_info = *tun_info;
a54e20b4
HHZ		 1799 e->tunnel_type = tunnel_type;
1800 INIT_LIST_HEAD(&e->flows);
1801
ce99f6b9 1802 if (family == AF_INET)
1a8552bd 1803 err = mlx5e_create_encap_header_ipv4(priv, mirred_dev, e);
ce99f6b9 1804 else if (family == AF_INET6)
1a8552bd 1805 err = mlx5e_create_encap_header_ipv6(priv, mirred_dev, e);
ce99f6b9 1806
232c0013 1807 if (err && err != -EAGAIN)
a54e20b4
HHZ		 1808 goto out_err;
1809
a54e20b4
HHZ		 1810 hash_add_rcu(esw->offloads.encap_tbl, &e->encap_hlist, hash_key);
1811
45247bf2
OG		 1812attach_flow:
1813 list_add(&flow->encap, &e->flows);
1814 *encap_dev = e->out_dev;
232c0013
HHZ		 1815 if (e->flags & MLX5_ENCAP_ENTRY_VALID)
1816 attr->encap_id = e->encap_id;
45247bf2 1817
232c0013 1818 return err;
a54e20b4
HHZ		 1819
1820out_err:
1821 kfree(e);
1822 return err;
1823}
1824
03a9d11e 1825static int parse_tc_fdb_actions(struct mlx5e_priv *priv, struct tcf_exts *exts,
d7e75a32 1826 struct mlx5e_tc_flow_parse_attr *parse_attr,
a54e20b4 1827 struct mlx5e_tc_flow *flow)
03a9d11e 1828{
ecf5bb79 1829 struct mlx5_esw_flow_attr *attr = flow->esw_attr;
1d447a39 1830 struct mlx5e_rep_priv *rpriv = priv->ppriv;
a54e20b4 1831 struct ip_tunnel_info *info = NULL;
03a9d11e 1832 const struct tc_action *a;
22dc13c8 1833 LIST_HEAD(actions);
a54e20b4 1834 bool encap = false;
232c0013 1835 int err = 0;
03a9d11e
OG		 1836
1837 if (tc_no_actions(exts))
1838 return -EINVAL;
1839
776b12b6 1840 memset(attr, 0, sizeof(*attr));
1d447a39 1841 attr->in_rep = rpriv->rep;
03a9d11e 1842
22dc13c8
WC		 1843 tcf_exts_to_list(exts, &actions);
1844 list_for_each_entry(a, &actions, list) {
03a9d11e 1845 if (is_tcf_gact_shot(a)) {
8b32580d
OG		 1846 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP |
1847 MLX5_FLOW_CONTEXT_ACTION_COUNT;
03a9d11e
OG		 1848 continue;
1849 }
1850
d7e75a32
OG		 1851 if (is_tcf_pedit(a)) {
1852 err = parse_tc_pedit_action(priv, a, MLX5_FLOW_NAMESPACE_FDB,
1853 parse_attr);
1854 if (err)
1855 return err;
1856
1857 attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1858 continue;
1859 }
1860
26c02749
OG		 1861 if (is_tcf_csum(a)) {
1862 if (csum_offload_supported(priv, attr->action,
1863 tcf_csum_update_flags(a)))
1864 continue;
1865
1866 return -EOPNOTSUPP;
1867 }
1868
5724b8b5 1869 if (is_tcf_mirred_egress_redirect(a)) {
03a9d11e 1870 int ifindex = tcf_mirred_ifindex(a);
45247bf2 1871 struct net_device *out_dev, *encap_dev = NULL;
03a9d11e 1872 struct mlx5e_priv *out_priv;
03a9d11e
OG		 1873
1874 out_dev = __dev_get_by_index(dev_net(priv->netdev), ifindex);
1875
a54e20b4
HHZ		 1876 if (switchdev_port_same_parent_id(priv->netdev,
1877 out_dev)) {
1878 attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1879 MLX5_FLOW_CONTEXT_ACTION_COUNT;
1880 out_priv = netdev_priv(out_dev);
1d447a39
SM		 1881 rpriv = out_priv->ppriv;
1882 attr->out_rep = rpriv->rep;
a54e20b4
HHZ		 1883 } else if (encap) {
1884 err = mlx5e_attach_encap(priv, info,
45247bf2 1885 out_dev, &encap_dev, flow);
232c0013 1886 if (err && err != -EAGAIN)
a54e20b4 1887 return err;
a54e20b4
HHZ		 1888 attr->action |= MLX5_FLOW_CONTEXT_ACTION_ENCAP |
1889 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST |
1890 MLX5_FLOW_CONTEXT_ACTION_COUNT;
45247bf2 1891 out_priv = netdev_priv(encap_dev);
1d447a39
SM		 1892 rpriv = out_priv->ppriv;
1893 attr->out_rep = rpriv->rep;
232c0013 1894 attr->parse_attr = parse_attr;
a54e20b4 1895 } else {
03a9d11e
OG		 1896 pr_err("devices %s %s not on same switch HW, can't offload forwarding\n",
1897 priv->netdev->name, out_dev->name);
1898 return -EINVAL;
1899 }
a54e20b4
HHZ		 1900 continue;
1901 }
03a9d11e 1902
a54e20b4
HHZ		 1903 if (is_tcf_tunnel_set(a)) {
1904 info = tcf_tunnel_info(a);
1905 if (info)
1906 encap = true;
1907 else
1908 return -EOPNOTSUPP;
03a9d11e
OG		 1909 continue;
1910 }
1911
8b32580d 1912 if (is_tcf_vlan(a)) {
09c91ddf 1913 if (tcf_vlan_action(a) == TCA_VLAN_ACT_POP) {
8b32580d 1914 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_POP;
09c91ddf 1915 } else if (tcf_vlan_action(a) == TCA_VLAN_ACT_PUSH) {
8b32580d
OG		 1916 if (tcf_vlan_push_proto(a) != htons(ETH_P_8021Q))
1917 return -EOPNOTSUPP;
1918
1919 attr->action |= MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH;
1920 attr->vlan = tcf_vlan_push_vid(a);
09c91ddf
OG		 1921 } else { /* action is TCA_VLAN_ACT_MODIFY */
1922 return -EOPNOTSUPP;
8b32580d
OG		 1923 }
1924 continue;
1925 }
1926
bbd00f7e
HHZ		 1927 if (is_tcf_tunnel_release(a)) {
1928 attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
1929 continue;
1930 }
1931
03a9d11e
OG		 1932 return -EINVAL;
1933 }
232c0013 1934 return err;
03a9d11e
OG		 1935}
1936
e3a2b7ed
AV		 1937int mlx5e_configure_flower(struct mlx5e_priv *priv, __be16 protocol,
1938 struct tc_cls_flower_offload *f)
1939{
3bc4b7bf 1940 struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
17091853 1941 struct mlx5e_tc_flow_parse_attr *parse_attr;
acff797c 1942 struct mlx5e_tc_table *tc = &priv->fs.tc;
3bc4b7bf
OG		 1943 struct mlx5e_tc_flow *flow;
1944 int attr_size, err = 0;
65ba8fb7 1945 u8 flow_flags = 0;
e3a2b7ed 1946
65ba8fb7
OG		 1947 if (esw && esw->mode == SRIOV_OFFLOADS) {
1948 flow_flags = MLX5E_TC_FLOW_ESWITCH;
1949 attr_size = sizeof(struct mlx5_esw_flow_attr);
3bc4b7bf
OG		 1950 } else {
1951 flow_flags = MLX5E_TC_FLOW_NIC;
1952 attr_size = sizeof(struct mlx5_nic_flow_attr);
65ba8fb7 1953 }
e3a2b7ed 1954
65ba8fb7 1955 flow = kzalloc(sizeof(*flow) + attr_size, GFP_KERNEL);
1b9a07ee 1956 parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
17091853 1957 if (!parse_attr || !flow) {
e3a2b7ed
AV		 1958 err = -ENOMEM;
1959 goto err_free;
1960 }
1961
1962 flow->cookie = f->cookie;
65ba8fb7 1963 flow->flags = flow_flags;
e3a2b7ed 1964
17091853 1965 err = parse_cls_flower(priv, flow, &parse_attr->spec, f);
e3a2b7ed
AV		 1966 if (err < 0)
1967 goto err_free;
1968
65ba8fb7 1969 if (flow->flags & MLX5E_TC_FLOW_ESWITCH) {
d7e75a32 1970 err = parse_tc_fdb_actions(priv, f->exts, parse_attr, flow);
adb4c123 1971 if (err < 0)
232c0013 1972 goto err_handle_encap_flow;
aa0cbbae 1973 flow->rule = mlx5e_tc_add_fdb_flow(priv, parse_attr, flow);
adb4c123 1974 } else {
aa0cbbae 1975 err = parse_tc_nic_actions(priv, f->exts, parse_attr, flow);
adb4c123
OG		 1976 if (err < 0)
1977 goto err_free;
aa0cbbae 1978 flow->rule = mlx5e_tc_add_nic_flow(priv, parse_attr, flow);
adb4c123 1979 }
e3a2b7ed 1980
e3a2b7ed
AV		 1981 if (IS_ERR(flow->rule)) {
1982 err = PTR_ERR(flow->rule);
aa0cbbae 1983 goto err_free;
e3a2b7ed
AV		 1984 }
1985
0b67a38f 1986 flow->flags |= MLX5E_TC_FLOW_OFFLOADED;
5c40348c
OG		 1987 err = rhashtable_insert_fast(&tc->ht, &flow->node,
1988 tc->ht_params);
1989 if (err)
1990 goto err_del_rule;
1991
232c0013
HHZ		 1992 if (flow->flags & MLX5E_TC_FLOW_ESWITCH &&
1993 !(flow->esw_attr->action & MLX5_FLOW_CONTEXT_ACTION_ENCAP))
1994 kvfree(parse_attr);
1995 return err;
e3a2b7ed 1996
5c40348c 1997err_del_rule:
5e86397a 1998 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed 1999
232c0013
HHZ		 2000err_handle_encap_flow:
2001 if (err == -EAGAIN) {
2002 err = rhashtable_insert_fast(&tc->ht, &flow->node,
2003 tc->ht_params);
2004 if (err)
2005 mlx5e_tc_del_flow(priv, flow);
2006 else
2007 return 0;
2008 }
2009
e3a2b7ed 2010err_free:
17091853 2011 kvfree(parse_attr);
232c0013 2012 kfree(flow);
e3a2b7ed
AV		 2013 return err;
2014}
2015
2016int mlx5e_delete_flower(struct mlx5e_priv *priv,
2017 struct tc_cls_flower_offload *f)
2018{
2019 struct mlx5e_tc_flow *flow;
acff797c 2020 struct mlx5e_tc_table *tc = &priv->fs.tc;
e3a2b7ed
AV		 2021
2022 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2023 tc->ht_params);
2024 if (!flow)
2025 return -EINVAL;
2026
2027 rhashtable_remove_fast(&tc->ht, &flow->node, tc->ht_params);
2028
961e8979 2029 mlx5e_tc_del_flow(priv, flow);
e3a2b7ed
AV		 2030
2031 kfree(flow);
2032
2033 return 0;
2034}
2035
aad7e08d
AV		 2036int mlx5e_stats_flower(struct mlx5e_priv *priv,
2037 struct tc_cls_flower_offload *f)
2038{
2039 struct mlx5e_tc_table *tc = &priv->fs.tc;
2040 struct mlx5e_tc_flow *flow;
aad7e08d
AV		 2041 struct mlx5_fc *counter;
2042 u64 bytes;
2043 u64 packets;
2044 u64 lastuse;
2045
2046 flow = rhashtable_lookup_fast(&tc->ht, &f->cookie,
2047 tc->ht_params);
2048 if (!flow)
2049 return -EINVAL;
2050
0b67a38f
HHZ		 2051 if (!(flow->flags & MLX5E_TC_FLOW_OFFLOADED))
2052 return 0;
2053
aad7e08d
AV		 2054 counter = mlx5_flow_rule_counter(flow->rule);
2055 if (!counter)
2056 return 0;
2057
2058 mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
2059
d897a638 2060 tcf_exts_stats_update(f->exts, bytes, packets, lastuse);
fed06ee8 2061
aad7e08d
AV		 2062 return 0;
2063}
2064
e8f887ac
AV		 2065static const struct rhashtable_params mlx5e_tc_flow_ht_params = {
2066 .head_offset = offsetof(struct mlx5e_tc_flow, node),
2067 .key_offset = offsetof(struct mlx5e_tc_flow, cookie),
2068 .key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
2069 .automatic_shrinking = true,
2070};
2071
2072int mlx5e_tc_init(struct mlx5e_priv *priv)
2073{
acff797c 2074 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac 2075
11c9c548
OG		 2076 hash_init(tc->mod_hdr_tbl);
2077
e8f887ac
AV		 2078 tc->ht_params = mlx5e_tc_flow_ht_params;
2079 return rhashtable_init(&tc->ht, &tc->ht_params);
2080}
2081
2082static void _mlx5e_tc_del_flow(void *ptr, void *arg)
2083{
2084 struct mlx5e_tc_flow *flow = ptr;
2085 struct mlx5e_priv *priv = arg;
2086
961e8979 2087 mlx5e_tc_del_flow(priv, flow);
e8f887ac
AV		 2088 kfree(flow);
2089}
2090
2091void mlx5e_tc_cleanup(struct mlx5e_priv *priv)
2092{
acff797c 2093 struct mlx5e_tc_table *tc = &priv->fs.tc;
e8f887ac
AV		 2094
2095 rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, priv);
2096
acff797c
MG		 2097 if (!IS_ERR_OR_NULL(tc->t)) {
2098 mlx5_destroy_flow_table(tc->t);
2099 tc->t = NULL;
e8f887ac
AV		 2100 }
2101}
Linux 6.x block layer and io_uring tree(s)