Merge tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel...

Pull RISC-V updates from Palmer Dabbelt:

 - Support for cbo.zero in userspace

 - Support for CBOs on ACPI-based systems

 - A handful of improvements for the T-Head cache flushing ops

 - Support for software shadow call stacks

 - Various cleanups and fixes

* tag 'riscv-for-linus-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (31 commits)
  RISC-V: hwprobe: Fix vDSO SIGSEGV
  riscv: configs: defconfig: Enable configs required for RZ/Five SoC
  riscv: errata: prefix T-Head mnemonics with th.
  riscv: put interrupt entries into .irqentry.text
  riscv: mm: Update the comment of CONFIG_PAGE_OFFSET
  riscv: Using TOOLCHAIN_HAS_ZIHINTPAUSE marco replace zihintpause
  riscv/mm: Fix the comment for swap pte format
  RISC-V: clarify the QEMU workaround in ISA parser
  riscv: correct pt_level name via pgtable_l5/4_enabled
  RISC-V: Provide pgtable_l5_enabled on rv32
  clocksource: timer-riscv: Increase rating of clock_event_device for Sstc
  clocksource: timer-riscv: Don't enable/disable timer interrupt
  lkdtm: Fix CFI_BACKWARD on RISC-V
  riscv: Use separate IRQ shadow call stacks
  riscv: Implement Shadow Call Stack
  riscv: Move global pointer loading to a macro
  riscv: Deduplicate IRQ stack switching
  riscv: VMAP_STACK overflow detection thread-safe
  RISC-V: cacheflush: Initialize CBO variables on ACPI systems
  RISC-V: ACPI: RHCT: Add function to get CBO block sizes
  ...

diff --cc Documentation/arch/riscv/hwprobe.rst
index a52996b22f75d3e8fea1064313cf36abcd878cf3,0000000000000000000000000000000000000000..7b2384de471f8fa5813271a010f8f5f011e7d8c3
mode 100644,000000..100644
--- 1/Documentation/arch/riscv/hwprobe.rst
--- /dev/null
+++ b/Documentation/arch/riscv/hwprobe.rst
@@@ -1,98 -1,0 +1,104 @@@
 +.. SPDX-License-Identifier: GPL-2.0
 +
 +RISC-V Hardware Probing Interface
 +---------------------------------
 +
 +The RISC-V hardware probing interface is based around a single syscall, which
 +is defined in <asm/hwprobe.h>::
 +
 +    struct riscv_hwprobe {
 +        __s64 key;
 +        __u64 value;
 +    };
 +
 +    long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, size_t pair_count,
 +                           size_t cpu_count, cpu_set_t *cpus,
 +                           unsigned int flags);
 +
 +The arguments are split into three groups: an array of key-value pairs, a CPU
 +set, and some flags. The key-value pairs are supplied with a count. Userspace
 +must prepopulate the key field for each element, and the kernel will fill in the
 +value if the key is recognized. If a key is unknown to the kernel, its key field
 +will be cleared to -1, and its value set to 0. The CPU set is defined by
 +CPU_SET(3). For value-like keys (eg. vendor/arch/impl), the returned value will
 +be only be valid if all CPUs in the given set have the same value. Otherwise -1
 +will be returned. For boolean-like keys, the value returned will be a logical
 +AND of the values for the specified CPUs. Usermode can supply NULL for cpus and
 +0 for cpu_count as a shortcut for all online CPUs. There are currently no flags,
 +this value must be zero for future compatibility.
 +
 +On success 0 is returned, on failure a negative error code is returned.
 +
 +The following keys are defined:
 +
 +* :c:macro:`RISCV_HWPROBE_KEY_MVENDORID`: Contains the value of ``mvendorid``,
 +  as defined by the RISC-V privileged architecture specification.
 +
 +* :c:macro:`RISCV_HWPROBE_KEY_MARCHID`: Contains the value of ``marchid``, as
 +  defined by the RISC-V privileged architecture specification.
 +
 +* :c:macro:`RISCV_HWPROBE_KEY_MIMPLID`: Contains the value of ``mimplid``, as
 +  defined by the RISC-V privileged architecture specification.
 +
 +* :c:macro:`RISCV_HWPROBE_KEY_BASE_BEHAVIOR`: A bitmask containing the base
 +  user-visible behavior that this kernel supports.  The following base user ABIs
 +  are defined:
 +
 +  * :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: Support for rv32ima or
 +    rv64ima, as defined by version 2.2 of the user ISA and version 1.10 of the
 +    privileged ISA, with the following known exceptions (more exceptions may be
 +    added, but only if it can be demonstrated that the user ABI is not broken):
 +
 +    * The ``fence.i`` instruction cannot be directly executed by userspace
 +      programs (it may still be executed in userspace via a
 +      kernel-controlled mechanism such as the vDSO).
 +
 +* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_0`: A bitmask containing the extensions
 +  that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`:
 +  base system behavior.
 +
 +  * :c:macro:`RISCV_HWPROBE_IMA_FD`: The F and D extensions are supported, as
 +    defined by commit cd20cee ("FMIN/FMAX now implement
 +    minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
 +
 +  * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
 +    by version 2.2 of the RISC-V ISA manual.
 +
 +  * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by
 +    version 1.0 of the RISC-V Vector extension manual.
 +
 +  * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
 +       supported, as defined in version 1.0 of the Bit-Manipulation ISA
 +       extensions.
 +
 +  * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined
 +       in version 1.0 of the Bit-Manipulation ISA extensions.
 +
 +  * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
 +       in version 1.0 of the Bit-Manipulation ISA extensions.
 +
++  * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
++       ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
++
 +* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
 +  information about the selected set of processors.
 +
 +  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNKNOWN`: The performance of misaligned
 +    accesses is unknown.
 +
 +  * :c:macro:`RISCV_HWPROBE_MISALIGNED_EMULATED`: Misaligned accesses are
 +    emulated via software, either in or below the kernel.  These accesses are
 +    always extremely slow.
 +
 +  * :c:macro:`RISCV_HWPROBE_MISALIGNED_SLOW`: Misaligned accesses are slower
 +    than equivalent byte accesses.  Misaligned accesses may be supported
 +    directly in hardware, or trapped and emulated by software.
 +
 +  * :c:macro:`RISCV_HWPROBE_MISALIGNED_FAST`: Misaligned accesses are faster
 +    than equivalent byte accesses.
 +
 +  * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are
 +    not supported at all and will generate a misaligned address fault.
++
++* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
++  represents the size of the Zicboz block in bytes.

diff --cc arch/riscv/Kconfig
Simple merge

diff --cc arch/riscv/Makefile
Simple merge

diff --cc arch/riscv/configs/defconfig
Simple merge

diff --cc arch/riscv/include/asm/hwcap.h
Simple merge

diff --cc arch/riscv/include/uapi/asm/hwprobe.h
Simple merge

diff --cc arch/riscv/kernel/cpufeature.c
Simple merge

diff --cc arch/riscv/kernel/irq.c
index 9cc0a76692715ea6ff2ec56630f7b60ed0a37f92,7bfea97ee7e7e0033ddb6dd43e0a138efa873c3f..9ceda02507cae9c73efac8c0589695b38d03e499
--- 1/arch/riscv/kernel/irq.c
--- 2/arch/riscv/kernel/irq.c
+++ b/arch/riscv/kernel/irq.c
@@@ -60,41 -79,23 +79,23 @@@ static void init_irq_stacks(void
  }
  #endif /* CONFIG_VMAP_STACK */
  
 -#ifdef CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK
 +#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
+ static void ___do_softirq(struct pt_regs *regs)
+ {
+       __do_softirq();
+ }
+ 
  void do_softirq_own_stack(void)
  {
- #ifdef CONFIG_IRQ_STACKS
-       if (on_thread_stack()) {
-               ulong *sp = per_cpu(irq_stack_ptr, smp_processor_id())
-                                       + IRQ_STACK_SIZE/sizeof(ulong);
-               __asm__ __volatile(
-               "addi   sp, sp, -"RISCV_SZPTR  "\n"
-               REG_S"  ra, (sp)                \n"
-               "addi   sp, sp, -"RISCV_SZPTR  "\n"
-               REG_S"  s0, (sp)                \n"
-               "addi   s0, sp, 2*"RISCV_SZPTR "\n"
-               "move   sp, %[sp]               \n"
-               "call   __do_softirq            \n"
-               "addi   sp, s0, -2*"RISCV_SZPTR"\n"
-               REG_L"  s0, (sp)                \n"
-               "addi   sp, sp, "RISCV_SZPTR   "\n"
-               REG_L"  ra, (sp)                \n"
-               "addi   sp, sp, "RISCV_SZPTR   "\n"
-               :
-               : [sp] "r" (sp)
-               : "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
-                 "t0", "t1", "t2", "t3", "t4", "t5", "t6",
- #ifndef CONFIG_FRAME_POINTER
-                 "s0",
- #endif
-                 "memory");
-       } else
- #endif
+       if (on_thread_stack())
+               call_on_irq_stack(NULL, ___do_softirq);
+       else
                __do_softirq();
  }
 -#endif /* CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK */
 +#endif /* CONFIG_SOFTIRQ_ON_OWN_STACK */
  
  #else
+ static void init_irq_scs(void) {}
  static void init_irq_stacks(void) {}
  #endif /* CONFIG_IRQ_STACKS */
  

diff --cc arch/riscv/kernel/setup.c
Simple merge

diff --cc arch/riscv/kernel/sys_riscv.c
Simple merge

diff --cc arch/riscv/kernel/traps.c
Simple merge

diff --cc arch/riscv/kernel/vdso/Makefile
Simple merge

diff --cc arch/riscv/mm/init.c
Simple merge

diff --cc drivers/clocksource/timer-riscv.c
Simple merge