Merge tag 'drm-intel-gt-next-2022-09-16' of git://anongit.freedesktop.org/drm/drm...

Cross-subsystem Changes:

- MEI subsystem pieces for XeHP SDV GSC support
  These are Acked-by Greg.

Driver Changes:

- Release mmaps on RPM suspend on discrete GPUs (Anshuman)
- Update GuC version to 7.5 on DG1, DG2 and ADL
- Revert "drm/i915/dg2: extend Wa_1409120013 to DG2" (Lucas)
- MTL enabling incl. standalone media (Matt R, Lucas)
- Explicitly clear BB_OFFSET for new contexts on Gen8+ (Chris)
- Fix throttling / perf limit reason decoding (Ashutosh)
- XeHP SDV GSC support (Vitaly, Alexander, Tomas)

- Fix issues with overrding firmware file paths (John)
- Invert if-else ladders to check latest version first (Lucas)
- Cancel GuC engine busyness worker synchronously (Umesh)

- Skip applying copy engine fuses outside PVC (Lucas)
- Eliminate Gen10 frequency read function (Lucas)
- Static code checker fixes (Gaosheng)
- Selftest improvements (Chris)

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YyQ4Jgl3cpGL1/As@jlahtine-mobl.ger.corp.intel.com

diff --cc drivers/gpu/drm/i915/Makefile
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_stolen.c
Simple merge

diff --cc drivers/gpu/drm/i915/gem/i915_gem_ttm.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c
Simple merge

diff --cc drivers/gpu/drm/i915/gt/intel_gt.c
index e4bac2431e41607de83512f4e6620acaa4c498d4,926a1515cd3b09bce69531327b77e2e84050da9f..d0b03a928b9acaaae274907fa73e4431186470e6
--- 1/drivers/gpu/drm/i915/gt/intel_gt.c
--- 2/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@@ -827,11 -821,13 +822,13 @@@ int intel_gt_probe_all(struct drm_i915_
  {
        struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
        struct intel_gt *gt = &i915->gt0;
+       const struct intel_gt_definition *gtdef;
        phys_addr_t phys_addr;
        unsigned int mmio_bar;
+       unsigned int i;
        int ret;
  
 -      mmio_bar = GRAPHICS_VER(i915) == 2 ? 1 : 0;
 +      mmio_bar = GRAPHICS_VER(i915) == 2 ? GEN2_GTTMMADR_BAR : GTTMMADR_BAR;
        phys_addr = pci_resource_start(pdev, mmio_bar);
  
        /*
@@@ -839,6 -835,11 +836,11 @@@
         * and it has been already initialized early during probe
         * in i915_driver_probe()
         */
 -      gt->info.engine_mask = INTEL_INFO(i915)->platform_engine_mask;
+       gt->i915 = i915;
+       gt->name = "Primary GT";
++      gt->info.engine_mask = RUNTIME_INFO(i915)->platform_engine_mask;
+ 
+       drm_dbg(&i915->drm, "Setting up %s\n", gt->name);
        ret = intel_gt_tile_setup(gt, phys_addr);
        if (ret)
                return ret;

diff --cc drivers/gpu/drm/i915/i915_driver.c
index 053a7dab55061667b49614cd5dbd57dd51eae77a,01f42777b6e32f347f8816cf219337fbd08d923d..d94e183d716a547f0ef82e18f3c1ef0746a53a93
--- 1/drivers/gpu/drm/i915/i915_driver.c
--- 2/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@@ -793,10 -810,11 +825,11 @@@ static void i915_welcome_messages(struc
                                             INTEL_INFO(dev_priv)->platform),
                           GRAPHICS_VER(dev_priv));
  
 -              intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
 -              intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
 +              intel_device_info_print(INTEL_INFO(dev_priv),
 +                                      RUNTIME_INFO(dev_priv), &p);
                i915_print_iommu_status(dev_priv, &p);
-               intel_gt_info_print(&to_gt(dev_priv)->info, &p);
+               for_each_gt(gt, dev_priv, i)
+                       intel_gt_info_print(&gt->info, &p);
        }
  
        if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
@@@ -1585,7 -1612,9 +1622,8 @@@ static int intel_runtime_suspend(struc
  {
        struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
        struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
-       int ret;
 -      struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+       struct intel_gt *gt;
+       int ret, i;
  
        if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
                return -ENODEV;
@@@ -1668,7 -1705,9 +1708,8 @@@ static int intel_runtime_resume(struct 
  {
        struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
        struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
-       int ret;
 -      struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
+       struct intel_gt *gt;
+       int ret, i;
  
        if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
                return -ENODEV;

diff --cc drivers/gpu/drm/i915/i915_drv.h
index ba8a16d0fe7ca02d169b3c1d3eb95882db448775,b11c212f1b0d6a3a321cce90c8cae3da03c91a63..4828f9d2460d8d44f849601e769ee4345cc05f43
--- 1/drivers/gpu/drm/i915/i915_drv.h
--- 2/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@@ -1058,9 -1369,11 +1061,11 @@@ IS_SUBPLATFORM(const struct drm_i915_pr
  
  #define HAS_IPC(dev_priv)              (INTEL_INFO(dev_priv)->display.has_ipc)
  
 -#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
 +#define HAS_REGION(i915, i) (RUNTIME_INFO(i915)->memory_regions & (i))
  #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
  
+ #define HAS_EXTRA_GT_LIST(dev_priv)   (INTEL_INFO(dev_priv)->extra_gt_list)
+ 
  /*
   * Platform has the dedicated compression control state for each lmem surfaces
   * stored in lmem to support the 3D and media compression formats.

diff --cc drivers/gpu/drm/i915/i915_gem.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_irq.c
Simple merge

diff --cc drivers/gpu/drm/i915/i915_pci.c
index 26b25d9434d662634b03b5caaa5771f9b5f47197,2899c7cbdfb525361c75c325184cf4834c319d67..19fc00bcd7b9ba9067c1e064bd4c9dfc9215b674
--- 1/drivers/gpu/drm/i915/i915_pci.c
--- 2/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@@ -1112,9 -1118,18 +1115,19 @@@ static const struct intel_device_info p
  #define XE_LPDP_FEATURES      \
        XE_LPD_FEATURES,        \
        .display.ver = 14,      \
 -      .display.has_cdclk_crawl = 1
 +      .display.has_cdclk_crawl = 1, \
 +      .__runtime.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B)
  
+ static const struct intel_gt_definition xelpmp_extra_gt[] = {
+       {
+               .type = GT_MEDIA,
+               .name = "Standalone Media GT",
+               .gsi_offset = MTL_MEDIA_GSI_BASE,
+               .engine_mask = BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
+       },
+       {}
+ };
+ 
  __maybe_unused
  static const struct intel_device_info mtl_info = {
        XE_HP_FEATURES,
@@@ -1128,10 -1143,11 +1141,11 @@@
        .media.ver = 13,
        PLATFORM(INTEL_METEORLAKE),
        .display.has_modular_fia = 1,
+       .extra_gt_list = xelpmp_extra_gt,
        .has_flat_ccs = 0,
        .has_snoop = 1,
 -      .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
 -      .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
 +      .__runtime.memory_regions = REGION_SMEM | REGION_STOLEN_LMEM,
 +      .__runtime.platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0),
        .require_force_probe = 1,
  };
  

diff --cc drivers/gpu/drm/i915/i915_reg.h
Simple merge

diff --cc drivers/gpu/drm/i915/intel_device_info.h
index 6904ad03ca19f7061562af52081a122a5350de7d,80ff83f96b8863b30fe8608105c621d457205a17..deaa07d8df2c14eeb6d062ea768325f86a5bdf61
--- 1/drivers/gpu/drm/i915/intel_device_info.h
--- 2/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@@ -225,33 -217,14 +226,35 @@@ struct intel_runtime_info 
        enum intel_ppgtt_type ppgtt_type;
        unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
  
 -      unsigned int page_sizes; /* page sizes supported by the HW */
 -
        u32 memory_regions; /* regions supported by the HW */
  
 -      u32 display_mmio_offset;
 +      bool has_pooled_eu;
 +
 +      /* display */
 +      struct {
 +              u8 pipe_mask;
 +              u8 cpu_transcoder_mask;
 +
 +              u8 num_sprites[I915_MAX_PIPES];
 +              u8 num_scalers[I915_MAX_PIPES];
 +
 +              u8 fbc_mask;
 +
 +              bool has_hdcp;
 +              bool has_dmc;
 +              bool has_dsc;
 +      };
 +};
 +
 +struct intel_device_info {
 +      struct ip_version media;
 +
 +      enum intel_platform platform;
 +
 +      unsigned int dma_mask_size; /* available DMA address bits */
  
+       const struct intel_gt_definition *extra_gt_list;
+ 
        u8 gt; /* GT number, 0 if undefined */
  
  #define DEFINE_FLAG(name) u8 name:1

diff --cc drivers/gpu/drm/i915/intel_pm.c
Simple merge

diff --cc drivers/gpu/drm/i915/intel_uncore.c
Simple merge

diff --cc drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.c
Simple merge

diff --cc drivers/gpu/drm/i915/selftests/mock_gem_device.c
Simple merge

diff --cc drivers/misc/mei/hbm.c
Simple merge

diff --cc drivers/misc/mei/hw-me-regs.h
Simple merge

diff --cc drivers/misc/mei/hw-me.c
Simple merge

diff --cc drivers/misc/mei/pci-me.c
Simple merge