Merge tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel...

Pull more RISC-V updates from Palmer Dabbelt:

 - Support for handling misaligned accesses in S-mode

 - Probing for misaligned access support is now properly cached and
   handled in parallel

 - PTDUMP now reflects the SW reserved bits, as well as the PBMT and
   NAPOT extensions

 - Performance improvements for TLB flushing

 - Support for many new relocations in the module loader

 - Various bug fixes and cleanups

* tag 'riscv-for-linus-6.7-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (51 commits)
  riscv: Optimize bitops with Zbb extension
  riscv: Rearrange hwcap.h and cpufeature.h
  drivers: perf: Do not broadcast to other cpus when starting a counter
  drivers: perf: Check find_first_bit() return value
  of: property: Add fw_devlink support for msi-parent
  RISC-V: Don't fail in riscv_of_parent_hartid() for disabled HARTs
  riscv: Fix set_memory_XX() and set_direct_map_XX() by splitting huge linear mappings
  riscv: Don't use PGD entries for the linear mapping
  RISC-V: Probe misaligned access speed in parallel
  RISC-V: Remove __init on unaligned_emulation_finish()
  RISC-V: Show accurate per-hart isa in /proc/cpuinfo
  RISC-V: Don't rely on positional structure initialization
  riscv: Add tests for riscv module loading
  riscv: Add remaining module relocations
  riscv: Avoid unaligned access when relocating modules
  riscv: split cache ops out of dma-noncoherent.c
  riscv: Improve flush_tlb_kernel_range()
  riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb
  riscv: Improve flush_tlb_range() for hugetlb pages
  riscv: Improve tlb_flush()
  ...

diff --cc Documentation/arch/riscv/uabi.rst
index 8960fac42c40f3c7fd288f86f5f8d2233f422f09,0000000000000000000000000000000000000000..54d199dce78bf50525b0430dcfc5a6a71429bf68
mode 100644,000000..100644
--- 1/Documentation/arch/riscv/uabi.rst
--- /dev/null
+++ b/Documentation/arch/riscv/uabi.rst
@@@ -1,48 -1,0 +1,68 @@@
 +.. SPDX-License-Identifier: GPL-2.0
 +
 +RISC-V Linux User ABI
 +=====================
 +
 +ISA string ordering in /proc/cpuinfo
 +------------------------------------
 +
 +The canonical order of ISA extension names in the ISA string is defined in
 +chapter 27 of the unprivileged specification.
 +The specification uses vague wording, such as should, when it comes to ordering,
 +so for our purposes the following rules apply:
 +
 +#. Single-letter extensions come first, in canonical order.
 +   The canonical order is "IMAFDQLCBKJTPVH".
 +
 +#. All multi-letter extensions will be separated from other extensions by an
 +   underscore.
 +
 +#. Additional standard extensions (starting with 'Z') will be sorted after
 +   single-letter extensions and before any higher-privileged extensions.
 +
 +#. For additional standard extensions, the first letter following the 'Z'
 +   conventionally indicates the most closely related alphabetical
 +   extension category. If multiple 'Z' extensions are named, they will be
 +   ordered first by category, in canonical order, as listed above, then
 +   alphabetically within a category.
 +
 +#. Standard supervisor-level extensions (starting with 'S') will be listed
 +   after standard unprivileged extensions.  If multiple supervisor-level
 +   extensions are listed, they will be ordered alphabetically.
 +
 +#. Standard machine-level extensions (starting with 'Zxm') will be listed
 +   after any lower-privileged, standard extensions. If multiple machine-level
 +   extensions are listed, they will be ordered alphabetically.
 +
 +#. Non-standard extensions (starting with 'X') will be listed after all standard
 +   extensions. If multiple non-standard extensions are listed, they will be
 +   ordered alphabetically.
 +
 +An example string following the order is::
 +
 +   rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux
 +
++"isa" and "hart isa" lines in /proc/cpuinfo
++-------------------------------------------
++
++The "isa" line in /proc/cpuinfo describes the lowest common denominator of
++RISC-V ISA extensions recognized by the kernel and implemented on all harts. The
++"hart isa" line, in contrast, describes the set of extensions recognized by the
++kernel on the particular hart being described, even if those extensions may not
++be present on all harts in the system.
++
++In both lines, the presence of an extension guarantees only that the hardware
++has the described capability. Additional kernel support or policy changes may be
++required before an extension's capability is fully usable by userspace programs.
++Similarly, for S-mode extensions, presence in one of these lines does not
++guarantee that the kernel is taking advantage of the extension, or that the
++feature will be visible in guest VMs managed by this kernel.
++
++Inversely, the absence of an extension in these lines does not necessarily mean
++the hardware does not support that feature. The running kernel may not recognize
++the extension, or may have deliberately removed it from the listing.
++
 +Misaligned accesses
 +-------------------
 +
 +Misaligned accesses are supported in userspace, but they may perform poorly.

diff --cc arch/riscv/Kconfig
Simple merge

diff --cc arch/riscv/configs/defconfig
Simple merge

diff --cc arch/riscv/include/asm/bitops.h
Simple merge

diff --cc arch/riscv/include/asm/hwcap.h
Simple merge

diff --cc arch/riscv/include/asm/processor.h
Simple merge

diff --cc arch/riscv/include/asm/sbi.h
Simple merge

diff --cc arch/riscv/kernel/cpufeature.c
Simple merge

diff --cc arch/riscv/kvm/vcpu_onereg.c
Simple merge

diff --cc arch/riscv/mm/init.c
Simple merge

diff --cc drivers/clocksource/timer-riscv.c
Simple merge

diff --cc drivers/firmware/efi/libstub/Makefile
Simple merge