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net: ethernet: ti: am65-cpsw: Delete unreachable error handling code
[linux-2.6-block.git] / drivers / net / ethernet / ti / am65-cpts.c
CommitLineData
f6bd5952
GS		 1// SPDX-License-Identifier: GPL-2.0
2/* TI K3 AM65x Common Platform Time Sync
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
5 *
6 */
7
8#include <linux/clk.h>
9#include <linux/clk-provider.h>
10#include <linux/err.h>
11#include <linux/if_vlan.h>
12#include <linux/interrupt.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/net_tstamp.h>
16#include <linux/of.h>
17#include <linux/of_irq.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/ptp_classify.h>
21#include <linux/ptp_clock_kernel.h>
22
23#include "am65-cpts.h"
24
25struct am65_genf_regs {
26 u32 comp_lo; /* Comparison Low Value 0:31 */
27 u32 comp_hi; /* Comparison High Value 32:63 */
28 u32 control; /* control */
29 u32 length; /* Length */
30 u32 ppm_low; /* PPM Load Low Value 0:31 */
31 u32 ppm_hi; /* PPM Load High Value 32:63 */
32 u32 ts_nudge; /* Nudge value */
33} __aligned(32) __packed;
34
35#define AM65_CPTS_GENF_MAX_NUM 9
36#define AM65_CPTS_ESTF_MAX_NUM 8
37
38struct am65_cpts_regs {
39 u32 idver; /* Identification and version */
40 u32 control; /* Time sync control */
41 u32 rftclk_sel; /* Reference Clock Select Register */
42 u32 ts_push; /* Time stamp event push */
43 u32 ts_load_val_lo; /* Time Stamp Load Low Value 0:31 */
44 u32 ts_load_en; /* Time stamp load enable */
45 u32 ts_comp_lo; /* Time Stamp Comparison Low Value 0:31 */
46 u32 ts_comp_length; /* Time Stamp Comparison Length */
47 u32 intstat_raw; /* Time sync interrupt status raw */
48 u32 intstat_masked; /* Time sync interrupt status masked */
49 u32 int_enable; /* Time sync interrupt enable */
50 u32 ts_comp_nudge; /* Time Stamp Comparison Nudge Value */
51 u32 event_pop; /* Event interrupt pop */
52 u32 event_0; /* Event Time Stamp lo 0:31 */
53 u32 event_1; /* Event Type Fields */
54 u32 event_2; /* Event Type Fields domain */
55 u32 event_3; /* Event Time Stamp hi 32:63 */
56 u32 ts_load_val_hi; /* Time Stamp Load High Value 32:63 */
57 u32 ts_comp_hi; /* Time Stamp Comparison High Value 32:63 */
58 u32 ts_add_val; /* Time Stamp Add value */
59 u32 ts_ppm_low; /* Time Stamp PPM Load Low Value 0:31 */
60 u32 ts_ppm_hi; /* Time Stamp PPM Load High Value 32:63 */
61 u32 ts_nudge; /* Time Stamp Nudge value */
62 u32 reserv[33];
63 struct am65_genf_regs genf[AM65_CPTS_GENF_MAX_NUM];
64 struct am65_genf_regs estf[AM65_CPTS_ESTF_MAX_NUM];
65};
66
67/* CONTROL_REG */
68#define AM65_CPTS_CONTROL_EN BIT(0)
69#define AM65_CPTS_CONTROL_INT_TEST BIT(1)
70#define AM65_CPTS_CONTROL_TS_COMP_POLARITY BIT(2)
71#define AM65_CPTS_CONTROL_TSTAMP_EN BIT(3)
72#define AM65_CPTS_CONTROL_SEQUENCE_EN BIT(4)
73#define AM65_CPTS_CONTROL_64MODE BIT(5)
74#define AM65_CPTS_CONTROL_TS_COMP_TOG BIT(6)
75#define AM65_CPTS_CONTROL_TS_PPM_DIR BIT(7)
76#define AM65_CPTS_CONTROL_HW1_TS_PUSH_EN BIT(8)
77#define AM65_CPTS_CONTROL_HW2_TS_PUSH_EN BIT(9)
78#define AM65_CPTS_CONTROL_HW3_TS_PUSH_EN BIT(10)
79#define AM65_CPTS_CONTROL_HW4_TS_PUSH_EN BIT(11)
80#define AM65_CPTS_CONTROL_HW5_TS_PUSH_EN BIT(12)
81#define AM65_CPTS_CONTROL_HW6_TS_PUSH_EN BIT(13)
82#define AM65_CPTS_CONTROL_HW7_TS_PUSH_EN BIT(14)
83#define AM65_CPTS_CONTROL_HW8_TS_PUSH_EN BIT(15)
84#define AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET (8)
85
4d4dce31
GS		 86#define AM65_CPTS_CONTROL_TX_GENF_CLR_EN BIT(17)
87
f6bd5952
GS		 88#define AM65_CPTS_CONTROL_TS_SYNC_SEL_MASK (0xF)
89#define AM65_CPTS_CONTROL_TS_SYNC_SEL_SHIFT (28)
90
91/* RFTCLK_SEL_REG */
92#define AM65_CPTS_RFTCLK_SEL_MASK (0x1F)
93
94/* TS_PUSH_REG */
95#define AM65_CPTS_TS_PUSH BIT(0)
96
97/* TS_LOAD_EN_REG */
98#define AM65_CPTS_TS_LOAD_EN BIT(0)
99
100/* INTSTAT_RAW_REG */
101#define AM65_CPTS_INTSTAT_RAW_TS_PEND BIT(0)
102
103/* INTSTAT_MASKED_REG */
104#define AM65_CPTS_INTSTAT_MASKED_TS_PEND BIT(0)
105
106/* INT_ENABLE_REG */
107#define AM65_CPTS_INT_ENABLE_TS_PEND_EN BIT(0)
108
109/* TS_COMP_NUDGE_REG */
110#define AM65_CPTS_TS_COMP_NUDGE_MASK (0xFF)
111
112/* EVENT_POP_REG */
113#define AM65_CPTS_EVENT_POP BIT(0)
114
115/* EVENT_1_REG */
116#define AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK GENMASK(15, 0)
117
118#define AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK GENMASK(19, 16)
119#define AM65_CPTS_EVENT_1_MESSAGE_TYPE_SHIFT (16)
120
121#define AM65_CPTS_EVENT_1_EVENT_TYPE_MASK GENMASK(23, 20)
122#define AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT (20)
123
124#define AM65_CPTS_EVENT_1_PORT_NUMBER_MASK GENMASK(28, 24)
125#define AM65_CPTS_EVENT_1_PORT_NUMBER_SHIFT (24)
126
127/* EVENT_2_REG */
128#define AM65_CPTS_EVENT_2_REG_DOMAIN_MASK (0xFF)
129#define AM65_CPTS_EVENT_2_REG_DOMAIN_SHIFT (0)
130
131enum {
132 AM65_CPTS_EV_PUSH, /* Time Stamp Push Event */
133 AM65_CPTS_EV_ROLL, /* Time Stamp Rollover Event */
134 AM65_CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
135 AM65_CPTS_EV_HW, /* Hardware Time Stamp Push Event */
136 AM65_CPTS_EV_RX, /* Ethernet Receive Event */
137 AM65_CPTS_EV_TX, /* Ethernet Transmit Event */
138 AM65_CPTS_EV_TS_COMP, /* Time Stamp Compare Event */
139 AM65_CPTS_EV_HOST, /* Host Transmit Event */
140};
141
142struct am65_cpts_event {
143 struct list_head list;
144 unsigned long tmo;
145 u32 event1;
146 u32 event2;
147 u64 timestamp;
148};
149
150#define AM65_CPTS_FIFO_DEPTH (16)
151#define AM65_CPTS_MAX_EVENTS (32)
152#define AM65_CPTS_EVENT_RX_TX_TIMEOUT (20) /* ms */
153#define AM65_CPTS_SKB_TX_WORK_TIMEOUT 1 /* jiffies */
154#define AM65_CPTS_MIN_PPM 0x400
155
156struct am65_cpts {
157 struct device *dev;
158 struct am65_cpts_regs __iomem *reg;
159 struct ptp_clock_info ptp_info;
160 struct ptp_clock *ptp_clock;
161 int phc_index;
162 struct clk_hw *clk_mux_hw;
163 struct device_node *clk_mux_np;
164 struct clk *refclk;
165 u32 refclk_freq;
166 struct list_head events;
167 struct list_head pool;
168 struct am65_cpts_event pool_data[AM65_CPTS_MAX_EVENTS];
169 spinlock_t lock; /* protects events lists*/
170 u32 ext_ts_inputs;
171 u32 genf_num;
172 u32 ts_add_val;
173 int irq;
174 struct mutex ptp_clk_lock; /* PHC access sync */
175 u64 timestamp;
176 u32 genf_enable;
177 u32 hw_ts_enable;
178 struct sk_buff_head txq;
b6d78712
GS		 179 bool pps_enabled;
180 bool pps_present;
181 u32 pps_hw_ts_idx;
182 u32 pps_genf_idx;
cef122d4
RQ		 183 /* context save/restore */
184 u64 sr_cpts_ns;
185 u64 sr_ktime_ns;
186 u32 sr_control;
187 u32 sr_int_enable;
188 u32 sr_rftclk_sel;
189 u32 sr_ts_ppm_hi;
190 u32 sr_ts_ppm_low;
191 struct am65_genf_regs sr_genf[AM65_CPTS_GENF_MAX_NUM];
192 struct am65_genf_regs sr_estf[AM65_CPTS_ESTF_MAX_NUM];
f6bd5952
GS		 193};
194
195struct am65_cpts_skb_cb_data {
196 unsigned long tmo;
197 u32 skb_mtype_seqid;
198};
199
200#define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
201#define am65_cpts_read32(c, r) readl(&(c)->reg->r)
202
203static void am65_cpts_settime(struct am65_cpts *cpts, u64 start_tstamp)
204{
205 u32 val;
206
207 val = upper_32_bits(start_tstamp);
208 am65_cpts_write32(cpts, val, ts_load_val_hi);
209 val = lower_32_bits(start_tstamp);
210 am65_cpts_write32(cpts, val, ts_load_val_lo);
211
212 am65_cpts_write32(cpts, AM65_CPTS_TS_LOAD_EN, ts_load_en);
213}
214
215static void am65_cpts_set_add_val(struct am65_cpts *cpts)
216{
217 /* select coefficient according to the rate */
218 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7;
219
220 am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val);
221}
222
223static void am65_cpts_disable(struct am65_cpts *cpts)
224{
225 am65_cpts_write32(cpts, 0, control);
226 am65_cpts_write32(cpts, 0, int_enable);
227}
228
229static int am65_cpts_event_get_port(struct am65_cpts_event *event)
230{
231 return (event->event1 & AM65_CPTS_EVENT_1_PORT_NUMBER_MASK) >>
232 AM65_CPTS_EVENT_1_PORT_NUMBER_SHIFT;
233}
234
235static int am65_cpts_event_get_type(struct am65_cpts_event *event)
236{
237 return (event->event1 & AM65_CPTS_EVENT_1_EVENT_TYPE_MASK) >>
238 AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT;
239}
240
241static int am65_cpts_cpts_purge_events(struct am65_cpts *cpts)
242{
243 struct list_head *this, *next;
244 struct am65_cpts_event *event;
245 int removed = 0;
246
247 list_for_each_safe(this, next, &cpts->events) {
248 event = list_entry(this, struct am65_cpts_event, list);
249 if (time_after(jiffies, event->tmo)) {
250 list_del_init(&event->list);
251 list_add(&event->list, &cpts->pool);
252 ++removed;
253 }
254 }
255
256 if (removed)
257 dev_dbg(cpts->dev, "event pool cleaned up %d\n", removed);
258 return removed ? 0 : -1;
259}
260
261static bool am65_cpts_fifo_pop_event(struct am65_cpts *cpts,
262 struct am65_cpts_event *event)
263{
264 u32 r = am65_cpts_read32(cpts, intstat_raw);
265
266 if (r & AM65_CPTS_INTSTAT_RAW_TS_PEND) {
267 event->timestamp = am65_cpts_read32(cpts, event_0);
268 event->event1 = am65_cpts_read32(cpts, event_1);
269 event->event2 = am65_cpts_read32(cpts, event_2);
270 event->timestamp |= (u64)am65_cpts_read32(cpts, event_3) << 32;
271 am65_cpts_write32(cpts, AM65_CPTS_EVENT_POP, event_pop);
272 return false;
273 }
274 return true;
275}
276
277static int am65_cpts_fifo_read(struct am65_cpts *cpts)
278{
279 struct ptp_clock_event pevent;
280 struct am65_cpts_event *event;
281 bool schedule = false;
282 int i, type, ret = 0;
283 unsigned long flags;
284
285 spin_lock_irqsave(&cpts->lock, flags);
286 for (i = 0; i < AM65_CPTS_FIFO_DEPTH; i++) {
287 event = list_first_entry_or_null(&cpts->pool,
288 struct am65_cpts_event, list);
289
290 if (!event) {
291 if (am65_cpts_cpts_purge_events(cpts)) {
292 dev_err(cpts->dev, "cpts: event pool empty\n");
293 ret = -1;
294 goto out;
295 }
296 continue;
297 }
298
299 if (am65_cpts_fifo_pop_event(cpts, event))
300 break;
301
302 type = am65_cpts_event_get_type(event);
303 switch (type) {
304 case AM65_CPTS_EV_PUSH:
305 cpts->timestamp = event->timestamp;
306 dev_dbg(cpts->dev, "AM65_CPTS_EV_PUSH t:%llu\n",
307 cpts->timestamp);
308 break;
309 case AM65_CPTS_EV_RX:
310 case AM65_CPTS_EV_TX:
311 event->tmo = jiffies +
312 msecs_to_jiffies(AM65_CPTS_EVENT_RX_TX_TIMEOUT);
313
314 list_del_init(&event->list);
315 list_add_tail(&event->list, &cpts->events);
316
317 dev_dbg(cpts->dev,
318 "AM65_CPTS_EV_TX e1:%08x e2:%08x t:%lld\n",
319 event->event1, event->event2,
320 event->timestamp);
321 schedule = true;
322 break;
323 case AM65_CPTS_EV_HW:
324 pevent.index = am65_cpts_event_get_port(event) - 1;
325 pevent.timestamp = event->timestamp;
b6d78712
GS		 326 if (cpts->pps_enabled && pevent.index == cpts->pps_hw_ts_idx) {
327 pevent.type = PTP_CLOCK_PPSUSR;
328 pevent.pps_times.ts_real = ns_to_timespec64(pevent.timestamp);
329 } else {
330 pevent.type = PTP_CLOCK_EXTTS;
331 }
332 dev_dbg(cpts->dev, "AM65_CPTS_EV_HW:%s p:%d t:%llu\n",
333 pevent.type == PTP_CLOCK_EXTTS ?
334 "extts" : "pps",
f6bd5952
GS		 335 pevent.index, event->timestamp);
336
337 ptp_clock_event(cpts->ptp_clock, &pevent);
338 break;
339 case AM65_CPTS_EV_HOST:
340 break;
341 case AM65_CPTS_EV_ROLL:
342 case AM65_CPTS_EV_HALF:
343 case AM65_CPTS_EV_TS_COMP:
344 dev_dbg(cpts->dev,
345 "AM65_CPTS_EVT: %d e1:%08x e2:%08x t:%lld\n",
346 type,
347 event->event1, event->event2,
348 event->timestamp);
349 break;
350 default:
351 dev_err(cpts->dev, "cpts: unknown event type\n");
352 ret = -1;
353 goto out;
354 }
355 }
356
357out:
358 spin_unlock_irqrestore(&cpts->lock, flags);
359
360 if (schedule)
361 ptp_schedule_worker(cpts->ptp_clock, 0);
362
363 return ret;
364}
365
366static u64 am65_cpts_gettime(struct am65_cpts *cpts,
367 struct ptp_system_timestamp *sts)
368{
369 unsigned long flags;
370 u64 val = 0;
371
372 /* temporarily disable cpts interrupt to avoid intentional
373 * doubled read. Interrupt can be in-flight - it's Ok.
374 */
375 am65_cpts_write32(cpts, 0, int_enable);
376
377 /* use spin_lock_irqsave() here as it has to run very fast */
378 spin_lock_irqsave(&cpts->lock, flags);
379 ptp_read_system_prets(sts);
380 am65_cpts_write32(cpts, AM65_CPTS_TS_PUSH, ts_push);
381 am65_cpts_read32(cpts, ts_push);
382 ptp_read_system_postts(sts);
383 spin_unlock_irqrestore(&cpts->lock, flags);
384
385 am65_cpts_fifo_read(cpts);
386
387 am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable);
388
389 val = cpts->timestamp;
390
391 return val;
392}
393
394static irqreturn_t am65_cpts_interrupt(int irq, void *dev_id)
395{
396 struct am65_cpts *cpts = dev_id;
397
398 if (am65_cpts_fifo_read(cpts))
399 dev_dbg(cpts->dev, "cpts: unable to obtain a time stamp\n");
400
401 return IRQ_HANDLED;
402}
403
404/* PTP clock operations */
e2bd9c76 405static int am65_cpts_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
f6bd5952
GS		 406{
407 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
eb9233ce 408 u32 pps_ctrl_val = 0, pps_ppm_hi = 0, pps_ppm_low = 0;
e2bd9c76 409 s32 ppb = scaled_ppm_to_ppb(scaled_ppm);
eb9233ce
GS		 410 int pps_index = cpts->pps_genf_idx;
411 u64 adj_period, pps_adj_period;
412 u32 ctrl_val, ppm_hi, ppm_low;
413 unsigned long flags;
f6bd5952 414 int neg_adj = 0;
f6bd5952
GS		 415
416 if (ppb < 0) {
417 neg_adj = 1;
418 ppb = -ppb;
419 }
420
421 /* base freq = 1GHz = 1 000 000 000
422 * ppb_norm = ppb * base_freq / clock_freq;
423 * ppm_norm = ppb_norm / 1000
424 * adj_period = 1 000 000 / ppm_norm
425 * adj_period = 1 000 000 000 / ppb_norm
426 * adj_period = 1 000 000 000 / (ppb * base_freq / clock_freq)
427 * adj_period = (1 000 000 000 * clock_freq) / (ppb * base_freq)
428 * adj_period = clock_freq / ppb
429 */
430 adj_period = div_u64(cpts->refclk_freq, ppb);
431
432 mutex_lock(&cpts->ptp_clk_lock);
433
eb9233ce 434 ctrl_val = am65_cpts_read32(cpts, control);
f6bd5952 435 if (neg_adj)
eb9233ce 436 ctrl_val |= AM65_CPTS_CONTROL_TS_PPM_DIR;
f6bd5952 437 else
eb9233ce
GS		 438 ctrl_val &= ~AM65_CPTS_CONTROL_TS_PPM_DIR;
439
440 ppm_hi = upper_32_bits(adj_period) & 0x3FF;
441 ppm_low = lower_32_bits(adj_period);
442
443 if (cpts->pps_enabled) {
444 pps_ctrl_val = am65_cpts_read32(cpts, genf[pps_index].control);
445 if (neg_adj)
446 pps_ctrl_val &= ~BIT(1);
447 else
448 pps_ctrl_val |= BIT(1);
449
450 /* GenF PPM will do correction using cpts refclk tick which is
451 * (cpts->ts_add_val + 1) ns, so GenF length PPM adj period
452 * need to be corrected.
453 */
454 pps_adj_period = adj_period * (cpts->ts_add_val + 1);
455 pps_ppm_hi = upper_32_bits(pps_adj_period) & 0x3FF;
456 pps_ppm_low = lower_32_bits(pps_adj_period);
457 }
f6bd5952 458
eb9233ce
GS		 459 spin_lock_irqsave(&cpts->lock, flags);
460
461 /* All below writes must be done extremely fast:
462 * - delay between PPM dir and PPM value changes can cause err due old
463 * PPM correction applied in wrong direction
464 * - delay between CPTS-clock PPM cfg and GenF PPM cfg can cause err
465 * due CPTS-clock PPM working with new cfg while GenF PPM cfg still
466 * with old for short period of time
467 */
468
469 am65_cpts_write32(cpts, ctrl_val, control);
470 am65_cpts_write32(cpts, ppm_hi, ts_ppm_hi);
471 am65_cpts_write32(cpts, ppm_low, ts_ppm_low);
472
473 if (cpts->pps_enabled) {
474 am65_cpts_write32(cpts, pps_ctrl_val, genf[pps_index].control);
475 am65_cpts_write32(cpts, pps_ppm_hi, genf[pps_index].ppm_hi);
476 am65_cpts_write32(cpts, pps_ppm_low, genf[pps_index].ppm_low);
477 }
478
479 /* All GenF/EstF can be updated here the same way */
480 spin_unlock_irqrestore(&cpts->lock, flags);
f6bd5952
GS		 481
482 mutex_unlock(&cpts->ptp_clk_lock);
483
484 return 0;
485}
486
487static int am65_cpts_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
488{
489 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
490 s64 ns;
491
492 mutex_lock(&cpts->ptp_clk_lock);
493 ns = am65_cpts_gettime(cpts, NULL);
494 ns += delta;
495 am65_cpts_settime(cpts, ns);
496 mutex_unlock(&cpts->ptp_clk_lock);
497
498 return 0;
499}
500
501static int am65_cpts_ptp_gettimex(struct ptp_clock_info *ptp,
502 struct timespec64 *ts,
503 struct ptp_system_timestamp *sts)
504{
505 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
506 u64 ns;
507
508 mutex_lock(&cpts->ptp_clk_lock);
509 ns = am65_cpts_gettime(cpts, sts);
510 mutex_unlock(&cpts->ptp_clk_lock);
511 *ts = ns_to_timespec64(ns);
512
513 return 0;
514}
515
ec008fa2
IK		 516u64 am65_cpts_ns_gettime(struct am65_cpts *cpts)
517{
518 u64 ns;
519
520 /* reuse ptp_clk_lock as it serialize ts push */
521 mutex_lock(&cpts->ptp_clk_lock);
522 ns = am65_cpts_gettime(cpts, NULL);
523 mutex_unlock(&cpts->ptp_clk_lock);
524
525 return ns;
526}
527EXPORT_SYMBOL_GPL(am65_cpts_ns_gettime);
528
f6bd5952
GS		 529static int am65_cpts_ptp_settime(struct ptp_clock_info *ptp,
530 const struct timespec64 *ts)
531{
532 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
533 u64 ns;
534
535 ns = timespec64_to_ns(ts);
536 mutex_lock(&cpts->ptp_clk_lock);
537 am65_cpts_settime(cpts, ns);
538 mutex_unlock(&cpts->ptp_clk_lock);
539
540 return 0;
541}
542
543static void am65_cpts_extts_enable_hw(struct am65_cpts *cpts, u32 index, int on)
544{
545 u32 v;
546
547 v = am65_cpts_read32(cpts, control);
548 if (on) {
549 v |= BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index);
550 cpts->hw_ts_enable |= BIT(index);
551 } else {
552 v &= ~BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index);
553 cpts->hw_ts_enable &= ~BIT(index);
554 }
555 am65_cpts_write32(cpts, v, control);
556}
557
558static int am65_cpts_extts_enable(struct am65_cpts *cpts, u32 index, int on)
559{
b6d78712
GS		 560 if (index >= cpts->ptp_info.n_ext_ts)
561 return -ENXIO;
562
563 if (cpts->pps_present && index == cpts->pps_hw_ts_idx)
564 return -EINVAL;
565
566 if (((cpts->hw_ts_enable & BIT(index)) >> index) == on)
f6bd5952
GS		 567 return 0;
568
569 mutex_lock(&cpts->ptp_clk_lock);
570 am65_cpts_extts_enable_hw(cpts, index, on);
571 mutex_unlock(&cpts->ptp_clk_lock);
572
573 dev_dbg(cpts->dev, "%s: ExtTS:%u %s\n",
574 __func__, index, on ? "enabled" : "disabled");
575
576 return 0;
577}
578
ec008fa2
IK		 579int am65_cpts_estf_enable(struct am65_cpts *cpts, int idx,
580 struct am65_cpts_estf_cfg *cfg)
581{
582 u64 cycles;
583 u32 val;
584
585 cycles = cfg->ns_period * cpts->refclk_freq;
586 cycles = DIV_ROUND_UP(cycles, NSEC_PER_SEC);
587 if (cycles > U32_MAX)
588 return -EINVAL;
589
590 /* according to TRM should be zeroed */
591 am65_cpts_write32(cpts, 0, estf[idx].length);
592
593 val = upper_32_bits(cfg->ns_start);
594 am65_cpts_write32(cpts, val, estf[idx].comp_hi);
595 val = lower_32_bits(cfg->ns_start);
596 am65_cpts_write32(cpts, val, estf[idx].comp_lo);
597 val = lower_32_bits(cycles);
598 am65_cpts_write32(cpts, val, estf[idx].length);
599
600 dev_dbg(cpts->dev, "%s: ESTF:%u enabled\n", __func__, idx);
601
602 return 0;
603}
604EXPORT_SYMBOL_GPL(am65_cpts_estf_enable);
605
606void am65_cpts_estf_disable(struct am65_cpts *cpts, int idx)
607{
608 am65_cpts_write32(cpts, 0, estf[idx].length);
609
610 dev_dbg(cpts->dev, "%s: ESTF:%u disabled\n", __func__, idx);
611}
612EXPORT_SYMBOL_GPL(am65_cpts_estf_disable);
613
f6bd5952
GS		 614static void am65_cpts_perout_enable_hw(struct am65_cpts *cpts,
615 struct ptp_perout_request *req, int on)
616{
617 u64 ns_period, ns_start, cycles;
618 struct timespec64 ts;
619 u32 val;
620
621 if (on) {
622 ts.tv_sec = req->period.sec;
623 ts.tv_nsec = req->period.nsec;
624 ns_period = timespec64_to_ns(&ts);
625
626 cycles = (ns_period * cpts->refclk_freq) / NSEC_PER_SEC;
627
628 ts.tv_sec = req->start.sec;
629 ts.tv_nsec = req->start.nsec;
630 ns_start = timespec64_to_ns(&ts);
631
632 val = upper_32_bits(ns_start);
633 am65_cpts_write32(cpts, val, genf[req->index].comp_hi);
634 val = lower_32_bits(ns_start);
635 am65_cpts_write32(cpts, val, genf[req->index].comp_lo);
636 val = lower_32_bits(cycles);
637 am65_cpts_write32(cpts, val, genf[req->index].length);
638
639 cpts->genf_enable |= BIT(req->index);
640 } else {
641 am65_cpts_write32(cpts, 0, genf[req->index].length);
642
643 cpts->genf_enable &= ~BIT(req->index);
644 }
645}
646
647static int am65_cpts_perout_enable(struct am65_cpts *cpts,
648 struct ptp_perout_request *req, int on)
649{
b6d78712
GS		 650 if (req->index >= cpts->ptp_info.n_per_out)
651 return -ENXIO;
652
653 if (cpts->pps_present && req->index == cpts->pps_genf_idx)
654 return -EINVAL;
655
f6bd5952
GS		 656 if (!!(cpts->genf_enable & BIT(req->index)) == !!on)
657 return 0;
658
659 mutex_lock(&cpts->ptp_clk_lock);
660 am65_cpts_perout_enable_hw(cpts, req, on);
661 mutex_unlock(&cpts->ptp_clk_lock);
662
663 dev_dbg(cpts->dev, "%s: GenF:%u %s\n",
664 __func__, req->index, on ? "enabled" : "disabled");
665
666 return 0;
667}
668
b6d78712
GS		 669static int am65_cpts_pps_enable(struct am65_cpts *cpts, int on)
670{
671 int ret = 0;
672 struct timespec64 ts;
673 struct ptp_clock_request rq;
674 u64 ns;
675
676 if (!cpts->pps_present)
677 return -EINVAL;
678
679 if (cpts->pps_enabled == !!on)
680 return 0;
681
682 mutex_lock(&cpts->ptp_clk_lock);
683
684 if (on) {
685 am65_cpts_extts_enable_hw(cpts, cpts->pps_hw_ts_idx, on);
686
687 ns = am65_cpts_gettime(cpts, NULL);
688 ts = ns_to_timespec64(ns);
689 rq.perout.period.sec = 1;
690 rq.perout.period.nsec = 0;
691 rq.perout.start.sec = ts.tv_sec + 2;
692 rq.perout.start.nsec = 0;
693 rq.perout.index = cpts->pps_genf_idx;
694
695 am65_cpts_perout_enable_hw(cpts, &rq.perout, on);
696 cpts->pps_enabled = true;
697 } else {
698 rq.perout.index = cpts->pps_genf_idx;
699 am65_cpts_perout_enable_hw(cpts, &rq.perout, on);
700 am65_cpts_extts_enable_hw(cpts, cpts->pps_hw_ts_idx, on);
701 cpts->pps_enabled = false;
702 }
703
704 mutex_unlock(&cpts->ptp_clk_lock);
705
706 dev_dbg(cpts->dev, "%s: pps: %s\n",
707 __func__, on ? "enabled" : "disabled");
708 return ret;
709}
710
f6bd5952
GS		 711static int am65_cpts_ptp_enable(struct ptp_clock_info *ptp,
712 struct ptp_clock_request *rq, int on)
713{
714 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
715
716 switch (rq->type) {
717 case PTP_CLK_REQ_EXTTS:
718 return am65_cpts_extts_enable(cpts, rq->extts.index, on);
719 case PTP_CLK_REQ_PEROUT:
720 return am65_cpts_perout_enable(cpts, &rq->perout, on);
b6d78712
GS		 721 case PTP_CLK_REQ_PPS:
722 return am65_cpts_pps_enable(cpts, on);
f6bd5952
GS		 723 default:
724 break;
725 }
726
727 return -EOPNOTSUPP;
728}
729
730static long am65_cpts_ts_work(struct ptp_clock_info *ptp);
731
732static struct ptp_clock_info am65_ptp_info = {
733 .owner = THIS_MODULE,
734 .name = "CTPS timer",
e2bd9c76 735 .adjfine = am65_cpts_ptp_adjfine,
f6bd5952
GS		 736 .adjtime = am65_cpts_ptp_adjtime,
737 .gettimex64 = am65_cpts_ptp_gettimex,
738 .settime64 = am65_cpts_ptp_settime,
739 .enable = am65_cpts_ptp_enable,
740 .do_aux_work = am65_cpts_ts_work,
741};
742
743static bool am65_cpts_match_tx_ts(struct am65_cpts *cpts,
744 struct am65_cpts_event *event)
745{
746 struct sk_buff_head txq_list;
747 struct sk_buff *skb, *tmp;
748 unsigned long flags;
749 bool found = false;
750 u32 mtype_seqid;
751
752 mtype_seqid = event->event1 &
753 (AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK |
754 AM65_CPTS_EVENT_1_EVENT_TYPE_MASK |
755 AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK);
756
757 __skb_queue_head_init(&txq_list);
758
759 spin_lock_irqsave(&cpts->txq.lock, flags);
760 skb_queue_splice_init(&cpts->txq, &txq_list);
761 spin_unlock_irqrestore(&cpts->txq.lock, flags);
762
763 /* no need to grab txq.lock as access is always done under cpts->lock */
764 skb_queue_walk_safe(&txq_list, skb, tmp) {
765 struct skb_shared_hwtstamps ssh;
766 struct am65_cpts_skb_cb_data *skb_cb =
767 (struct am65_cpts_skb_cb_data *)skb->cb;
768
769 if (mtype_seqid == skb_cb->skb_mtype_seqid) {
770 u64 ns = event->timestamp;
771
772 memset(&ssh, 0, sizeof(ssh));
773 ssh.hwtstamp = ns_to_ktime(ns);
774 skb_tstamp_tx(skb, &ssh);
775 found = true;
776 __skb_unlink(skb, &txq_list);
777 dev_consume_skb_any(skb);
778 dev_dbg(cpts->dev,
779 "match tx timestamp mtype_seqid %08x\n",
780 mtype_seqid);
781 break;
782 }
783
784 if (time_after(jiffies, skb_cb->tmo)) {
785 /* timeout any expired skbs over 100 ms */
786 dev_dbg(cpts->dev,
787 "expiring tx timestamp mtype_seqid %08x\n",
788 mtype_seqid);
789 __skb_unlink(skb, &txq_list);
790 dev_consume_skb_any(skb);
791 }
792 }
793
794 spin_lock_irqsave(&cpts->txq.lock, flags);
795 skb_queue_splice(&txq_list, &cpts->txq);
796 spin_unlock_irqrestore(&cpts->txq.lock, flags);
797
798 return found;
799}
800
801static void am65_cpts_find_ts(struct am65_cpts *cpts)
802{
803 struct am65_cpts_event *event;
804 struct list_head *this, *next;
805 LIST_HEAD(events_free);
806 unsigned long flags;
807 LIST_HEAD(events);
808
809 spin_lock_irqsave(&cpts->lock, flags);
810 list_splice_init(&cpts->events, &events);
811 spin_unlock_irqrestore(&cpts->lock, flags);
812
813 list_for_each_safe(this, next, &events) {
814 event = list_entry(this, struct am65_cpts_event, list);
815 if (am65_cpts_match_tx_ts(cpts, event) ||
816 time_after(jiffies, event->tmo)) {
817 list_del_init(&event->list);
818 list_add(&event->list, &events_free);
819 }
820 }
821
822 spin_lock_irqsave(&cpts->lock, flags);
823 list_splice_tail(&events, &cpts->events);
824 list_splice_tail(&events_free, &cpts->pool);
825 spin_unlock_irqrestore(&cpts->lock, flags);
826}
827
828static long am65_cpts_ts_work(struct ptp_clock_info *ptp)
829{
830 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
831 unsigned long flags;
832 long delay = -1;
833
834 am65_cpts_find_ts(cpts);
835
836 spin_lock_irqsave(&cpts->txq.lock, flags);
837 if (!skb_queue_empty(&cpts->txq))
838 delay = AM65_CPTS_SKB_TX_WORK_TIMEOUT;
839 spin_unlock_irqrestore(&cpts->txq.lock, flags);
840
841 return delay;
842}
843
844/**
845 * am65_cpts_rx_enable - enable rx timestamping
846 * @cpts: cpts handle
e49e4647 847 * @en: enable
f6bd5952
GS		 848 *
849 * This functions enables rx packets timestamping. The CPTS can timestamp all
850 * rx packets.
851 */
852void am65_cpts_rx_enable(struct am65_cpts *cpts, bool en)
853{
854 u32 val;
855
856 mutex_lock(&cpts->ptp_clk_lock);
857 val = am65_cpts_read32(cpts, control);
858 if (en)
859 val |= AM65_CPTS_CONTROL_TSTAMP_EN;
860 else
861 val &= ~AM65_CPTS_CONTROL_TSTAMP_EN;
862 am65_cpts_write32(cpts, val, control);
863 mutex_unlock(&cpts->ptp_clk_lock);
864}
865EXPORT_SYMBOL_GPL(am65_cpts_rx_enable);
866
867static int am65_skb_get_mtype_seqid(struct sk_buff *skb, u32 *mtype_seqid)
868{
869 unsigned int ptp_class = ptp_classify_raw(skb);
4bccb5d0
KK		 870 struct ptp_header *hdr;
871 u8 msgtype;
872 u16 seqid;
f6bd5952
GS		 873
874 if (ptp_class == PTP_CLASS_NONE)
875 return 0;
876
4bccb5d0
KK		 877 hdr = ptp_parse_header(skb, ptp_class);
878 if (!hdr)
f6bd5952
GS		 879 return 0;
880
4bccb5d0
KK		 881 msgtype = ptp_get_msgtype(hdr, ptp_class);
882 seqid = ntohs(hdr->sequence_id);
f6bd5952 883
4bccb5d0 884 *mtype_seqid = (msgtype << AM65_CPTS_EVENT_1_MESSAGE_TYPE_SHIFT) &
f6bd5952 885 AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK;
4bccb5d0 886 *mtype_seqid |= (seqid & AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK);
f6bd5952
GS		 887
888 return 1;
889}
890
891/**
892 * am65_cpts_tx_timestamp - save tx packet for timestamping
893 * @cpts: cpts handle
894 * @skb: packet
895 *
896 * This functions saves tx packet for timestamping if packet can be timestamped.
897 * The future processing is done in from PTP auxiliary worker.
898 */
899void am65_cpts_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb)
900{
901 struct am65_cpts_skb_cb_data *skb_cb = (void *)skb->cb;
902
903 if (!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
904 return;
905
906 /* add frame to queue for processing later.
907 * The periodic FIFO check will handle this.
908 */
909 skb_get(skb);
910 /* get the timestamp for timeouts */
911 skb_cb->tmo = jiffies + msecs_to_jiffies(100);
912 skb_queue_tail(&cpts->txq, skb);
913 ptp_schedule_worker(cpts->ptp_clock, 0);
914}
915EXPORT_SYMBOL_GPL(am65_cpts_tx_timestamp);
916
917/**
918 * am65_cpts_prep_tx_timestamp - check and prepare tx packet for timestamping
919 * @cpts: cpts handle
920 * @skb: packet
921 *
922 * This functions should be called from .xmit().
923 * It checks if packet can be timestamped, fills internal cpts data
924 * in skb-cb and marks packet as SKBTX_IN_PROGRESS.
925 */
926void am65_cpts_prep_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb)
927{
928 struct am65_cpts_skb_cb_data *skb_cb = (void *)skb->cb;
929 int ret;
930
931 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
932 return;
933
934 ret = am65_skb_get_mtype_seqid(skb, &skb_cb->skb_mtype_seqid);
935 if (!ret)
936 return;
937 skb_cb->skb_mtype_seqid |= (AM65_CPTS_EV_TX <<
938 AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT);
939
940 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
941}
942EXPORT_SYMBOL_GPL(am65_cpts_prep_tx_timestamp);
943
944int am65_cpts_phc_index(struct am65_cpts *cpts)
945{
946 return cpts->phc_index;
947}
948EXPORT_SYMBOL_GPL(am65_cpts_phc_index);
949
950static void cpts_free_clk_mux(void *data)
951{
952 struct am65_cpts *cpts = data;
953
954 of_clk_del_provider(cpts->clk_mux_np);
955 clk_hw_unregister_mux(cpts->clk_mux_hw);
956 of_node_put(cpts->clk_mux_np);
957}
958
959static int cpts_of_mux_clk_setup(struct am65_cpts *cpts,
960 struct device_node *node)
961{
962 unsigned int num_parents;
963 const char **parent_names;
964 char *clk_mux_name;
965 void __iomem *reg;
966 int ret = -EINVAL;
967
968 cpts->clk_mux_np = of_get_child_by_name(node, "refclk-mux");
969 if (!cpts->clk_mux_np)
970 return 0;
971
972 num_parents = of_clk_get_parent_count(cpts->clk_mux_np);
973 if (num_parents < 1) {
974 dev_err(cpts->dev, "mux-clock %pOF must have parents\n",
975 cpts->clk_mux_np);
976 goto mux_fail;
977 }
978
979 parent_names = devm_kcalloc(cpts->dev, sizeof(char *), num_parents,
980 GFP_KERNEL);
981 if (!parent_names) {
982 ret = -ENOMEM;
983 goto mux_fail;
984 }
985
986 of_clk_parent_fill(cpts->clk_mux_np, parent_names, num_parents);
987
988 clk_mux_name = devm_kasprintf(cpts->dev, GFP_KERNEL, "%s.%pOFn",
989 dev_name(cpts->dev), cpts->clk_mux_np);
990 if (!clk_mux_name) {
991 ret = -ENOMEM;
992 goto mux_fail;
993 }
994
995 reg = &cpts->reg->rftclk_sel;
996 /* dev must be NULL to avoid recursive incrementing
997 * of module refcnt
998 */
999 cpts->clk_mux_hw = clk_hw_register_mux(NULL, clk_mux_name,
1000 parent_names, num_parents,
1001 0, reg, 0, 5, 0, NULL);
1002 if (IS_ERR(cpts->clk_mux_hw)) {
1003 ret = PTR_ERR(cpts->clk_mux_hw);
1004 goto mux_fail;
1005 }
1006
1007 ret = of_clk_add_hw_provider(cpts->clk_mux_np, of_clk_hw_simple_get,
1008 cpts->clk_mux_hw);
1009 if (ret)
1010 goto clk_hw_register;
1011
1012 ret = devm_add_action_or_reset(cpts->dev, cpts_free_clk_mux, cpts);
1013 if (ret)
1014 dev_err(cpts->dev, "failed to add clkmux reset action %d", ret);
1015
1016 return ret;
1017
1018clk_hw_register:
1019 clk_hw_unregister_mux(cpts->clk_mux_hw);
1020mux_fail:
1021 of_node_put(cpts->clk_mux_np);
1022 return ret;
1023}
1024
1025static int am65_cpts_of_parse(struct am65_cpts *cpts, struct device_node *node)
1026{
1027 u32 prop[2];
1028
1029 if (!of_property_read_u32(node, "ti,cpts-ext-ts-inputs", &prop[0]))
1030 cpts->ext_ts_inputs = prop[0];
1031
1032 if (!of_property_read_u32(node, "ti,cpts-periodic-outputs", &prop[0]))
1033 cpts->genf_num = prop[0];
1034
b6d78712
GS		 1035 if (!of_property_read_u32_array(node, "ti,pps", prop, 2)) {
1036 cpts->pps_present = true;
1037
1038 if (prop[0] > 7) {
1039 dev_err(cpts->dev, "invalid HWx_TS_PUSH index: %u provided\n", prop[0]);
1040 cpts->pps_present = false;
1041 }
1042 if (prop[1] > 1) {
1043 dev_err(cpts->dev, "invalid GENFy index: %u provided\n", prop[1]);
1044 cpts->pps_present = false;
1045 }
1046 if (cpts->pps_present) {
1047 cpts->pps_hw_ts_idx = prop[0];
1048 cpts->pps_genf_idx = prop[1];
1049 }
1050 }
1051
f6bd5952
GS		 1052 return cpts_of_mux_clk_setup(cpts, node);
1053}
1054
1055static void am65_cpts_release(void *data)
1056{
1057 struct am65_cpts *cpts = data;
1058
1059 ptp_clock_unregister(cpts->ptp_clock);
1060 am65_cpts_disable(cpts);
1061 clk_disable_unprepare(cpts->refclk);
1062}
1063
1064struct am65_cpts *am65_cpts_create(struct device *dev, void __iomem *regs,
1065 struct device_node *node)
1066{
1067 struct am65_cpts *cpts;
1068 int ret, i;
1069
1070 cpts = devm_kzalloc(dev, sizeof(*cpts), GFP_KERNEL);
1071 if (!cpts)
1072 return ERR_PTR(-ENOMEM);
1073
1074 cpts->dev = dev;
1075 cpts->reg = (struct am65_cpts_regs __iomem *)regs;
1076
1077 cpts->irq = of_irq_get_byname(node, "cpts");
1078 if (cpts->irq <= 0) {
1079 ret = cpts->irq ?: -ENXIO;
e2baa126 1080 dev_err_probe(dev, ret, "Failed to get IRQ number\n");
f6bd5952
GS		 1081 return ERR_PTR(ret);
1082 }
1083
1084 ret = am65_cpts_of_parse(cpts, node);
1085 if (ret)
1086 return ERR_PTR(ret);
1087
1088 mutex_init(&cpts->ptp_clk_lock);
1089 INIT_LIST_HEAD(&cpts->events);
1090 INIT_LIST_HEAD(&cpts->pool);
1091 spin_lock_init(&cpts->lock);
1092 skb_queue_head_init(&cpts->txq);
1093
1094 for (i = 0; i < AM65_CPTS_MAX_EVENTS; i++)
1095 list_add(&cpts->pool_data[i].list, &cpts->pool);
1096
1097 cpts->refclk = devm_get_clk_from_child(dev, node, "cpts");
1098 if (IS_ERR(cpts->refclk)) {
1099 ret = PTR_ERR(cpts->refclk);
e2baa126 1100 dev_err_probe(dev, ret, "Failed to get refclk\n");
f6bd5952
GS		 1101 return ERR_PTR(ret);
1102 }
1103
1104 ret = clk_prepare_enable(cpts->refclk);
1105 if (ret) {
1106 dev_err(dev, "Failed to enable refclk %d\n", ret);
1107 return ERR_PTR(ret);
1108 }
1109
1110 cpts->refclk_freq = clk_get_rate(cpts->refclk);
1111
1112 am65_ptp_info.max_adj = cpts->refclk_freq / AM65_CPTS_MIN_PPM;
1113 cpts->ptp_info = am65_ptp_info;
1114
1115 if (cpts->ext_ts_inputs)
1116 cpts->ptp_info.n_ext_ts = cpts->ext_ts_inputs;
1117 if (cpts->genf_num)
1118 cpts->ptp_info.n_per_out = cpts->genf_num;
b6d78712
GS		 1119 if (cpts->pps_present)
1120 cpts->ptp_info.pps = 1;
f6bd5952
GS		 1121
1122 am65_cpts_set_add_val(cpts);
1123
4d4dce31
GS		 1124 am65_cpts_write32(cpts, AM65_CPTS_CONTROL_EN |
1125 AM65_CPTS_CONTROL_64MODE |
1126 AM65_CPTS_CONTROL_TX_GENF_CLR_EN,
f6bd5952
GS		 1127 control);
1128 am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable);
1129
1130 /* set time to the current system time */
1131 am65_cpts_settime(cpts, ktime_to_ns(ktime_get_real()));
1132
1133 cpts->ptp_clock = ptp_clock_register(&cpts->ptp_info, cpts->dev);
1134 if (IS_ERR_OR_NULL(cpts->ptp_clock)) {
1135 dev_err(dev, "Failed to register ptp clk %ld\n",
1136 PTR_ERR(cpts->ptp_clock));
81e329e9 1137 ret = cpts->ptp_clock ? PTR_ERR(cpts->ptp_clock) : -ENODEV;
f6bd5952
GS		 1138 goto refclk_disable;
1139 }
1140 cpts->phc_index = ptp_clock_index(cpts->ptp_clock);
1141
1142 ret = devm_add_action_or_reset(dev, am65_cpts_release, cpts);
1143 if (ret) {
1144 dev_err(dev, "failed to add ptpclk reset action %d", ret);
1145 return ERR_PTR(ret);
1146 }
1147
1148 ret = devm_request_threaded_irq(dev, cpts->irq, NULL,
1149 am65_cpts_interrupt,
1150 IRQF_ONESHOT, dev_name(dev), cpts);
1151 if (ret < 0) {
1152 dev_err(cpts->dev, "error attaching irq %d\n", ret);
1153 return ERR_PTR(ret);
1154 }
1155
b6d78712 1156 dev_info(dev, "CPTS ver 0x%08x, freq:%u, add_val:%u pps:%d\n",
f6bd5952 1157 am65_cpts_read32(cpts, idver),
b6d78712 1158 cpts->refclk_freq, cpts->ts_add_val, cpts->pps_present);
f6bd5952
GS		 1159
1160 return cpts;
1161
1162refclk_disable:
1163 clk_disable_unprepare(cpts->refclk);
1164 return ERR_PTR(ret);
1165}
1166EXPORT_SYMBOL_GPL(am65_cpts_create);
1167
cef122d4
RQ		 1168void am65_cpts_suspend(struct am65_cpts *cpts)
1169{
1170 /* save state and disable CPTS */
1171 cpts->sr_control = am65_cpts_read32(cpts, control);
1172 cpts->sr_int_enable = am65_cpts_read32(cpts, int_enable);
1173 cpts->sr_rftclk_sel = am65_cpts_read32(cpts, rftclk_sel);
1174 cpts->sr_ts_ppm_hi = am65_cpts_read32(cpts, ts_ppm_hi);
1175 cpts->sr_ts_ppm_low = am65_cpts_read32(cpts, ts_ppm_low);
1176 cpts->sr_cpts_ns = am65_cpts_gettime(cpts, NULL);
1177 cpts->sr_ktime_ns = ktime_to_ns(ktime_get_real());
1178 am65_cpts_disable(cpts);
1179 clk_disable(cpts->refclk);
1180
1181 /* Save GENF state */
1182 memcpy_fromio(&cpts->sr_genf, &cpts->reg->genf, sizeof(cpts->sr_genf));
1183
1184 /* Save ESTF state */
1185 memcpy_fromio(&cpts->sr_estf, &cpts->reg->estf, sizeof(cpts->sr_estf));
1186}
1187EXPORT_SYMBOL_GPL(am65_cpts_suspend);
1188
1189void am65_cpts_resume(struct am65_cpts *cpts)
1190{
1191 int i;
1192 s64 ktime_ns;
1193
1194 /* restore state and enable CPTS */
1195 clk_enable(cpts->refclk);
1196 am65_cpts_write32(cpts, cpts->sr_rftclk_sel, rftclk_sel);
1197 am65_cpts_set_add_val(cpts);
1198 am65_cpts_write32(cpts, cpts->sr_control, control);
1199 am65_cpts_write32(cpts, cpts->sr_int_enable, int_enable);
1200
1201 /* Restore time to saved CPTS time + time in suspend/resume */
1202 ktime_ns = ktime_to_ns(ktime_get_real());
1203 ktime_ns -= cpts->sr_ktime_ns;
1204 am65_cpts_settime(cpts, cpts->sr_cpts_ns + ktime_ns);
1205
1206 /* Restore compensation (PPM) */
1207 am65_cpts_write32(cpts, cpts->sr_ts_ppm_hi, ts_ppm_hi);
1208 am65_cpts_write32(cpts, cpts->sr_ts_ppm_low, ts_ppm_low);
1209
1210 /* Restore GENF state */
1211 for (i = 0; i < AM65_CPTS_GENF_MAX_NUM; i++) {
1212 am65_cpts_write32(cpts, 0, genf[i].length); /* TRM sequence */
1213 am65_cpts_write32(cpts, cpts->sr_genf[i].comp_hi, genf[i].comp_hi);
1214 am65_cpts_write32(cpts, cpts->sr_genf[i].comp_lo, genf[i].comp_lo);
1215 am65_cpts_write32(cpts, cpts->sr_genf[i].length, genf[i].length);
1216 am65_cpts_write32(cpts, cpts->sr_genf[i].control, genf[i].control);
1217 am65_cpts_write32(cpts, cpts->sr_genf[i].ppm_hi, genf[i].ppm_hi);
1218 am65_cpts_write32(cpts, cpts->sr_genf[i].ppm_low, genf[i].ppm_low);
1219 }
1220
1221 /* Restore ESTTF state */
1222 for (i = 0; i < AM65_CPTS_ESTF_MAX_NUM; i++) {
1223 am65_cpts_write32(cpts, 0, estf[i].length); /* TRM sequence */
1224 am65_cpts_write32(cpts, cpts->sr_estf[i].comp_hi, estf[i].comp_hi);
1225 am65_cpts_write32(cpts, cpts->sr_estf[i].comp_lo, estf[i].comp_lo);
1226 am65_cpts_write32(cpts, cpts->sr_estf[i].length, estf[i].length);
1227 am65_cpts_write32(cpts, cpts->sr_estf[i].control, estf[i].control);
1228 am65_cpts_write32(cpts, cpts->sr_estf[i].ppm_hi, estf[i].ppm_hi);
1229 am65_cpts_write32(cpts, cpts->sr_estf[i].ppm_low, estf[i].ppm_low);
1230 }
1231}
1232EXPORT_SYMBOL_GPL(am65_cpts_resume);
1233
f6bd5952
GS		 1234static int am65_cpts_probe(struct platform_device *pdev)
1235{
1236 struct device_node *node = pdev->dev.of_node;
1237 struct device *dev = &pdev->dev;
1238 struct am65_cpts *cpts;
f6bd5952
GS		 1239 void __iomem *base;
1240
e77e2cf4 1241 base = devm_platform_ioremap_resource_byname(pdev, "cpts");
f6bd5952
GS		 1242 if (IS_ERR(base))
1243 return PTR_ERR(base);
1244
1245 cpts = am65_cpts_create(dev, base, node);
bbae62e3 1246 return PTR_ERR_OR_ZERO(cpts);
f6bd5952
GS		 1247}
1248
1249static const struct of_device_id am65_cpts_of_match[] = {
1250 { .compatible = "ti,am65-cpts", },
1251 { .compatible = "ti,j721e-cpts", },
1252 {},
1253};
1254MODULE_DEVICE_TABLE(of, am65_cpts_of_match);
1255
1256static struct platform_driver am65_cpts_driver = {
1257 .probe = am65_cpts_probe,
1258 .driver = {
1259 .name = "am65-cpts",
1260 .of_match_table = am65_cpts_of_match,
1261 },
1262};
1263module_platform_driver(am65_cpts_driver);
1264
1265MODULE_LICENSE("GPL v2");
1266MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>");
1267MODULE_DESCRIPTION("TI K3 AM65 CPTS driver");
Linux 6.x block layer and io_uring tree(s)