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dt-binding: net: ti: am65x-cpts: add 'ti,pps' property
[linux-2.6-block.git] / drivers / net / ethernet / ti / am65-cpts.c
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f6bd5952
GS		 1// SPDX-License-Identifier: GPL-2.0
2/* TI K3 AM65x Common Platform Time Sync
3 *
4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
5 *
6 */
7
8#include <linux/clk.h>
9#include <linux/clk-provider.h>
10#include <linux/err.h>
11#include <linux/if_vlan.h>
12#include <linux/interrupt.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/net_tstamp.h>
16#include <linux/of.h>
17#include <linux/of_irq.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/ptp_classify.h>
21#include <linux/ptp_clock_kernel.h>
22
23#include "am65-cpts.h"
24
25struct am65_genf_regs {
26 u32 comp_lo; /* Comparison Low Value 0:31 */
27 u32 comp_hi; /* Comparison High Value 32:63 */
28 u32 control; /* control */
29 u32 length; /* Length */
30 u32 ppm_low; /* PPM Load Low Value 0:31 */
31 u32 ppm_hi; /* PPM Load High Value 32:63 */
32 u32 ts_nudge; /* Nudge value */
33} __aligned(32) __packed;
34
35#define AM65_CPTS_GENF_MAX_NUM 9
36#define AM65_CPTS_ESTF_MAX_NUM 8
37
38struct am65_cpts_regs {
39 u32 idver; /* Identification and version */
40 u32 control; /* Time sync control */
41 u32 rftclk_sel; /* Reference Clock Select Register */
42 u32 ts_push; /* Time stamp event push */
43 u32 ts_load_val_lo; /* Time Stamp Load Low Value 0:31 */
44 u32 ts_load_en; /* Time stamp load enable */
45 u32 ts_comp_lo; /* Time Stamp Comparison Low Value 0:31 */
46 u32 ts_comp_length; /* Time Stamp Comparison Length */
47 u32 intstat_raw; /* Time sync interrupt status raw */
48 u32 intstat_masked; /* Time sync interrupt status masked */
49 u32 int_enable; /* Time sync interrupt enable */
50 u32 ts_comp_nudge; /* Time Stamp Comparison Nudge Value */
51 u32 event_pop; /* Event interrupt pop */
52 u32 event_0; /* Event Time Stamp lo 0:31 */
53 u32 event_1; /* Event Type Fields */
54 u32 event_2; /* Event Type Fields domain */
55 u32 event_3; /* Event Time Stamp hi 32:63 */
56 u32 ts_load_val_hi; /* Time Stamp Load High Value 32:63 */
57 u32 ts_comp_hi; /* Time Stamp Comparison High Value 32:63 */
58 u32 ts_add_val; /* Time Stamp Add value */
59 u32 ts_ppm_low; /* Time Stamp PPM Load Low Value 0:31 */
60 u32 ts_ppm_hi; /* Time Stamp PPM Load High Value 32:63 */
61 u32 ts_nudge; /* Time Stamp Nudge value */
62 u32 reserv[33];
63 struct am65_genf_regs genf[AM65_CPTS_GENF_MAX_NUM];
64 struct am65_genf_regs estf[AM65_CPTS_ESTF_MAX_NUM];
65};
66
67/* CONTROL_REG */
68#define AM65_CPTS_CONTROL_EN BIT(0)
69#define AM65_CPTS_CONTROL_INT_TEST BIT(1)
70#define AM65_CPTS_CONTROL_TS_COMP_POLARITY BIT(2)
71#define AM65_CPTS_CONTROL_TSTAMP_EN BIT(3)
72#define AM65_CPTS_CONTROL_SEQUENCE_EN BIT(4)
73#define AM65_CPTS_CONTROL_64MODE BIT(5)
74#define AM65_CPTS_CONTROL_TS_COMP_TOG BIT(6)
75#define AM65_CPTS_CONTROL_TS_PPM_DIR BIT(7)
76#define AM65_CPTS_CONTROL_HW1_TS_PUSH_EN BIT(8)
77#define AM65_CPTS_CONTROL_HW2_TS_PUSH_EN BIT(9)
78#define AM65_CPTS_CONTROL_HW3_TS_PUSH_EN BIT(10)
79#define AM65_CPTS_CONTROL_HW4_TS_PUSH_EN BIT(11)
80#define AM65_CPTS_CONTROL_HW5_TS_PUSH_EN BIT(12)
81#define AM65_CPTS_CONTROL_HW6_TS_PUSH_EN BIT(13)
82#define AM65_CPTS_CONTROL_HW7_TS_PUSH_EN BIT(14)
83#define AM65_CPTS_CONTROL_HW8_TS_PUSH_EN BIT(15)
84#define AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET (8)
85
4d4dce31
GS		 86#define AM65_CPTS_CONTROL_TX_GENF_CLR_EN BIT(17)
87
f6bd5952
GS		 88#define AM65_CPTS_CONTROL_TS_SYNC_SEL_MASK (0xF)
89#define AM65_CPTS_CONTROL_TS_SYNC_SEL_SHIFT (28)
90
91/* RFTCLK_SEL_REG */
92#define AM65_CPTS_RFTCLK_SEL_MASK (0x1F)
93
94/* TS_PUSH_REG */
95#define AM65_CPTS_TS_PUSH BIT(0)
96
97/* TS_LOAD_EN_REG */
98#define AM65_CPTS_TS_LOAD_EN BIT(0)
99
100/* INTSTAT_RAW_REG */
101#define AM65_CPTS_INTSTAT_RAW_TS_PEND BIT(0)
102
103/* INTSTAT_MASKED_REG */
104#define AM65_CPTS_INTSTAT_MASKED_TS_PEND BIT(0)
105
106/* INT_ENABLE_REG */
107#define AM65_CPTS_INT_ENABLE_TS_PEND_EN BIT(0)
108
109/* TS_COMP_NUDGE_REG */
110#define AM65_CPTS_TS_COMP_NUDGE_MASK (0xFF)
111
112/* EVENT_POP_REG */
113#define AM65_CPTS_EVENT_POP BIT(0)
114
115/* EVENT_1_REG */
116#define AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK GENMASK(15, 0)
117
118#define AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK GENMASK(19, 16)
119#define AM65_CPTS_EVENT_1_MESSAGE_TYPE_SHIFT (16)
120
121#define AM65_CPTS_EVENT_1_EVENT_TYPE_MASK GENMASK(23, 20)
122#define AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT (20)
123
124#define AM65_CPTS_EVENT_1_PORT_NUMBER_MASK GENMASK(28, 24)
125#define AM65_CPTS_EVENT_1_PORT_NUMBER_SHIFT (24)
126
127/* EVENT_2_REG */
128#define AM65_CPTS_EVENT_2_REG_DOMAIN_MASK (0xFF)
129#define AM65_CPTS_EVENT_2_REG_DOMAIN_SHIFT (0)
130
131enum {
132 AM65_CPTS_EV_PUSH, /* Time Stamp Push Event */
133 AM65_CPTS_EV_ROLL, /* Time Stamp Rollover Event */
134 AM65_CPTS_EV_HALF, /* Time Stamp Half Rollover Event */
135 AM65_CPTS_EV_HW, /* Hardware Time Stamp Push Event */
136 AM65_CPTS_EV_RX, /* Ethernet Receive Event */
137 AM65_CPTS_EV_TX, /* Ethernet Transmit Event */
138 AM65_CPTS_EV_TS_COMP, /* Time Stamp Compare Event */
139 AM65_CPTS_EV_HOST, /* Host Transmit Event */
140};
141
142struct am65_cpts_event {
143 struct list_head list;
144 unsigned long tmo;
145 u32 event1;
146 u32 event2;
147 u64 timestamp;
148};
149
150#define AM65_CPTS_FIFO_DEPTH (16)
151#define AM65_CPTS_MAX_EVENTS (32)
152#define AM65_CPTS_EVENT_RX_TX_TIMEOUT (20) /* ms */
153#define AM65_CPTS_SKB_TX_WORK_TIMEOUT 1 /* jiffies */
154#define AM65_CPTS_MIN_PPM 0x400
155
156struct am65_cpts {
157 struct device *dev;
158 struct am65_cpts_regs __iomem *reg;
159 struct ptp_clock_info ptp_info;
160 struct ptp_clock *ptp_clock;
161 int phc_index;
162 struct clk_hw *clk_mux_hw;
163 struct device_node *clk_mux_np;
164 struct clk *refclk;
165 u32 refclk_freq;
166 struct list_head events;
167 struct list_head pool;
168 struct am65_cpts_event pool_data[AM65_CPTS_MAX_EVENTS];
169 spinlock_t lock; /* protects events lists*/
170 u32 ext_ts_inputs;
171 u32 genf_num;
172 u32 ts_add_val;
173 int irq;
174 struct mutex ptp_clk_lock; /* PHC access sync */
175 u64 timestamp;
176 u32 genf_enable;
177 u32 hw_ts_enable;
178 struct sk_buff_head txq;
cef122d4
RQ		 179 /* context save/restore */
180 u64 sr_cpts_ns;
181 u64 sr_ktime_ns;
182 u32 sr_control;
183 u32 sr_int_enable;
184 u32 sr_rftclk_sel;
185 u32 sr_ts_ppm_hi;
186 u32 sr_ts_ppm_low;
187 struct am65_genf_regs sr_genf[AM65_CPTS_GENF_MAX_NUM];
188 struct am65_genf_regs sr_estf[AM65_CPTS_ESTF_MAX_NUM];
f6bd5952
GS		 189};
190
191struct am65_cpts_skb_cb_data {
192 unsigned long tmo;
193 u32 skb_mtype_seqid;
194};
195
196#define am65_cpts_write32(c, v, r) writel(v, &(c)->reg->r)
197#define am65_cpts_read32(c, r) readl(&(c)->reg->r)
198
199static void am65_cpts_settime(struct am65_cpts *cpts, u64 start_tstamp)
200{
201 u32 val;
202
203 val = upper_32_bits(start_tstamp);
204 am65_cpts_write32(cpts, val, ts_load_val_hi);
205 val = lower_32_bits(start_tstamp);
206 am65_cpts_write32(cpts, val, ts_load_val_lo);
207
208 am65_cpts_write32(cpts, AM65_CPTS_TS_LOAD_EN, ts_load_en);
209}
210
211static void am65_cpts_set_add_val(struct am65_cpts *cpts)
212{
213 /* select coefficient according to the rate */
214 cpts->ts_add_val = (NSEC_PER_SEC / cpts->refclk_freq - 1) & 0x7;
215
216 am65_cpts_write32(cpts, cpts->ts_add_val, ts_add_val);
217}
218
219static void am65_cpts_disable(struct am65_cpts *cpts)
220{
221 am65_cpts_write32(cpts, 0, control);
222 am65_cpts_write32(cpts, 0, int_enable);
223}
224
225static int am65_cpts_event_get_port(struct am65_cpts_event *event)
226{
227 return (event->event1 & AM65_CPTS_EVENT_1_PORT_NUMBER_MASK) >>
228 AM65_CPTS_EVENT_1_PORT_NUMBER_SHIFT;
229}
230
231static int am65_cpts_event_get_type(struct am65_cpts_event *event)
232{
233 return (event->event1 & AM65_CPTS_EVENT_1_EVENT_TYPE_MASK) >>
234 AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT;
235}
236
237static int am65_cpts_cpts_purge_events(struct am65_cpts *cpts)
238{
239 struct list_head *this, *next;
240 struct am65_cpts_event *event;
241 int removed = 0;
242
243 list_for_each_safe(this, next, &cpts->events) {
244 event = list_entry(this, struct am65_cpts_event, list);
245 if (time_after(jiffies, event->tmo)) {
246 list_del_init(&event->list);
247 list_add(&event->list, &cpts->pool);
248 ++removed;
249 }
250 }
251
252 if (removed)
253 dev_dbg(cpts->dev, "event pool cleaned up %d\n", removed);
254 return removed ? 0 : -1;
255}
256
257static bool am65_cpts_fifo_pop_event(struct am65_cpts *cpts,
258 struct am65_cpts_event *event)
259{
260 u32 r = am65_cpts_read32(cpts, intstat_raw);
261
262 if (r & AM65_CPTS_INTSTAT_RAW_TS_PEND) {
263 event->timestamp = am65_cpts_read32(cpts, event_0);
264 event->event1 = am65_cpts_read32(cpts, event_1);
265 event->event2 = am65_cpts_read32(cpts, event_2);
266 event->timestamp |= (u64)am65_cpts_read32(cpts, event_3) << 32;
267 am65_cpts_write32(cpts, AM65_CPTS_EVENT_POP, event_pop);
268 return false;
269 }
270 return true;
271}
272
273static int am65_cpts_fifo_read(struct am65_cpts *cpts)
274{
275 struct ptp_clock_event pevent;
276 struct am65_cpts_event *event;
277 bool schedule = false;
278 int i, type, ret = 0;
279 unsigned long flags;
280
281 spin_lock_irqsave(&cpts->lock, flags);
282 for (i = 0; i < AM65_CPTS_FIFO_DEPTH; i++) {
283 event = list_first_entry_or_null(&cpts->pool,
284 struct am65_cpts_event, list);
285
286 if (!event) {
287 if (am65_cpts_cpts_purge_events(cpts)) {
288 dev_err(cpts->dev, "cpts: event pool empty\n");
289 ret = -1;
290 goto out;
291 }
292 continue;
293 }
294
295 if (am65_cpts_fifo_pop_event(cpts, event))
296 break;
297
298 type = am65_cpts_event_get_type(event);
299 switch (type) {
300 case AM65_CPTS_EV_PUSH:
301 cpts->timestamp = event->timestamp;
302 dev_dbg(cpts->dev, "AM65_CPTS_EV_PUSH t:%llu\n",
303 cpts->timestamp);
304 break;
305 case AM65_CPTS_EV_RX:
306 case AM65_CPTS_EV_TX:
307 event->tmo = jiffies +
308 msecs_to_jiffies(AM65_CPTS_EVENT_RX_TX_TIMEOUT);
309
310 list_del_init(&event->list);
311 list_add_tail(&event->list, &cpts->events);
312
313 dev_dbg(cpts->dev,
314 "AM65_CPTS_EV_TX e1:%08x e2:%08x t:%lld\n",
315 event->event1, event->event2,
316 event->timestamp);
317 schedule = true;
318 break;
319 case AM65_CPTS_EV_HW:
320 pevent.index = am65_cpts_event_get_port(event) - 1;
321 pevent.timestamp = event->timestamp;
322 pevent.type = PTP_CLOCK_EXTTS;
323 dev_dbg(cpts->dev, "AM65_CPTS_EV_HW p:%d t:%llu\n",
324 pevent.index, event->timestamp);
325
326 ptp_clock_event(cpts->ptp_clock, &pevent);
327 break;
328 case AM65_CPTS_EV_HOST:
329 break;
330 case AM65_CPTS_EV_ROLL:
331 case AM65_CPTS_EV_HALF:
332 case AM65_CPTS_EV_TS_COMP:
333 dev_dbg(cpts->dev,
334 "AM65_CPTS_EVT: %d e1:%08x e2:%08x t:%lld\n",
335 type,
336 event->event1, event->event2,
337 event->timestamp);
338 break;
339 default:
340 dev_err(cpts->dev, "cpts: unknown event type\n");
341 ret = -1;
342 goto out;
343 }
344 }
345
346out:
347 spin_unlock_irqrestore(&cpts->lock, flags);
348
349 if (schedule)
350 ptp_schedule_worker(cpts->ptp_clock, 0);
351
352 return ret;
353}
354
355static u64 am65_cpts_gettime(struct am65_cpts *cpts,
356 struct ptp_system_timestamp *sts)
357{
358 unsigned long flags;
359 u64 val = 0;
360
361 /* temporarily disable cpts interrupt to avoid intentional
362 * doubled read. Interrupt can be in-flight - it's Ok.
363 */
364 am65_cpts_write32(cpts, 0, int_enable);
365
366 /* use spin_lock_irqsave() here as it has to run very fast */
367 spin_lock_irqsave(&cpts->lock, flags);
368 ptp_read_system_prets(sts);
369 am65_cpts_write32(cpts, AM65_CPTS_TS_PUSH, ts_push);
370 am65_cpts_read32(cpts, ts_push);
371 ptp_read_system_postts(sts);
372 spin_unlock_irqrestore(&cpts->lock, flags);
373
374 am65_cpts_fifo_read(cpts);
375
376 am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable);
377
378 val = cpts->timestamp;
379
380 return val;
381}
382
383static irqreturn_t am65_cpts_interrupt(int irq, void *dev_id)
384{
385 struct am65_cpts *cpts = dev_id;
386
387 if (am65_cpts_fifo_read(cpts))
388 dev_dbg(cpts->dev, "cpts: unable to obtain a time stamp\n");
389
390 return IRQ_HANDLED;
391}
392
393/* PTP clock operations */
e2bd9c76 394static int am65_cpts_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
f6bd5952
GS		 395{
396 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
e2bd9c76 397 s32 ppb = scaled_ppm_to_ppb(scaled_ppm);
f6bd5952
GS		 398 int neg_adj = 0;
399 u64 adj_period;
400 u32 val;
401
402 if (ppb < 0) {
403 neg_adj = 1;
404 ppb = -ppb;
405 }
406
407 /* base freq = 1GHz = 1 000 000 000
408 * ppb_norm = ppb * base_freq / clock_freq;
409 * ppm_norm = ppb_norm / 1000
410 * adj_period = 1 000 000 / ppm_norm
411 * adj_period = 1 000 000 000 / ppb_norm
412 * adj_period = 1 000 000 000 / (ppb * base_freq / clock_freq)
413 * adj_period = (1 000 000 000 * clock_freq) / (ppb * base_freq)
414 * adj_period = clock_freq / ppb
415 */
416 adj_period = div_u64(cpts->refclk_freq, ppb);
417
418 mutex_lock(&cpts->ptp_clk_lock);
419
420 val = am65_cpts_read32(cpts, control);
421 if (neg_adj)
422 val |= AM65_CPTS_CONTROL_TS_PPM_DIR;
423 else
424 val &= ~AM65_CPTS_CONTROL_TS_PPM_DIR;
425 am65_cpts_write32(cpts, val, control);
426
427 val = upper_32_bits(adj_period) & 0x3FF;
428 am65_cpts_write32(cpts, val, ts_ppm_hi);
429 val = lower_32_bits(adj_period);
430 am65_cpts_write32(cpts, val, ts_ppm_low);
431
432 mutex_unlock(&cpts->ptp_clk_lock);
433
434 return 0;
435}
436
437static int am65_cpts_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
438{
439 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
440 s64 ns;
441
442 mutex_lock(&cpts->ptp_clk_lock);
443 ns = am65_cpts_gettime(cpts, NULL);
444 ns += delta;
445 am65_cpts_settime(cpts, ns);
446 mutex_unlock(&cpts->ptp_clk_lock);
447
448 return 0;
449}
450
451static int am65_cpts_ptp_gettimex(struct ptp_clock_info *ptp,
452 struct timespec64 *ts,
453 struct ptp_system_timestamp *sts)
454{
455 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
456 u64 ns;
457
458 mutex_lock(&cpts->ptp_clk_lock);
459 ns = am65_cpts_gettime(cpts, sts);
460 mutex_unlock(&cpts->ptp_clk_lock);
461 *ts = ns_to_timespec64(ns);
462
463 return 0;
464}
465
ec008fa2
IK		 466u64 am65_cpts_ns_gettime(struct am65_cpts *cpts)
467{
468 u64 ns;
469
470 /* reuse ptp_clk_lock as it serialize ts push */
471 mutex_lock(&cpts->ptp_clk_lock);
472 ns = am65_cpts_gettime(cpts, NULL);
473 mutex_unlock(&cpts->ptp_clk_lock);
474
475 return ns;
476}
477EXPORT_SYMBOL_GPL(am65_cpts_ns_gettime);
478
f6bd5952
GS		 479static int am65_cpts_ptp_settime(struct ptp_clock_info *ptp,
480 const struct timespec64 *ts)
481{
482 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
483 u64 ns;
484
485 ns = timespec64_to_ns(ts);
486 mutex_lock(&cpts->ptp_clk_lock);
487 am65_cpts_settime(cpts, ns);
488 mutex_unlock(&cpts->ptp_clk_lock);
489
490 return 0;
491}
492
493static void am65_cpts_extts_enable_hw(struct am65_cpts *cpts, u32 index, int on)
494{
495 u32 v;
496
497 v = am65_cpts_read32(cpts, control);
498 if (on) {
499 v |= BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index);
500 cpts->hw_ts_enable |= BIT(index);
501 } else {
502 v &= ~BIT(AM65_CPTS_CONTROL_HW1_TS_PUSH_OFFSET + index);
503 cpts->hw_ts_enable &= ~BIT(index);
504 }
505 am65_cpts_write32(cpts, v, control);
506}
507
508static int am65_cpts_extts_enable(struct am65_cpts *cpts, u32 index, int on)
509{
510 if (!!(cpts->hw_ts_enable & BIT(index)) == !!on)
511 return 0;
512
513 mutex_lock(&cpts->ptp_clk_lock);
514 am65_cpts_extts_enable_hw(cpts, index, on);
515 mutex_unlock(&cpts->ptp_clk_lock);
516
517 dev_dbg(cpts->dev, "%s: ExtTS:%u %s\n",
518 __func__, index, on ? "enabled" : "disabled");
519
520 return 0;
521}
522
ec008fa2
IK		 523int am65_cpts_estf_enable(struct am65_cpts *cpts, int idx,
524 struct am65_cpts_estf_cfg *cfg)
525{
526 u64 cycles;
527 u32 val;
528
529 cycles = cfg->ns_period * cpts->refclk_freq;
530 cycles = DIV_ROUND_UP(cycles, NSEC_PER_SEC);
531 if (cycles > U32_MAX)
532 return -EINVAL;
533
534 /* according to TRM should be zeroed */
535 am65_cpts_write32(cpts, 0, estf[idx].length);
536
537 val = upper_32_bits(cfg->ns_start);
538 am65_cpts_write32(cpts, val, estf[idx].comp_hi);
539 val = lower_32_bits(cfg->ns_start);
540 am65_cpts_write32(cpts, val, estf[idx].comp_lo);
541 val = lower_32_bits(cycles);
542 am65_cpts_write32(cpts, val, estf[idx].length);
543
544 dev_dbg(cpts->dev, "%s: ESTF:%u enabled\n", __func__, idx);
545
546 return 0;
547}
548EXPORT_SYMBOL_GPL(am65_cpts_estf_enable);
549
550void am65_cpts_estf_disable(struct am65_cpts *cpts, int idx)
551{
552 am65_cpts_write32(cpts, 0, estf[idx].length);
553
554 dev_dbg(cpts->dev, "%s: ESTF:%u disabled\n", __func__, idx);
555}
556EXPORT_SYMBOL_GPL(am65_cpts_estf_disable);
557
f6bd5952
GS		 558static void am65_cpts_perout_enable_hw(struct am65_cpts *cpts,
559 struct ptp_perout_request *req, int on)
560{
561 u64 ns_period, ns_start, cycles;
562 struct timespec64 ts;
563 u32 val;
564
565 if (on) {
566 ts.tv_sec = req->period.sec;
567 ts.tv_nsec = req->period.nsec;
568 ns_period = timespec64_to_ns(&ts);
569
570 cycles = (ns_period * cpts->refclk_freq) / NSEC_PER_SEC;
571
572 ts.tv_sec = req->start.sec;
573 ts.tv_nsec = req->start.nsec;
574 ns_start = timespec64_to_ns(&ts);
575
576 val = upper_32_bits(ns_start);
577 am65_cpts_write32(cpts, val, genf[req->index].comp_hi);
578 val = lower_32_bits(ns_start);
579 am65_cpts_write32(cpts, val, genf[req->index].comp_lo);
580 val = lower_32_bits(cycles);
581 am65_cpts_write32(cpts, val, genf[req->index].length);
582
583 cpts->genf_enable |= BIT(req->index);
584 } else {
585 am65_cpts_write32(cpts, 0, genf[req->index].length);
586
587 cpts->genf_enable &= ~BIT(req->index);
588 }
589}
590
591static int am65_cpts_perout_enable(struct am65_cpts *cpts,
592 struct ptp_perout_request *req, int on)
593{
594 if (!!(cpts->genf_enable & BIT(req->index)) == !!on)
595 return 0;
596
597 mutex_lock(&cpts->ptp_clk_lock);
598 am65_cpts_perout_enable_hw(cpts, req, on);
599 mutex_unlock(&cpts->ptp_clk_lock);
600
601 dev_dbg(cpts->dev, "%s: GenF:%u %s\n",
602 __func__, req->index, on ? "enabled" : "disabled");
603
604 return 0;
605}
606
607static int am65_cpts_ptp_enable(struct ptp_clock_info *ptp,
608 struct ptp_clock_request *rq, int on)
609{
610 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
611
612 switch (rq->type) {
613 case PTP_CLK_REQ_EXTTS:
614 return am65_cpts_extts_enable(cpts, rq->extts.index, on);
615 case PTP_CLK_REQ_PEROUT:
616 return am65_cpts_perout_enable(cpts, &rq->perout, on);
617 default:
618 break;
619 }
620
621 return -EOPNOTSUPP;
622}
623
624static long am65_cpts_ts_work(struct ptp_clock_info *ptp);
625
626static struct ptp_clock_info am65_ptp_info = {
627 .owner = THIS_MODULE,
628 .name = "CTPS timer",
e2bd9c76 629 .adjfine = am65_cpts_ptp_adjfine,
f6bd5952
GS		 630 .adjtime = am65_cpts_ptp_adjtime,
631 .gettimex64 = am65_cpts_ptp_gettimex,
632 .settime64 = am65_cpts_ptp_settime,
633 .enable = am65_cpts_ptp_enable,
634 .do_aux_work = am65_cpts_ts_work,
635};
636
637static bool am65_cpts_match_tx_ts(struct am65_cpts *cpts,
638 struct am65_cpts_event *event)
639{
640 struct sk_buff_head txq_list;
641 struct sk_buff *skb, *tmp;
642 unsigned long flags;
643 bool found = false;
644 u32 mtype_seqid;
645
646 mtype_seqid = event->event1 &
647 (AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK |
648 AM65_CPTS_EVENT_1_EVENT_TYPE_MASK |
649 AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK);
650
651 __skb_queue_head_init(&txq_list);
652
653 spin_lock_irqsave(&cpts->txq.lock, flags);
654 skb_queue_splice_init(&cpts->txq, &txq_list);
655 spin_unlock_irqrestore(&cpts->txq.lock, flags);
656
657 /* no need to grab txq.lock as access is always done under cpts->lock */
658 skb_queue_walk_safe(&txq_list, skb, tmp) {
659 struct skb_shared_hwtstamps ssh;
660 struct am65_cpts_skb_cb_data *skb_cb =
661 (struct am65_cpts_skb_cb_data *)skb->cb;
662
663 if (mtype_seqid == skb_cb->skb_mtype_seqid) {
664 u64 ns = event->timestamp;
665
666 memset(&ssh, 0, sizeof(ssh));
667 ssh.hwtstamp = ns_to_ktime(ns);
668 skb_tstamp_tx(skb, &ssh);
669 found = true;
670 __skb_unlink(skb, &txq_list);
671 dev_consume_skb_any(skb);
672 dev_dbg(cpts->dev,
673 "match tx timestamp mtype_seqid %08x\n",
674 mtype_seqid);
675 break;
676 }
677
678 if (time_after(jiffies, skb_cb->tmo)) {
679 /* timeout any expired skbs over 100 ms */
680 dev_dbg(cpts->dev,
681 "expiring tx timestamp mtype_seqid %08x\n",
682 mtype_seqid);
683 __skb_unlink(skb, &txq_list);
684 dev_consume_skb_any(skb);
685 }
686 }
687
688 spin_lock_irqsave(&cpts->txq.lock, flags);
689 skb_queue_splice(&txq_list, &cpts->txq);
690 spin_unlock_irqrestore(&cpts->txq.lock, flags);
691
692 return found;
693}
694
695static void am65_cpts_find_ts(struct am65_cpts *cpts)
696{
697 struct am65_cpts_event *event;
698 struct list_head *this, *next;
699 LIST_HEAD(events_free);
700 unsigned long flags;
701 LIST_HEAD(events);
702
703 spin_lock_irqsave(&cpts->lock, flags);
704 list_splice_init(&cpts->events, &events);
705 spin_unlock_irqrestore(&cpts->lock, flags);
706
707 list_for_each_safe(this, next, &events) {
708 event = list_entry(this, struct am65_cpts_event, list);
709 if (am65_cpts_match_tx_ts(cpts, event) ||
710 time_after(jiffies, event->tmo)) {
711 list_del_init(&event->list);
712 list_add(&event->list, &events_free);
713 }
714 }
715
716 spin_lock_irqsave(&cpts->lock, flags);
717 list_splice_tail(&events, &cpts->events);
718 list_splice_tail(&events_free, &cpts->pool);
719 spin_unlock_irqrestore(&cpts->lock, flags);
720}
721
722static long am65_cpts_ts_work(struct ptp_clock_info *ptp)
723{
724 struct am65_cpts *cpts = container_of(ptp, struct am65_cpts, ptp_info);
725 unsigned long flags;
726 long delay = -1;
727
728 am65_cpts_find_ts(cpts);
729
730 spin_lock_irqsave(&cpts->txq.lock, flags);
731 if (!skb_queue_empty(&cpts->txq))
732 delay = AM65_CPTS_SKB_TX_WORK_TIMEOUT;
733 spin_unlock_irqrestore(&cpts->txq.lock, flags);
734
735 return delay;
736}
737
738/**
739 * am65_cpts_rx_enable - enable rx timestamping
740 * @cpts: cpts handle
e49e4647 741 * @en: enable
f6bd5952
GS		 742 *
743 * This functions enables rx packets timestamping. The CPTS can timestamp all
744 * rx packets.
745 */
746void am65_cpts_rx_enable(struct am65_cpts *cpts, bool en)
747{
748 u32 val;
749
750 mutex_lock(&cpts->ptp_clk_lock);
751 val = am65_cpts_read32(cpts, control);
752 if (en)
753 val |= AM65_CPTS_CONTROL_TSTAMP_EN;
754 else
755 val &= ~AM65_CPTS_CONTROL_TSTAMP_EN;
756 am65_cpts_write32(cpts, val, control);
757 mutex_unlock(&cpts->ptp_clk_lock);
758}
759EXPORT_SYMBOL_GPL(am65_cpts_rx_enable);
760
761static int am65_skb_get_mtype_seqid(struct sk_buff *skb, u32 *mtype_seqid)
762{
763 unsigned int ptp_class = ptp_classify_raw(skb);
4bccb5d0
KK		 764 struct ptp_header *hdr;
765 u8 msgtype;
766 u16 seqid;
f6bd5952
GS		 767
768 if (ptp_class == PTP_CLASS_NONE)
769 return 0;
770
4bccb5d0
KK		 771 hdr = ptp_parse_header(skb, ptp_class);
772 if (!hdr)
f6bd5952
GS		 773 return 0;
774
4bccb5d0
KK		 775 msgtype = ptp_get_msgtype(hdr, ptp_class);
776 seqid = ntohs(hdr->sequence_id);
f6bd5952 777
4bccb5d0 778 *mtype_seqid = (msgtype << AM65_CPTS_EVENT_1_MESSAGE_TYPE_SHIFT) &
f6bd5952 779 AM65_CPTS_EVENT_1_MESSAGE_TYPE_MASK;
4bccb5d0 780 *mtype_seqid |= (seqid & AM65_CPTS_EVENT_1_SEQUENCE_ID_MASK);
f6bd5952
GS		 781
782 return 1;
783}
784
785/**
786 * am65_cpts_tx_timestamp - save tx packet for timestamping
787 * @cpts: cpts handle
788 * @skb: packet
789 *
790 * This functions saves tx packet for timestamping if packet can be timestamped.
791 * The future processing is done in from PTP auxiliary worker.
792 */
793void am65_cpts_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb)
794{
795 struct am65_cpts_skb_cb_data *skb_cb = (void *)skb->cb;
796
797 if (!(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
798 return;
799
800 /* add frame to queue for processing later.
801 * The periodic FIFO check will handle this.
802 */
803 skb_get(skb);
804 /* get the timestamp for timeouts */
805 skb_cb->tmo = jiffies + msecs_to_jiffies(100);
806 skb_queue_tail(&cpts->txq, skb);
807 ptp_schedule_worker(cpts->ptp_clock, 0);
808}
809EXPORT_SYMBOL_GPL(am65_cpts_tx_timestamp);
810
811/**
812 * am65_cpts_prep_tx_timestamp - check and prepare tx packet for timestamping
813 * @cpts: cpts handle
814 * @skb: packet
815 *
816 * This functions should be called from .xmit().
817 * It checks if packet can be timestamped, fills internal cpts data
818 * in skb-cb and marks packet as SKBTX_IN_PROGRESS.
819 */
820void am65_cpts_prep_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb)
821{
822 struct am65_cpts_skb_cb_data *skb_cb = (void *)skb->cb;
823 int ret;
824
825 if (!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP))
826 return;
827
828 ret = am65_skb_get_mtype_seqid(skb, &skb_cb->skb_mtype_seqid);
829 if (!ret)
830 return;
831 skb_cb->skb_mtype_seqid |= (AM65_CPTS_EV_TX <<
832 AM65_CPTS_EVENT_1_EVENT_TYPE_SHIFT);
833
834 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
835}
836EXPORT_SYMBOL_GPL(am65_cpts_prep_tx_timestamp);
837
838int am65_cpts_phc_index(struct am65_cpts *cpts)
839{
840 return cpts->phc_index;
841}
842EXPORT_SYMBOL_GPL(am65_cpts_phc_index);
843
844static void cpts_free_clk_mux(void *data)
845{
846 struct am65_cpts *cpts = data;
847
848 of_clk_del_provider(cpts->clk_mux_np);
849 clk_hw_unregister_mux(cpts->clk_mux_hw);
850 of_node_put(cpts->clk_mux_np);
851}
852
853static int cpts_of_mux_clk_setup(struct am65_cpts *cpts,
854 struct device_node *node)
855{
856 unsigned int num_parents;
857 const char **parent_names;
858 char *clk_mux_name;
859 void __iomem *reg;
860 int ret = -EINVAL;
861
862 cpts->clk_mux_np = of_get_child_by_name(node, "refclk-mux");
863 if (!cpts->clk_mux_np)
864 return 0;
865
866 num_parents = of_clk_get_parent_count(cpts->clk_mux_np);
867 if (num_parents < 1) {
868 dev_err(cpts->dev, "mux-clock %pOF must have parents\n",
869 cpts->clk_mux_np);
870 goto mux_fail;
871 }
872
873 parent_names = devm_kcalloc(cpts->dev, sizeof(char *), num_parents,
874 GFP_KERNEL);
875 if (!parent_names) {
876 ret = -ENOMEM;
877 goto mux_fail;
878 }
879
880 of_clk_parent_fill(cpts->clk_mux_np, parent_names, num_parents);
881
882 clk_mux_name = devm_kasprintf(cpts->dev, GFP_KERNEL, "%s.%pOFn",
883 dev_name(cpts->dev), cpts->clk_mux_np);
884 if (!clk_mux_name) {
885 ret = -ENOMEM;
886 goto mux_fail;
887 }
888
889 reg = &cpts->reg->rftclk_sel;
890 /* dev must be NULL to avoid recursive incrementing
891 * of module refcnt
892 */
893 cpts->clk_mux_hw = clk_hw_register_mux(NULL, clk_mux_name,
894 parent_names, num_parents,
895 0, reg, 0, 5, 0, NULL);
896 if (IS_ERR(cpts->clk_mux_hw)) {
897 ret = PTR_ERR(cpts->clk_mux_hw);
898 goto mux_fail;
899 }
900
901 ret = of_clk_add_hw_provider(cpts->clk_mux_np, of_clk_hw_simple_get,
902 cpts->clk_mux_hw);
903 if (ret)
904 goto clk_hw_register;
905
906 ret = devm_add_action_or_reset(cpts->dev, cpts_free_clk_mux, cpts);
907 if (ret)
908 dev_err(cpts->dev, "failed to add clkmux reset action %d", ret);
909
910 return ret;
911
912clk_hw_register:
913 clk_hw_unregister_mux(cpts->clk_mux_hw);
914mux_fail:
915 of_node_put(cpts->clk_mux_np);
916 return ret;
917}
918
919static int am65_cpts_of_parse(struct am65_cpts *cpts, struct device_node *node)
920{
921 u32 prop[2];
922
923 if (!of_property_read_u32(node, "ti,cpts-ext-ts-inputs", &prop[0]))
924 cpts->ext_ts_inputs = prop[0];
925
926 if (!of_property_read_u32(node, "ti,cpts-periodic-outputs", &prop[0]))
927 cpts->genf_num = prop[0];
928
929 return cpts_of_mux_clk_setup(cpts, node);
930}
931
932static void am65_cpts_release(void *data)
933{
934 struct am65_cpts *cpts = data;
935
936 ptp_clock_unregister(cpts->ptp_clock);
937 am65_cpts_disable(cpts);
938 clk_disable_unprepare(cpts->refclk);
939}
940
941struct am65_cpts *am65_cpts_create(struct device *dev, void __iomem *regs,
942 struct device_node *node)
943{
944 struct am65_cpts *cpts;
945 int ret, i;
946
947 cpts = devm_kzalloc(dev, sizeof(*cpts), GFP_KERNEL);
948 if (!cpts)
949 return ERR_PTR(-ENOMEM);
950
951 cpts->dev = dev;
952 cpts->reg = (struct am65_cpts_regs __iomem *)regs;
953
954 cpts->irq = of_irq_get_byname(node, "cpts");
955 if (cpts->irq <= 0) {
956 ret = cpts->irq ?: -ENXIO;
e2baa126 957 dev_err_probe(dev, ret, "Failed to get IRQ number\n");
f6bd5952
GS		 958 return ERR_PTR(ret);
959 }
960
961 ret = am65_cpts_of_parse(cpts, node);
962 if (ret)
963 return ERR_PTR(ret);
964
965 mutex_init(&cpts->ptp_clk_lock);
966 INIT_LIST_HEAD(&cpts->events);
967 INIT_LIST_HEAD(&cpts->pool);
968 spin_lock_init(&cpts->lock);
969 skb_queue_head_init(&cpts->txq);
970
971 for (i = 0; i < AM65_CPTS_MAX_EVENTS; i++)
972 list_add(&cpts->pool_data[i].list, &cpts->pool);
973
974 cpts->refclk = devm_get_clk_from_child(dev, node, "cpts");
975 if (IS_ERR(cpts->refclk)) {
976 ret = PTR_ERR(cpts->refclk);
e2baa126 977 dev_err_probe(dev, ret, "Failed to get refclk\n");
f6bd5952
GS		 978 return ERR_PTR(ret);
979 }
980
981 ret = clk_prepare_enable(cpts->refclk);
982 if (ret) {
983 dev_err(dev, "Failed to enable refclk %d\n", ret);
984 return ERR_PTR(ret);
985 }
986
987 cpts->refclk_freq = clk_get_rate(cpts->refclk);
988
989 am65_ptp_info.max_adj = cpts->refclk_freq / AM65_CPTS_MIN_PPM;
990 cpts->ptp_info = am65_ptp_info;
991
992 if (cpts->ext_ts_inputs)
993 cpts->ptp_info.n_ext_ts = cpts->ext_ts_inputs;
994 if (cpts->genf_num)
995 cpts->ptp_info.n_per_out = cpts->genf_num;
996
997 am65_cpts_set_add_val(cpts);
998
4d4dce31
GS		 999 am65_cpts_write32(cpts, AM65_CPTS_CONTROL_EN |
1000 AM65_CPTS_CONTROL_64MODE |
1001 AM65_CPTS_CONTROL_TX_GENF_CLR_EN,
f6bd5952
GS		 1002 control);
1003 am65_cpts_write32(cpts, AM65_CPTS_INT_ENABLE_TS_PEND_EN, int_enable);
1004
1005 /* set time to the current system time */
1006 am65_cpts_settime(cpts, ktime_to_ns(ktime_get_real()));
1007
1008 cpts->ptp_clock = ptp_clock_register(&cpts->ptp_info, cpts->dev);
1009 if (IS_ERR_OR_NULL(cpts->ptp_clock)) {
1010 dev_err(dev, "Failed to register ptp clk %ld\n",
1011 PTR_ERR(cpts->ptp_clock));
81e329e9 1012 ret = cpts->ptp_clock ? PTR_ERR(cpts->ptp_clock) : -ENODEV;
f6bd5952
GS		 1013 goto refclk_disable;
1014 }
1015 cpts->phc_index = ptp_clock_index(cpts->ptp_clock);
1016
1017 ret = devm_add_action_or_reset(dev, am65_cpts_release, cpts);
1018 if (ret) {
1019 dev_err(dev, "failed to add ptpclk reset action %d", ret);
1020 return ERR_PTR(ret);
1021 }
1022
1023 ret = devm_request_threaded_irq(dev, cpts->irq, NULL,
1024 am65_cpts_interrupt,
1025 IRQF_ONESHOT, dev_name(dev), cpts);
1026 if (ret < 0) {
1027 dev_err(cpts->dev, "error attaching irq %d\n", ret);
1028 return ERR_PTR(ret);
1029 }
1030
1031 dev_info(dev, "CPTS ver 0x%08x, freq:%u, add_val:%u\n",
1032 am65_cpts_read32(cpts, idver),
1033 cpts->refclk_freq, cpts->ts_add_val);
1034
1035 return cpts;
1036
1037refclk_disable:
1038 clk_disable_unprepare(cpts->refclk);
1039 return ERR_PTR(ret);
1040}
1041EXPORT_SYMBOL_GPL(am65_cpts_create);
1042
cef122d4
RQ		 1043void am65_cpts_suspend(struct am65_cpts *cpts)
1044{
1045 /* save state and disable CPTS */
1046 cpts->sr_control = am65_cpts_read32(cpts, control);
1047 cpts->sr_int_enable = am65_cpts_read32(cpts, int_enable);
1048 cpts->sr_rftclk_sel = am65_cpts_read32(cpts, rftclk_sel);
1049 cpts->sr_ts_ppm_hi = am65_cpts_read32(cpts, ts_ppm_hi);
1050 cpts->sr_ts_ppm_low = am65_cpts_read32(cpts, ts_ppm_low);
1051 cpts->sr_cpts_ns = am65_cpts_gettime(cpts, NULL);
1052 cpts->sr_ktime_ns = ktime_to_ns(ktime_get_real());
1053 am65_cpts_disable(cpts);
1054 clk_disable(cpts->refclk);
1055
1056 /* Save GENF state */
1057 memcpy_fromio(&cpts->sr_genf, &cpts->reg->genf, sizeof(cpts->sr_genf));
1058
1059 /* Save ESTF state */
1060 memcpy_fromio(&cpts->sr_estf, &cpts->reg->estf, sizeof(cpts->sr_estf));
1061}
1062EXPORT_SYMBOL_GPL(am65_cpts_suspend);
1063
1064void am65_cpts_resume(struct am65_cpts *cpts)
1065{
1066 int i;
1067 s64 ktime_ns;
1068
1069 /* restore state and enable CPTS */
1070 clk_enable(cpts->refclk);
1071 am65_cpts_write32(cpts, cpts->sr_rftclk_sel, rftclk_sel);
1072 am65_cpts_set_add_val(cpts);
1073 am65_cpts_write32(cpts, cpts->sr_control, control);
1074 am65_cpts_write32(cpts, cpts->sr_int_enable, int_enable);
1075
1076 /* Restore time to saved CPTS time + time in suspend/resume */
1077 ktime_ns = ktime_to_ns(ktime_get_real());
1078 ktime_ns -= cpts->sr_ktime_ns;
1079 am65_cpts_settime(cpts, cpts->sr_cpts_ns + ktime_ns);
1080
1081 /* Restore compensation (PPM) */
1082 am65_cpts_write32(cpts, cpts->sr_ts_ppm_hi, ts_ppm_hi);
1083 am65_cpts_write32(cpts, cpts->sr_ts_ppm_low, ts_ppm_low);
1084
1085 /* Restore GENF state */
1086 for (i = 0; i < AM65_CPTS_GENF_MAX_NUM; i++) {
1087 am65_cpts_write32(cpts, 0, genf[i].length); /* TRM sequence */
1088 am65_cpts_write32(cpts, cpts->sr_genf[i].comp_hi, genf[i].comp_hi);
1089 am65_cpts_write32(cpts, cpts->sr_genf[i].comp_lo, genf[i].comp_lo);
1090 am65_cpts_write32(cpts, cpts->sr_genf[i].length, genf[i].length);
1091 am65_cpts_write32(cpts, cpts->sr_genf[i].control, genf[i].control);
1092 am65_cpts_write32(cpts, cpts->sr_genf[i].ppm_hi, genf[i].ppm_hi);
1093 am65_cpts_write32(cpts, cpts->sr_genf[i].ppm_low, genf[i].ppm_low);
1094 }
1095
1096 /* Restore ESTTF state */
1097 for (i = 0; i < AM65_CPTS_ESTF_MAX_NUM; i++) {
1098 am65_cpts_write32(cpts, 0, estf[i].length); /* TRM sequence */
1099 am65_cpts_write32(cpts, cpts->sr_estf[i].comp_hi, estf[i].comp_hi);
1100 am65_cpts_write32(cpts, cpts->sr_estf[i].comp_lo, estf[i].comp_lo);
1101 am65_cpts_write32(cpts, cpts->sr_estf[i].length, estf[i].length);
1102 am65_cpts_write32(cpts, cpts->sr_estf[i].control, estf[i].control);
1103 am65_cpts_write32(cpts, cpts->sr_estf[i].ppm_hi, estf[i].ppm_hi);
1104 am65_cpts_write32(cpts, cpts->sr_estf[i].ppm_low, estf[i].ppm_low);
1105 }
1106}
1107EXPORT_SYMBOL_GPL(am65_cpts_resume);
1108
f6bd5952
GS		 1109static int am65_cpts_probe(struct platform_device *pdev)
1110{
1111 struct device_node *node = pdev->dev.of_node;
1112 struct device *dev = &pdev->dev;
1113 struct am65_cpts *cpts;
f6bd5952
GS		 1114 void __iomem *base;
1115
e77e2cf4 1116 base = devm_platform_ioremap_resource_byname(pdev, "cpts");
f6bd5952
GS		 1117 if (IS_ERR(base))
1118 return PTR_ERR(base);
1119
1120 cpts = am65_cpts_create(dev, base, node);
bbae62e3 1121 return PTR_ERR_OR_ZERO(cpts);
f6bd5952
GS		 1122}
1123
1124static const struct of_device_id am65_cpts_of_match[] = {
1125 { .compatible = "ti,am65-cpts", },
1126 { .compatible = "ti,j721e-cpts", },
1127 {},
1128};
1129MODULE_DEVICE_TABLE(of, am65_cpts_of_match);
1130
1131static struct platform_driver am65_cpts_driver = {
1132 .probe = am65_cpts_probe,
1133 .driver = {
1134 .name = "am65-cpts",
1135 .of_match_table = am65_cpts_of_match,
1136 },
1137};
1138module_platform_driver(am65_cpts_driver);
1139
1140MODULE_LICENSE("GPL v2");
1141MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>");
1142MODULE_DESCRIPTION("TI K3 AM65 CPTS driver");
Linux 6.x block layer and io_uring tree(s)