Add cross-stripe intel sample verify job

[fio.git] / crc / crc32c-intel.c

diff --git a/crc/crc32c-intel.c b/crc/crc32c-intel.c
index 77d6df411973510298342d79e190db4b3a447ffa..6e810a28f93608dfafcaac4bb6dec03bea526554 100644 (file)
--- a/crc/crc32c-intel.c
+++ b/crc/crc32c-intel.c
@@ -1,10 +1,3 @@
-#include <inttypes.h>
-#include <string.h>
-#include <unistd.h>
-#include <stdlib.h>
-#include <signal.h>
-#include <sys/types.h>
-#include <sys/wait.h>
 #include "crc32c.h"
 
 /*
@@ -18,7 +11,9 @@
  * Volume 2A: Instruction Set Reference, A-M
  */
 
-#ifdef ARCH_HAVE_SSE
+bool crc32c_intel_available = false;
+
+#ifdef ARCH_HAVE_SSE4_2
 
 #if BITS_PER_LONG == 64
 #define REX_PRE "0x48, "
@@ -28,8 +23,10 @@
 #define SCALE_F 4
 #endif
 
-uint32_t crc32c_intel_le_hw_byte(uint32_t crc, unsigned char const *data,
-                                unsigned long length)
+static bool crc32c_probed;
+
+static uint32_t crc32c_intel_le_hw_byte(uint32_t crc, unsigned char const *data,
+                                       unsigned long length)
 {
        while (length--) {
                __asm__ __volatile__(
@@ -74,30 +71,17 @@ uint32_t crc32c_intel(unsigned char const *data, unsigned long length)
        return crc;
 }
 
-static void do_cpuid(unsigned int *eax, unsigned int *ebx, unsigned int *ecx,
-                    unsigned int *edx)
+void crc32c_intel_probe(void)
 {
-       int id = *eax;
+       if (!crc32c_probed) {
+               unsigned int eax, ebx, ecx = 0, edx;
 
-       asm("movl %4, %%eax;"
-           "cpuid;"
-           "movl %%eax, %0;"
-           "movl %%ebx, %1;"
-           "movl %%ecx, %2;"
-           "movl %%edx, %3;"
-               : "=r" (*eax), "=r" (*ebx), "=r" (*ecx), "=r" (*edx)
-               : "r" (id)
-               : "eax", "ebx", "ecx", "edx");
-}
+               eax = 1;
 
-int crc32c_intel_works(void)
-{
-       unsigned int eax, ebx, ecx, edx;
-
-       eax = 1;
-
-       do_cpuid(&eax, &ebx, &ecx, &edx);
-       return (ecx & (1 << 20)) != 0;
+               do_cpuid(&eax, &ebx, &ecx, &edx);
+               crc32c_intel_available = (ecx & (1 << 20)) != 0;
+               crc32c_probed = true;
+       }
 }
 
-#endif /* ARCH_HAVE_SSE */
+#endif /* ARCH_HAVE_SSE4_2 */