rand: add 64-bit tausworthe variant with a 2^258 cycle

[fio.git] / crc / crc32c-intel.c

diff --git a/crc/crc32c-intel.c b/crc/crc32c-intel.c
index fc106fa5a9755348e97b5e7dd631267b911061f0..0b0f193c0564a75de8d5d00e80695af40e49dd6a 100644 (file)
--- a/crc/crc32c-intel.c
+++ b/crc/crc32c-intel.c
@@ -18,7 +18,9 @@
  * Volume 2A: Instruction Set Reference, A-M
  */
 
-#ifdef ARCH_HAVE_SSE
+int crc32c_intel_available = 0;
+
+#ifdef ARCH_HAVE_SSE4_2
 
 #if BITS_PER_LONG == 64
 #define REX_PRE "0x48, "
@@ -28,8 +30,10 @@
 #define SCALE_F 4
 #endif
 
-uint32_t crc32c_intel_le_hw_byte(uint32_t crc, unsigned char const *data,
-                                unsigned long length)
+static int crc32c_probed;
+
+static uint32_t crc32c_intel_le_hw_byte(uint32_t crc, unsigned char const *data,
+                                       unsigned long length)
 {
        while (length--) {
                __asm__ __volatile__(
@@ -74,36 +78,16 @@ uint32_t crc32c_intel(unsigned char const *data, unsigned long length)
        return crc;
 }
 
-static void sig_ill(int sig)
-{
-}
-
-static void crc32c_test(void)
+void crc32c_intel_probe(void)
 {
-       unsigned char buf[4] = { 1, 2, 3, 4 };
-       struct sigaction act;
+       if (!crc32c_probed) {
+               unsigned int eax, ebx, ecx = 0, edx;
 
-       /*
-        * Check if hw accelerated crc32c is available
-        */
-       memset(&act, 0, sizeof(act));
-       act.sa_handler = sig_ill;
-       act.sa_flags = SA_RESETHAND;
-       sigaction(SIGILL, &act, NULL);
-
-       (void) crc32c_intel(buf, sizeof(buf));
-}
-
-int crc32c_intel_works(void)
-{
-       if (!fork()) {
-               crc32c_test();
-               exit(0);
-       } else {
-               int status;
+               eax = 1;
 
-               wait(&status);
-               return !WIFSIGNALED(status);
+               do_cpuid(&eax, &ebx, &ecx, &edx);
+               crc32c_intel_available = (ecx & (1 << 20)) != 0;
+               crc32c_probed = 1;
        }
 }