bloom: if we're not setting bits, break after first failed mask check

[fio.git] / crc / crc32c-intel.c

diff --git a/crc/crc32c-intel.c b/crc/crc32c-intel.c
index c0abe73ad7a85ac5bb794f3e50b6137b796391df..0b0f193c0564a75de8d5d00e80695af40e49dd6a 100644 (file)
--- a/crc/crc32c-intel.c
+++ b/crc/crc32c-intel.c
@@ -1,4 +1,11 @@
 #include <inttypes.h>
+#include <string.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <signal.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include "crc32c.h"
 
 /*
  * Based on a posting to lkml by Austin Zhang <austin.zhang@intel.com>
@@ -11,6 +18,10 @@
  * Volume 2A: Instruction Set Reference, A-M
  */
 
+int crc32c_intel_available = 0;
+
+#ifdef ARCH_HAVE_SSE4_2
+
 #if BITS_PER_LONG == 64
 #define REX_PRE "0x48, "
 #define SCALE_F 8
@@ -19,8 +30,10 @@
 #define SCALE_F 4
 #endif
 
-uint32_t crc32c_intel_le_hw_byte(uint32_t crc, unsigned char const *data,
-                                unsigned long length)
+static int crc32c_probed;
+
+static uint32_t crc32c_intel_le_hw_byte(uint32_t crc, unsigned char const *data,
+                                       unsigned long length)
 {
        while (length--) {
                __asm__ __volatile__(
@@ -64,3 +77,18 @@ uint32_t crc32c_intel(unsigned char const *data, unsigned long length)
 
        return crc;
 }
+
+void crc32c_intel_probe(void)
+{
+       if (!crc32c_probed) {
+               unsigned int eax, ebx, ecx = 0, edx;
+
+               eax = 1;
+
+               do_cpuid(&eax, &ebx, &ecx, &edx);
+               crc32c_intel_available = (ecx & (1 << 20)) != 0;
+               crc32c_probed = 1;
+       }
+}
+
+#endif /* ARCH_HAVE_SSE */