[fio.git] / arch / arch-ppc.h

#ifndef ARCH_PPC_H
#define ARCH_PPC_H

#include <unistd.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/wait.h>

#define FIO_ARCH	(arch_ppc)

#ifndef __NR_ioprio_set
#define __NR_ioprio_set		273
#define __NR_ioprio_get		274
#endif

#ifndef __NR_fadvise64
#define __NR_fadvise64		233
#endif

#ifndef __NR_sys_splice
#define __NR_sys_splice		283
#define __NR_sys_tee		284
#define __NR_sys_vmsplice	285
#endif

#define nop	do { } while (0)

#ifdef __powerpc64__
#define read_barrier()	__asm__ __volatile__ ("lwsync" : : : "memory")
#else
#define read_barrier()	__asm__ __volatile__ ("sync" : : : "memory")
#endif

#define write_barrier()	__asm__ __volatile__ ("sync" : : : "memory")

#ifdef __powerpc64__
#define PPC_CNTLZL "cntlzd"
#else
#define PPC_CNTLZL "cntlzw"
#endif

static inline int __ilog2(unsigned long bitmask)
{
	int lz;

	asm (PPC_CNTLZL " %0,%1" : "=r" (lz) : "r" (bitmask));
	return BITS_PER_LONG - 1 - lz;
}

static inline int arch_ffz(unsigned long bitmask)
{
	if ((bitmask = ~bitmask) == 0)
		return BITS_PER_LONG;
	return  __ilog2(bitmask & -bitmask);
}

static inline unsigned int mfspr(unsigned int reg)
{
	unsigned int val;

	asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg));
	return val;
}

#define SPRN_TBRL  0x10C /* Time Base Register Lower */
#define SPRN_TBRU  0x10D /* Time Base Register Upper */
#define SPRN_ATBL  0x20E /* Alternate Time Base Lower */
#define SPRN_ATBU  0x20F /* Alternate Time Base Upper */

#ifdef __powerpc64__
static inline unsigned long long get_cpu_clock(void)
{
	unsigned long long rval;

	asm volatile(
		"90:	mfspr %0, %1;\n"
		"	cmpwi %0,0;\n"
		"	beq-  90b;\n"
	: "=r" (rval)
	: "i" (SPRN_TBRL));

	return rval;
}
#else
static inline unsigned long long get_cpu_clock(void)
{
	unsigned int tbl, tbu0, tbu1;
	unsigned long long ret;

	do {
		if (arch_flags & ARCH_FLAG_1) {
			tbu0 = mfspr(SPRN_ATBU);
			tbl = mfspr(SPRN_ATBL);
			tbu1 = mfspr(SPRN_ATBU);
		} else {
			tbu0 = mfspr(SPRN_TBRU);
			tbl = mfspr(SPRN_TBRL);
			tbu1 = mfspr(SPRN_TBRU);
		}
	} while (tbu0 != tbu1);

	ret = (((unsigned long long)tbu0) << 32) | tbl;
	return ret;
}
#endif

#if 0
static void atb_child(void)
{
	arch_flags |= ARCH_FLAG_1;
	get_cpu_clock();
	_exit(0);
}

static void atb_clocktest(void)
{
	pid_t pid;

	pid = fork();
	if (!pid)
		atb_child();
	else if (pid != -1) {
		int status;

		pid = wait(&status);
		if (pid == -1 || !WIFEXITED(status))
			arch_flags &= ~ARCH_FLAG_1;
		else
			arch_flags |= ARCH_FLAG_1;
	}
}
#endif

#define ARCH_HAVE_INIT
extern int tsc_reliable;

static inline int arch_init(char *envp[])
{
#if 0
	tsc_reliable = 1;
	atb_clocktest();
#endif
	return 0;
}

#define ARCH_HAVE_FFZ

/*
 * We don't have it on all platforms, lets comment this out until we
 * can handle it more intelligently.
 *
 * #define ARCH_HAVE_CPU_CLOCK
 */

/*
 * Let's have it defined for ppc64
 */

#ifdef __powerpc64__
#define ARCH_HAVE_CPU_CLOCK
#endif

#endif
Commit	Line	Data
	1	#ifndef ARCH_PPC_H
	2	#define ARCH_PPC_H
	3
	4	#include <unistd.h>
	5	#include <stdlib.h>
	6	#include <sys/types.h>
	7	#include <sys/wait.h>
	8
	9	#define FIO_ARCH (arch_ppc)
	10
	11	#ifndef __NR_ioprio_set
	12	#define __NR_ioprio_set 273
	13	#define __NR_ioprio_get 274
	14	#endif
	15
	16	#ifndef __NR_fadvise64
	17	#define __NR_fadvise64 233
	18	#endif
	19
	20	#ifndef __NR_sys_splice
	21	#define __NR_sys_splice 283
	22	#define __NR_sys_tee 284
	23	#define __NR_sys_vmsplice 285
	24	#endif
	25
	26	#define nop do { } while (0)
	27
	28	#ifdef __powerpc64__
	29	#define read_barrier() __asm__ __volatile__ ("lwsync" : : : "memory")
	30	#else
	31	#define read_barrier() __asm__ __volatile__ ("sync" : : : "memory")
	32	#endif
	33
	34	#define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
	35
	36	#ifdef __powerpc64__
	37	#define PPC_CNTLZL "cntlzd"
	38	#else
	39	#define PPC_CNTLZL "cntlzw"
	40	#endif
	41
	42	static inline int __ilog2(unsigned long bitmask)
	43	{
	44	int lz;
	45
	46	asm (PPC_CNTLZL " %0,%1" : "=r" (lz) : "r" (bitmask));
	47	return BITS_PER_LONG - 1 - lz;
	48	}
	49
	50	static inline int arch_ffz(unsigned long bitmask)
	51	{
	52	if ((bitmask = ~bitmask) == 0)
	53	return BITS_PER_LONG;
	54	return __ilog2(bitmask & -bitmask);
	55	}
	56
	57	static inline unsigned int mfspr(unsigned int reg)
	58	{
	59	unsigned int val;
	60
	61	asm volatile("mfspr %0,%1": "=r" (val) : "K" (reg));
	62	return val;
	63	}
	64
	65	#define SPRN_TBRL 0x10C /* Time Base Register Lower */
	66	#define SPRN_TBRU 0x10D /* Time Base Register Upper */
	67	#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
	68	#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
	69
	70	#ifdef __powerpc64__
	71	static inline unsigned long long get_cpu_clock(void)
	72	{
	73	unsigned long long rval;
	74
	75	asm volatile(
	76	"90: mfspr %0, %1;\n"
	77	" cmpwi %0,0;\n"
	78	" beq- 90b;\n"
	79	: "=r" (rval)
	80	: "i" (SPRN_TBRL));
	81
	82	return rval;
	83	}
	84	#else
	85	static inline unsigned long long get_cpu_clock(void)
	86	{
	87	unsigned int tbl, tbu0, tbu1;
	88	unsigned long long ret;
	89
	90	do {
	91	if (arch_flags & ARCH_FLAG_1) {
	92	tbu0 = mfspr(SPRN_ATBU);
	93	tbl = mfspr(SPRN_ATBL);
	94	tbu1 = mfspr(SPRN_ATBU);
	95	} else {
	96	tbu0 = mfspr(SPRN_TBRU);
	97	tbl = mfspr(SPRN_TBRL);
	98	tbu1 = mfspr(SPRN_TBRU);
	99	}
	100	} while (tbu0 != tbu1);
	101
	102	ret = (((unsigned long long)tbu0) << 32) \| tbl;
	103	return ret;
	104	}
	105	#endif
	106
	107	#if 0
	108	static void atb_child(void)
	109	{
	110	arch_flags \|= ARCH_FLAG_1;
	111	get_cpu_clock();
	112	_exit(0);
	113	}
	114
	115	static void atb_clocktest(void)
	116	{
	117	pid_t pid;
	118
	119	pid = fork();
	120	if (!pid)
	121	atb_child();
	122	else if (pid != -1) {
	123	int status;
	124
	125	pid = wait(&status);
	126	if (pid == -1 \|\| !WIFEXITED(status))
	127	arch_flags &= ~ARCH_FLAG_1;
	128	else
	129	arch_flags \|= ARCH_FLAG_1;
	130	}
	131	}
	132	#endif
	133
	134	#define ARCH_HAVE_INIT
	135	extern int tsc_reliable;
	136
	137	static inline int arch_init(char *envp[])
	138	{
	139	#if 0
	140	tsc_reliable = 1;
	141	atb_clocktest();
	142	#endif
	143	return 0;
	144	}
	145
	146	#define ARCH_HAVE_FFZ
	147
	148	/*
	149	* We don't have it on all platforms, lets comment this out until we
	150	* can handle it more intelligently.
	151	*
	152	* #define ARCH_HAVE_CPU_CLOCK
	153	*/
	154
	155	/*
	156	* Let's have it defined for ppc64
	157	*/
	158
	159	#ifdef __powerpc64__
	160	#define ARCH_HAVE_CPU_CLOCK
	161	#endif
	162
	163	#endif