[fio.git] / engines / nvme.h

/*
 * nvme structure declarations and helper functions for the
 * io_uring_cmd engine.
 */

#ifndef FIO_NVME_H
#define FIO_NVME_H

#include <linux/nvme_ioctl.h>
#include "../fio.h"

/*
 * If the uapi headers installed on the system lacks nvme uring command
 * support, use the local version to prevent compilation issues.
 */
#ifndef CONFIG_NVME_URING_CMD
struct nvme_uring_cmd {
	__u8	opcode;
	__u8	flags;
	__u16	rsvd1;
	__u32	nsid;
	__u32	cdw2;
	__u32	cdw3;
	__u64	metadata;
	__u64	addr;
	__u32	metadata_len;
	__u32	data_len;
	__u32	cdw10;
	__u32	cdw11;
	__u32	cdw12;
	__u32	cdw13;
	__u32	cdw14;
	__u32	cdw15;
	__u32	timeout_ms;
	__u32   rsvd2;
};

#define NVME_URING_CMD_IO	_IOWR('N', 0x80, struct nvme_uring_cmd)
#define NVME_URING_CMD_IO_VEC	_IOWR('N', 0x81, struct nvme_uring_cmd)
#endif /* CONFIG_NVME_URING_CMD */

#define NVME_DEFAULT_IOCTL_TIMEOUT 0
#define NVME_IDENTIFY_DATA_SIZE 4096
#define NVME_IDENTIFY_CSI_SHIFT 24
#define NVME_NQN_LENGTH	256

#define NVME_PI_APP_DISABLE 0xFFFF
#define NVME_PI_REF_DISABLE 0xFFFFFFFF

#define NVME_ZNS_ZRA_REPORT_ZONES 0
#define NVME_ZNS_ZRAS_FEAT_ERZ (1 << 16)
#define NVME_ZNS_ZSA_RESET 0x4
#define NVME_ZONE_TYPE_SEQWRITE_REQ 0x2

#define NVME_ATTRIBUTE_DEALLOCATE (1 << 2)

enum nvme_identify_cns {
	NVME_IDENTIFY_CNS_NS		= 0x00,
	NVME_IDENTIFY_CNS_CTRL		= 0x01,
	NVME_IDENTIFY_CNS_CSI_NS	= 0x05,
	NVME_IDENTIFY_CNS_CSI_CTRL	= 0x06,
};

enum nvme_csi {
	NVME_CSI_NVM			= 0,
	NVME_CSI_KV			= 1,
	NVME_CSI_ZNS			= 2,
};

enum nvme_admin_opcode {
	nvme_admin_identify		= 0x06,
};

enum nvme_io_opcode {
	nvme_cmd_write			= 0x01,
	nvme_cmd_read			= 0x02,
	nvme_cmd_dsm			= 0x09,
	nvme_cmd_io_mgmt_recv		= 0x12,
	nvme_zns_cmd_mgmt_send		= 0x79,
	nvme_zns_cmd_mgmt_recv		= 0x7a,
};

enum nvme_zns_zs {
	NVME_ZNS_ZS_EMPTY		= 0x1,
	NVME_ZNS_ZS_IMPL_OPEN		= 0x2,
	NVME_ZNS_ZS_EXPL_OPEN		= 0x3,
	NVME_ZNS_ZS_CLOSED		= 0x4,
	NVME_ZNS_ZS_READ_ONLY		= 0xd,
	NVME_ZNS_ZS_FULL		= 0xe,
	NVME_ZNS_ZS_OFFLINE		= 0xf,
};

enum nvme_id_ctrl_ctratt {
	NVME_CTRL_CTRATT_ELBAS		= 1 << 15,
};

enum {
	NVME_ID_NS_NVM_STS_MASK		= 0x7f,
	NVME_ID_NS_NVM_GUARD_SHIFT	= 7,
	NVME_ID_NS_NVM_GUARD_MASK	= 0x3,
};

enum {
	NVME_NVM_NS_16B_GUARD		= 0,
	NVME_NVM_NS_32B_GUARD		= 1,
	NVME_NVM_NS_64B_GUARD		= 2,
};

struct nvme_data {
	__u32 nsid;
	__u32 lba_shift;
	__u32 lba_size;
	__u32 lba_ext;
	__u16 ms;
	__u16 pi_size;
	__u8 pi_type;
	__u8 guard_type;
	__u8 pi_loc;
};

enum nvme_id_ns_dps {
	NVME_NS_DPS_PI_NONE		= 0,
	NVME_NS_DPS_PI_TYPE1		= 1,
	NVME_NS_DPS_PI_TYPE2		= 2,
	NVME_NS_DPS_PI_TYPE3		= 3,
	NVME_NS_DPS_PI_MASK		= 7 << 0,
	NVME_NS_DPS_PI_FIRST		= 1 << 3,
};

enum nvme_io_control_flags {
	NVME_IO_PRINFO_PRCHK_REF	= 1U << 26,
	NVME_IO_PRINFO_PRCHK_APP	= 1U << 27,
	NVME_IO_PRINFO_PRCHK_GUARD	= 1U << 28,
	NVME_IO_PRINFO_PRACT		= 1U << 29,
};

struct nvme_pi_data {
	__u32 interval;
	__u32 io_flags;
	__u16 apptag;
	__u16 apptag_mask;
};

struct nvme_lbaf {
	__le16			ms;
	__u8			ds;
	__u8			rp;
};

/* 16 bit guard protection Information format */
struct nvme_16b_guard_pif {
	__be16 guard;
	__be16 apptag;
	__be32 srtag;
};

/* 64 bit guard protection Information format */
struct nvme_64b_guard_pif {
	__be64 guard;
	__be16 apptag;
	__u8 srtag[6];
};

struct nvme_id_ns {
	__le64			nsze;
	__le64			ncap;
	__le64			nuse;
	__u8			nsfeat;
	__u8			nlbaf;
	__u8			flbas;
	__u8			mc;
	__u8			dpc;
	__u8			dps;
	__u8			nmic;
	__u8			rescap;
	__u8			fpi;
	__u8			dlfeat;
	__le16			nawun;
	__le16			nawupf;
	__le16			nacwu;
	__le16			nabsn;
	__le16			nabo;
	__le16			nabspf;
	__le16			noiob;
	__u8			nvmcap[16];
	__le16			npwg;
	__le16			npwa;
	__le16			npdg;
	__le16			npda;
	__le16			nows;
	__le16			mssrl;
	__le32			mcl;
	__u8			msrc;
	__u8			rsvd81[11];
	__le32			anagrpid;
	__u8			rsvd96[3];
	__u8			nsattr;
	__le16			nvmsetid;
	__le16			endgid;
	__u8			nguid[16];
	__u8			eui64[8];
	struct nvme_lbaf	lbaf[64];
	__u8			vs[3712];
};

struct nvme_id_psd {
	__le16			mp;
	__u8			rsvd2;
	__u8			flags;
	__le32			enlat;
	__le32			exlat;
	__u8			rrt;
	__u8			rrl;
	__u8			rwt;
	__u8			rwl;
	__le16			idlp;
	__u8			ips;
	__u8			rsvd19;
	__le16			actp;
	__u8			apws;
	__u8			rsvd23[9];
};

struct nvme_id_ctrl {
	__le16			vid;
	__le16			ssvid;
	char			sn[20];
	char			mn[40];
	char			fr[8];
	__u8			rab;
	__u8			ieee[3];
	__u8			cmic;
	__u8			mdts;
	__le16			cntlid;
	__le32			ver;
	__le32			rtd3r;
	__le32			rtd3e;
	__le32			oaes;
	__le32			ctratt;
	__le16			rrls;
	__u8			rsvd102[9];
	__u8			cntrltype;
	__u8			fguid[16];
	__le16			crdt1;
	__le16			crdt2;
	__le16			crdt3;
	__u8			rsvd134[119];
	__u8			nvmsr;
	__u8			vwci;
	__u8			mec;
	__le16			oacs;
	__u8			acl;
	__u8			aerl;
	__u8			frmw;
	__u8			lpa;
	__u8			elpe;
	__u8			npss;
	__u8			avscc;
	__u8			apsta;
	__le16			wctemp;
	__le16			cctemp;
	__le16			mtfa;
	__le32			hmpre;
	__le32			hmmin;
	__u8			tnvmcap[16];
	__u8			unvmcap[16];
	__le32			rpmbs;
	__le16			edstt;
	__u8			dsto;
	__u8			fwug;
	__le16			kas;
	__le16			hctma;
	__le16			mntmt;
	__le16			mxtmt;
	__le32			sanicap;
	__le32			hmminds;
	__le16			hmmaxd;
	__le16			nsetidmax;
	__le16			endgidmax;
	__u8			anatt;
	__u8			anacap;
	__le32			anagrpmax;
	__le32			nanagrpid;
	__le32			pels;
	__le16			domainid;
	__u8			rsvd358[10];
	__u8			megcap[16];
	__u8			rsvd384[128];
	__u8			sqes;
	__u8			cqes;
	__le16			maxcmd;
	__le32			nn;
	__le16			oncs;
	__le16			fuses;
	__u8			fna;
	__u8			vwc;
	__le16			awun;
	__le16			awupf;
	__u8			icsvscc;
	__u8			nwpc;
	__le16			acwu;
	__le16			ocfs;
	__le32			sgls;
	__le32			mnan;
	__u8			maxdna[16];
	__le32			maxcna;
	__u8			rsvd564[204];
	char			subnqn[NVME_NQN_LENGTH];
	__u8			rsvd1024[768];

	/* Fabrics Only */
	__le32			ioccsz;
	__le32			iorcsz;
	__le16			icdoff;
	__u8			fcatt;
	__u8			msdbd;
	__le16			ofcs;
	__u8			dctype;
	__u8			rsvd1807[241];

	struct nvme_id_psd	psd[32];
	__u8			vs[1024];
};

struct nvme_nvm_id_ns {
	__le64			lbstm;
	__u8			pic;
	__u8			rsvd9[3];
	__le32			elbaf[64];
	__u8			rsvd268[3828];
};

static inline int ilog2(uint32_t i)
{
	int log = -1;

	while (i) {
		i >>= 1;
		log++;
	}
	return log;
}

struct nvme_zns_lbafe {
	__le64	zsze;
	__u8	zdes;
	__u8	rsvd9[7];
};

struct nvme_zns_id_ns {
	__le16			zoc;
	__le16			ozcs;
	__le32			mar;
	__le32			mor;
	__le32			rrl;
	__le32			frl;
	__le32			rrl1;
	__le32			rrl2;
	__le32			rrl3;
	__le32			frl1;
	__le32			frl2;
	__le32			frl3;
	__le32			numzrwa;
	__le16			zrwafg;
	__le16			zrwasz;
	__u8			zrwacap;
	__u8			rsvd53[2763];
	struct nvme_zns_lbafe	lbafe[64];
	__u8			vs[256];
};

struct nvme_zns_desc {
	__u8	zt;
	__u8	zs;
	__u8	za;
	__u8	zai;
	__u8	rsvd4[4];
	__le64	zcap;
	__le64	zslba;
	__le64	wp;
	__u8	rsvd32[32];
};

struct nvme_zone_report {
	__le64			nr_zones;
	__u8			rsvd8[56];
	struct nvme_zns_desc	entries[];
};

struct nvme_fdp_ruh_status_desc {
	__u16 pid;
	__u16 ruhid;
	__u32 earutr;
	__u64 ruamw;
	__u8  rsvd16[16];
};

struct nvme_fdp_ruh_status {
	__u8  rsvd0[14];
	__le16 nruhsd;
	struct nvme_fdp_ruh_status_desc ruhss[];
};

struct nvme_dsm_range {
	__le32	cattr;
	__le32	nlb;
	__le64	slba;
};

struct nvme_cmd_ext_io_opts {
	__u32 io_flags;
	__u16 apptag;
	__u16 apptag_mask;
};

int fio_nvme_iomgmt_ruhs(struct thread_data *td, struct fio_file *f,
			 struct nvme_fdp_ruh_status *ruhs, __u32 bytes);

int fio_nvme_get_info(struct fio_file *f, __u64 *nlba, __u32 pi_act,
		      struct nvme_data *data);

int fio_nvme_uring_cmd_prep(struct nvme_uring_cmd *cmd, struct io_u *io_u,
			    struct iovec *iov, struct nvme_dsm_range *dsm);

void fio_nvme_pi_fill(struct nvme_uring_cmd *cmd, struct io_u *io_u,
		      struct nvme_cmd_ext_io_opts *opts);

int fio_nvme_pi_verify(struct nvme_data *data, struct io_u *io_u);

int fio_nvme_get_zoned_model(struct thread_data *td, struct fio_file *f,
			     enum zbd_zoned_model *model);

int fio_nvme_report_zones(struct thread_data *td, struct fio_file *f,
			  uint64_t offset, struct zbd_zone *zbdz,
			  unsigned int nr_zones);

int fio_nvme_reset_wp(struct thread_data *td, struct fio_file *f,
		      uint64_t offset, uint64_t length);

int fio_nvme_get_max_open_zones(struct thread_data *td, struct fio_file *f,
				unsigned int *max_open_zones);

#endif
Commit	Line	Data
b3d5e3fd AK	1	/*
	2	* nvme structure declarations and helper functions for the
	3	* io_uring_cmd engine.
	4	*/
	5
	6	#ifndef FIO_NVME_H
	7	#define FIO_NVME_H
	8
	9	#include <linux/nvme_ioctl.h>
	10	#include "../fio.h"
	11
	12	/*
	13	* If the uapi headers installed on the system lacks nvme uring command
	14	* support, use the local version to prevent compilation issues.
	15	*/
	16	#ifndef CONFIG_NVME_URING_CMD
	17	struct nvme_uring_cmd {
	18	__u8 opcode;
	19	__u8 flags;
	20	__u16 rsvd1;
	21	__u32 nsid;
	22	__u32 cdw2;
	23	__u32 cdw3;
	24	__u64 metadata;
	25	__u64 addr;
	26	__u32 metadata_len;
	27	__u32 data_len;
	28	__u32 cdw10;
	29	__u32 cdw11;
	30	__u32 cdw12;
	31	__u32 cdw13;
	32	__u32 cdw14;
	33	__u32 cdw15;
	34	__u32 timeout_ms;
	35	__u32 rsvd2;
	36	};
	37
	38	#define NVME_URING_CMD_IO _IOWR('N', 0x80, struct nvme_uring_cmd)
	39	#define NVME_URING_CMD_IO_VEC _IOWR('N', 0x81, struct nvme_uring_cmd)
	40	#endif /* CONFIG_NVME_URING_CMD */
	41
	42	#define NVME_DEFAULT_IOCTL_TIMEOUT 0
	43	#define NVME_IDENTIFY_DATA_SIZE 4096
	44	#define NVME_IDENTIFY_CSI_SHIFT 24
3ee8311a	45	#define NVME_NQN_LENGTH 256
b3d5e3fd	46
5163f35e AK	47	#define NVME_PI_APP_DISABLE 0xFFFF
	48	#define NVME_PI_REF_DISABLE 0xFFFFFFFF
	49
3d05e0ff AK	50	#define NVME_ZNS_ZRA_REPORT_ZONES 0
	51	#define NVME_ZNS_ZRAS_FEAT_ERZ (1 << 16)
	52	#define NVME_ZNS_ZSA_RESET 0x4
	53	#define NVME_ZONE_TYPE_SEQWRITE_REQ 0x2
	54
16be6037 AK	55	#define NVME_ATTRIBUTE_DEALLOCATE (1 << 2)
16be6037 AK	56
b3d5e3fd	57	enum nvme_identify_cns {
3d05e0ff	58	NVME_IDENTIFY_CNS_NS = 0x00,
3ee8311a	59	NVME_IDENTIFY_CNS_CTRL = 0x01,
3d05e0ff AK	60	NVME_IDENTIFY_CNS_CSI_NS = 0x05,
3d05e0ff AK	61	NVME_IDENTIFY_CNS_CSI_CTRL = 0x06,
b3d5e3fd AK	62	};
	63
	64	enum nvme_csi {
	65	NVME_CSI_NVM = 0,
	66	NVME_CSI_KV = 1,
	67	NVME_CSI_ZNS = 2,
	68	};
	69
	70	enum nvme_admin_opcode {
	71	nvme_admin_identify = 0x06,
	72	};
	73
	74	enum nvme_io_opcode {
	75	nvme_cmd_write = 0x01,
	76	nvme_cmd_read = 0x02,
16be6037	77	nvme_cmd_dsm = 0x09,
a7e8aae0	78	nvme_cmd_io_mgmt_recv = 0x12,
3d05e0ff AK	79	nvme_zns_cmd_mgmt_send = 0x79,
	80	nvme_zns_cmd_mgmt_recv = 0x7a,
	81	};
	82
	83	enum nvme_zns_zs {
	84	NVME_ZNS_ZS_EMPTY = 0x1,
	85	NVME_ZNS_ZS_IMPL_OPEN = 0x2,
	86	NVME_ZNS_ZS_EXPL_OPEN = 0x3,
	87	NVME_ZNS_ZS_CLOSED = 0x4,
	88	NVME_ZNS_ZS_READ_ONLY = 0xd,
	89	NVME_ZNS_ZS_FULL = 0xe,
	90	NVME_ZNS_ZS_OFFLINE = 0xf,
b3d5e3fd AK	91	};
b3d5e3fd AK	92
3ee8311a AK	93	enum nvme_id_ctrl_ctratt {
	94	NVME_CTRL_CTRATT_ELBAS = 1 << 15,
	95	};
	96
	97	enum {
	98	NVME_ID_NS_NVM_STS_MASK = 0x7f,
	99	NVME_ID_NS_NVM_GUARD_SHIFT = 7,
	100	NVME_ID_NS_NVM_GUARD_MASK = 0x3,
	101	};
	102
	103	enum {
	104	NVME_NVM_NS_16B_GUARD = 0,
	105	NVME_NVM_NS_32B_GUARD = 1,
	106	NVME_NVM_NS_64B_GUARD = 2,
	107	};
	108
b3d5e3fd AK	109	struct nvme_data {
	110	__u32 nsid;
	111	__u32 lba_shift;
e7e5023b	112	__u32 lba_size;
345fa8fd	113	__u32 lba_ext;
e7e5023b	114	__u16 ms;
3ee8311a AK	115	__u16 pi_size;
	116	__u8 pi_type;
	117	__u8 guard_type;
	118	__u8 pi_loc;
	119	};
	120
	121	enum nvme_id_ns_dps {
	122	NVME_NS_DPS_PI_NONE = 0,
	123	NVME_NS_DPS_PI_TYPE1 = 1,
	124	NVME_NS_DPS_PI_TYPE2 = 2,
	125	NVME_NS_DPS_PI_TYPE3 = 3,
	126	NVME_NS_DPS_PI_MASK = 7 << 0,
	127	NVME_NS_DPS_PI_FIRST = 1 << 3,
	128	};
	129
	130	enum nvme_io_control_flags {
	131	NVME_IO_PRINFO_PRCHK_REF = 1U << 26,
	132	NVME_IO_PRINFO_PRCHK_APP = 1U << 27,
	133	NVME_IO_PRINFO_PRCHK_GUARD = 1U << 28,
	134	NVME_IO_PRINFO_PRACT = 1U << 29,
b3d5e3fd AK	135	};
b3d5e3fd AK	136
5163f35e AK	137	struct nvme_pi_data {
	138	__u32 interval;
	139	__u32 io_flags;
	140	__u16 apptag;
	141	__u16 apptag_mask;
	142	};
	143
b3d5e3fd AK	144	struct nvme_lbaf {
	145	__le16 ms;
	146	__u8 ds;
	147	__u8 rp;
	148	};
	149
3ee8311a AK	150	/* 16 bit guard protection Information format */
	151	struct nvme_16b_guard_pif {
	152	__be16 guard;
	153	__be16 apptag;
	154	__be32 srtag;
	155	};
	156
	157	/* 64 bit guard protection Information format */
	158	struct nvme_64b_guard_pif {
	159	__be64 guard;
	160	__be16 apptag;
	161	__u8 srtag[6];
	162	};
	163
b3d5e3fd AK	164	struct nvme_id_ns {
	165	__le64 nsze;
	166	__le64 ncap;
	167	__le64 nuse;
	168	__u8 nsfeat;
	169	__u8 nlbaf;
	170	__u8 flbas;
	171	__u8 mc;
	172	__u8 dpc;
	173	__u8 dps;
	174	__u8 nmic;
	175	__u8 rescap;
	176	__u8 fpi;
	177	__u8 dlfeat;
	178	__le16 nawun;
	179	__le16 nawupf;
	180	__le16 nacwu;
	181	__le16 nabsn;
	182	__le16 nabo;
	183	__le16 nabspf;
	184	__le16 noiob;
	185	__u8 nvmcap[16];
	186	__le16 npwg;
	187	__le16 npwa;
	188	__le16 npdg;
	189	__le16 npda;
	190	__le16 nows;
	191	__le16 mssrl;
	192	__le32 mcl;
	193	__u8 msrc;
	194	__u8 rsvd81[11];
	195	__le32 anagrpid;
	196	__u8 rsvd96[3];
	197	__u8 nsattr;
	198	__le16 nvmsetid;
	199	__le16 endgid;
	200	__u8 nguid[16];
	201	__u8 eui64[8];
01a7d384	202	struct nvme_lbaf lbaf[64];
b3d5e3fd AK	203	__u8 vs[3712];
	204	};
	205
3ee8311a AK	206	struct nvme_id_psd {
	207	__le16 mp;
	208	__u8 rsvd2;
	209	__u8 flags;
	210	__le32 enlat;
	211	__le32 exlat;
	212	__u8 rrt;
	213	__u8 rrl;
	214	__u8 rwt;
	215	__u8 rwl;
	216	__le16 idlp;
	217	__u8 ips;
	218	__u8 rsvd19;
	219	__le16 actp;
	220	__u8 apws;
	221	__u8 rsvd23[9];
	222	};
	223
	224	struct nvme_id_ctrl {
	225	__le16 vid;
	226	__le16 ssvid;
	227	char sn[20];
	228	char mn[40];
	229	char fr[8];
	230	__u8 rab;
	231	__u8 ieee[3];
	232	__u8 cmic;
	233	__u8 mdts;
	234	__le16 cntlid;
	235	__le32 ver;
	236	__le32 rtd3r;
	237	__le32 rtd3e;
	238	__le32 oaes;
	239	__le32 ctratt;
	240	__le16 rrls;
	241	__u8 rsvd102[9];
	242	__u8 cntrltype;
	243	__u8 fguid[16];
	244	__le16 crdt1;
	245	__le16 crdt2;
	246	__le16 crdt3;
	247	__u8 rsvd134[119];
	248	__u8 nvmsr;
	249	__u8 vwci;
	250	__u8 mec;
	251	__le16 oacs;
	252	__u8 acl;
	253	__u8 aerl;
	254	__u8 frmw;
	255	__u8 lpa;
	256	__u8 elpe;
	257	__u8 npss;
	258	__u8 avscc;
	259	__u8 apsta;
	260	__le16 wctemp;
	261	__le16 cctemp;
	262	__le16 mtfa;
	263	__le32 hmpre;
	264	__le32 hmmin;
	265	__u8 tnvmcap[16];
	266	__u8 unvmcap[16];
	267	__le32 rpmbs;
	268	__le16 edstt;
	269	__u8 dsto;
270	__u8 fwug;
271	__le16 kas;
272	__le16 hctma;
273	__le16 mntmt;
274	__le16 mxtmt;
275	__le32 sanicap;
276	__le32 hmminds;
277	__le16 hmmaxd;
278	__le16 nsetidmax;
279	__le16 endgidmax;
280	__u8 anatt;
281	__u8 anacap;
282	__le32 anagrpmax;
283	__le32 nanagrpid;
284	__le32 pels;
285	__le16 domainid;
286	__u8 rsvd358[10];
287	__u8 megcap[16];
288	__u8 rsvd384[128];
289	__u8 sqes;
290	__u8 cqes;
291	__le16 maxcmd;
292	__le32 nn;
293	__le16 oncs;
294	__le16 fuses;
295	__u8 fna;
296	__u8 vwc;
297	__le16 awun;
298	__le16 awupf;
299	__u8 icsvscc;
300	__u8 nwpc;
301	__le16 acwu;
302	__le16 ocfs;
303	__le32 sgls;
304	__le32 mnan;
305	__u8 maxdna[16];
306	__le32 maxcna;
307	__u8 rsvd564[204];
308	char subnqn[NVME_NQN_LENGTH];
309	__u8 rsvd1024[768];
310
311	/* Fabrics Only */
312	__le32 ioccsz;
313	__le32 iorcsz;
314	__le16 icdoff;
315	__u8 fcatt;
316	__u8 msdbd;
317	__le16 ofcs;
318	__u8 dctype;
319	__u8 rsvd1807[241];
320
321	struct nvme_id_psd psd[32];
322	__u8 vs[1024];
323	};
324
325	struct nvme_nvm_id_ns {
326	__le64 lbstm;
327	__u8 pic;
328	__u8 rsvd9[3];
329	__le32 elbaf[64];
330	__u8 rsvd268[3828];
331	};
332
b3d5e3fd AK	333	static inline int ilog2(uint32_t i)
	334	{
	335	int log = -1;
	336
	337	while (i) {
	338	i >>= 1;
	339	log++;
	340	}
	341	return log;
	342	}
	343
3d05e0ff AK	344	struct nvme_zns_lbafe {
	345	__le64 zsze;
	346	__u8 zdes;
	347	__u8 rsvd9[7];
	348	};
	349
	350	struct nvme_zns_id_ns {
	351	__le16 zoc;
	352	__le16 ozcs;
	353	__le32 mar;
	354	__le32 mor;
	355	__le32 rrl;
	356	__le32 frl;
	357	__le32 rrl1;
	358	__le32 rrl2;
	359	__le32 rrl3;
	360	__le32 frl1;
	361	__le32 frl2;
	362	__le32 frl3;
	363	__le32 numzrwa;
	364	__le16 zrwafg;
	365	__le16 zrwasz;
	366	__u8 zrwacap;
	367	__u8 rsvd53[2763];
	368	struct nvme_zns_lbafe lbafe[64];
	369	__u8 vs[256];
	370	};
	371
	372	struct nvme_zns_desc {
	373	__u8 zt;
	374	__u8 zs;
	375	__u8 za;
	376	__u8 zai;
	377	__u8 rsvd4[4];
	378	__le64 zcap;
	379	__le64 zslba;
	380	__le64 wp;
	381	__u8 rsvd32[32];
	382	};
	383
	384	struct nvme_zone_report {
	385	__le64 nr_zones;
	386	__u8 rsvd8[56];
	387	struct nvme_zns_desc entries[];
	388	};
	389
a7e8aae0 KB	390	struct nvme_fdp_ruh_status_desc {
	391	__u16 pid;
	392	__u16 ruhid;
	393	__u32 earutr;
	394	__u64 ruamw;
	395	__u8 rsvd16[16];
	396	};
	397
	398	struct nvme_fdp_ruh_status {
	399	__u8 rsvd0[14];
	400	__le16 nruhsd;
	401	struct nvme_fdp_ruh_status_desc ruhss[];
	402	};
	403
16be6037 AK	404	struct nvme_dsm_range {
	405	__le32 cattr;
	406	__le32 nlb;
	407	__le64 slba;
	408	};
	409
3ee8311a AK	410	struct nvme_cmd_ext_io_opts {
	411	__u32 io_flags;
	412	__u16 apptag;
	413	__u16 apptag_mask;
	414	};
	415
a7e8aae0 KB	416	int fio_nvme_iomgmt_ruhs(struct thread_data td, struct fio_file f,
	417	struct nvme_fdp_ruh_status *ruhs, __u32 bytes);
	418
3ee8311a AK	419	int fio_nvme_get_info(struct fio_file f, __u64 nlba, __u32 pi_act,
3ee8311a AK	420	struct nvme_data *data);
b3d5e3fd AK	421
b3d5e3fd AK	422	int fio_nvme_uring_cmd_prep(struct nvme_uring_cmd cmd, struct io_u io_u,
4885a6eb	423	struct iovec iov, struct nvme_dsm_range dsm);
b3d5e3fd	424
3ee8311a AK	425	void fio_nvme_pi_fill(struct nvme_uring_cmd cmd, struct io_u io_u,
	426	struct nvme_cmd_ext_io_opts *opts);
	427
5163f35e AK	428	int fio_nvme_pi_verify(struct nvme_data data, struct io_u io_u);
5163f35e AK	429
3d05e0ff AK	430	int fio_nvme_get_zoned_model(struct thread_data td, struct fio_file f,
	431	enum zbd_zoned_model *model);
	432
	433	int fio_nvme_report_zones(struct thread_data td, struct fio_file f,
	434	uint64_t offset, struct zbd_zone *zbdz,
	435	unsigned int nr_zones);
	436
	437	int fio_nvme_reset_wp(struct thread_data td, struct fio_file f,
	438	uint64_t offset, uint64_t length);
	439
	440	int fio_nvme_get_max_open_zones(struct thread_data td, struct fio_file f,
	441	unsigned int *max_open_zones);
	442
b3d5e3fd	443	#endif