Commit | Line | Data |
---|---|---|
ebac4655 JA |
1 | #ifndef ARCH_IA64_H |
2 | #define ARCH_IA64_H | |
3 | ||
cca84643 | 4 | #define FIO_ARCH (arch_ia64) |
ebac4655 JA |
5 | |
6 | #ifndef __NR_ioprio_set | |
7 | #define __NR_ioprio_set 1274 | |
8 | #define __NR_ioprio_get 1275 | |
9 | #endif | |
10 | ||
11 | #ifndef __NR_fadvise64 | |
12 | #define __NR_fadvise64 1234 | |
13 | #endif | |
14 | ||
8756e4d4 JA |
15 | #ifndef __NR_sys_splice |
16 | #define __NR_sys_splice 1297 | |
17 | #define __NR_sys_tee 1301 | |
18 | #define __NR_sys_vmsplice 1302 | |
19 | #endif | |
20 | ||
43cf00fd JA |
21 | #ifndef __NR_preadv2 |
22 | #define __NR_preadv2 1348 | |
23 | #endif | |
24 | #ifndef __NR_pwritev2 | |
25 | #define __NR_pwritev2 1349 | |
26 | #endif | |
27 | ||
db6defc7 JA |
28 | #define nop asm volatile ("hint @pause" ::: "memory"); |
29 | #define read_barrier() asm volatile ("mf" ::: "memory") | |
783500ad | 30 | #define write_barrier() asm volatile ("mf" ::: "memory") |
ebac4655 | 31 | |
8f7e39dd JA |
32 | #define ia64_popcnt(x) \ |
33 | ({ \ | |
34 | unsigned long ia64_intri_res; \ | |
35 | asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \ | |
36 | ia64_intri_res; \ | |
37 | }) | |
38 | ||
39 | static inline unsigned long arch_ffz(unsigned long bitmask) | |
40 | { | |
41 | return ia64_popcnt(bitmask & (~bitmask - 1)); | |
42 | } | |
ab480047 | 43 | |
d93904c4 | 44 | static inline unsigned long long get_cpu_clock(void) |
ab480047 | 45 | { |
d93904c4 | 46 | unsigned long long ret; |
ab480047 JA |
47 | |
48 | __asm__ __volatile__("mov %0=ar.itc" : "=r" (ret) : : "memory"); | |
49 | return ret; | |
50 | } | |
51 | ||
1b745f55 JA |
52 | #define ARCH_HAVE_INIT |
53 | extern int tsc_reliable; | |
54 | static inline int arch_init(char *envp[]) | |
55 | { | |
56 | tsc_reliable = 1; | |
d20b2ca6 | 57 | return 0; |
1b745f55 JA |
58 | } |
59 | ||
8f7e39dd | 60 | #define ARCH_HAVE_FFZ |
ab480047 | 61 | #define ARCH_HAVE_CPU_CLOCK |
8f7e39dd | 62 | |
ebac4655 | 63 | #endif |