#define __NR_sys_vmsplice 343
#endif
+#ifndef __NR_preadv2
+#define __NR_preadv2 392
+#endif
+#ifndef __NR_pwritev2
+#define __NR_pwritev2 393
+#endif
+
#if defined (__ARM_ARCH_4__) || defined (__ARM_ARCH_4T__) \
|| defined (__ARM_ARCH_5__) || defined (__ARM_ARCH_5T__) || defined (__ARM_ARCH_5E__)\
|| defined (__ARM_ARCH_5TE__) || defined (__ARM_ARCH_5TEJ__) \
#define __NR_sys_vmsplice 1302
#endif
+#ifndef __NR_preadv2
+#define __NR_preadv2 1348
+#endif
+#ifndef __NR_pwritev2
+#define __NR_pwritev2 1349
+#endif
+
#define nop asm volatile ("hint @pause" ::: "memory");
#define read_barrier() asm volatile ("mf" ::: "memory")
#define write_barrier() asm volatile ("mf" ::: "memory")
#define __NR_sys_vmsplice 309
#endif
+#ifndef __NR_preadv2
+#define __NR_preadv2 376
+#endif
+#ifndef __NR_pwritev2
+#define __NR_pwritev2 377
+#endif
+
#define nop asm volatile("nop" : : : "memory")
#define read_barrier() asm volatile("bcr 15,0" : : : "memory")
#define write_barrier() asm volatile("bcr 15,0" : : : "memory")
#define __NR_sys_vmsplice 25
#endif
+#ifndef __NR_preadv2
+#define __NR_preadv2 358
+#endif
+#ifndef __NR_pwritev2
+#define __NR_pwritev2 359
+#endif
+
#define nop do { } while (0)
#define read_barrier() __asm__ __volatile__ ("" : : : "memory")
#define __NR_sys_vmsplice 25
#endif
+#ifndef __NR_preadv2
+#define __NR_preadv2 358
+#endif
+#ifndef __NR_pwritev2
+#define __NR_pwritev2 359
+#endif
+
#define nop do { } while (0)
#define membar_safe(type) \