Commit | Line | Data |
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ebac4655 JA |
1 | #ifndef ARCH_S390_H |
2 | #define ARCH_S390_H | |
3 | ||
cca84643 | 4 | #define FIO_ARCH (arch_s390) |
ebac4655 JA |
5 | |
6 | #ifndef __NR_ioprio_set | |
7 | #define __NR_ioprio_set 282 | |
8 | #define __NR_ioprio_get 283 | |
9 | #endif | |
10 | ||
11 | #ifndef __NR_fadvise64 | |
12 | #define __NR_fadvise64 253 | |
13 | #endif | |
14 | ||
9a9c63f1 JA |
15 | #ifndef __NR_sys_splice |
16 | #define __NR_sys_splice 306 | |
17 | #define __NR_sys_tee 308 | |
18 | #define __NR_sys_vmsplice 309 | |
19 | #endif | |
20 | ||
43cf00fd JA |
21 | #ifndef __NR_preadv2 |
22 | #define __NR_preadv2 376 | |
23 | #endif | |
24 | #ifndef __NR_pwritev2 | |
25 | #define __NR_pwritev2 377 | |
26 | #endif | |
27 | ||
1cffeb6f | 28 | #define nop asm volatile("nop" : : : "memory") |
db6defc7 | 29 | #define read_barrier() asm volatile("bcr 15,0" : : : "memory") |
44c47feb | 30 | #define write_barrier() asm volatile("bcr 15,0" : : : "memory") |
ebac4655 | 31 | |
15cf40b2 DH |
32 | static inline unsigned long long get_cpu_clock(void) |
33 | { | |
34 | unsigned long long clk; | |
35 | ||
81795ce3 CE |
36 | #ifdef CONFIG_S390_Z196_FACILITIES |
37 | /* | |
38 | * Fio needs monotonic (never lower), but not strict monotonic (never | |
39 | * the same) so store clock fast is enough. | |
40 | */ | |
919e789d | 41 | __asm__ __volatile__("stckf %0" : "=Q" (clk) : : "cc"); |
81795ce3 CE |
42 | #else |
43 | __asm__ __volatile__("stck %0" : "=Q" (clk) : : "cc"); | |
44 | #endif | |
919e789d | 45 | return clk>>12; |
15cf40b2 DH |
46 | } |
47 | ||
919e789d CE |
48 | #define ARCH_CPU_CLOCK_CYCLES_PER_USEC 1 |
49 | #define ARCH_HAVE_CPU_CLOCK | |
96170421 | 50 | #undef ARCH_CPU_CLOCK_WRAPS |
919e789d | 51 | |
15cf40b2 DH |
52 | #define ARCH_HAVE_INIT |
53 | extern int tsc_reliable; | |
54 | static inline int arch_init(char *envp[]) | |
55 | { | |
56 | tsc_reliable = 1; | |
57 | return 0; | |
58 | } | |
59 | ||
ebac4655 | 60 | #endif |