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hash: make 64-bit even on 32-bit
[fio.git]
/
arch
/
arch-ppc.h
diff --git
a/arch/arch-ppc.h
b/arch/arch-ppc.h
index 0cc0cbda7d69890e10ff41816d836b4189684963..161c39c511937c9a0d4604a69fa3f63da1825f26 100644
(file)
--- a/
arch/arch-ppc.h
+++ b/
arch/arch-ppc.h
@@
-1,5
+1,5
@@
#ifndef ARCH_PPC_H
#ifndef ARCH_PPC_H
-#define ARCH_PP
H
_H
+#define ARCH_PP
C
_H
#include <unistd.h>
#include <stdlib.h>
#include <unistd.h>
#include <stdlib.h>
@@
-33,18
+33,24
@@
#define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
#define write_barrier() __asm__ __volatile__ ("sync" : : : "memory")
+#ifdef __powerpc64__
+#define PPC_CNTLZL "cntlzd"
+#else
+#define PPC_CNTLZL "cntlzw"
+#endif
+
static inline int __ilog2(unsigned long bitmask)
{
int lz;
static inline int __ilog2(unsigned long bitmask)
{
int lz;
- asm (
"cntlzw
%0,%1" : "=r" (lz) : "r" (bitmask));
- return
3
1 - lz;
+ asm (
PPC_CNTLZL "
%0,%1" : "=r" (lz) : "r" (bitmask));
+ return
BITS_PER_LONG -
1 - lz;
}
static inline int arch_ffz(unsigned long bitmask)
{
if ((bitmask = ~bitmask) == 0)
}
static inline int arch_ffz(unsigned long bitmask)
{
if ((bitmask = ~bitmask) == 0)
- return
32
;
+ return
BITS_PER_LONG
;
return __ilog2(bitmask & -bitmask);
}
return __ilog2(bitmask & -bitmask);
}
@@
-61,6
+67,21
@@
static inline unsigned int mfspr(unsigned int reg)
#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
+#ifdef __powerpc64__
+static inline unsigned long long get_cpu_clock(void)
+{
+ unsigned long long rval;
+
+ asm volatile(
+ "90: mfspr %0, %1;\n"
+ " cmpwi %0,0;\n"
+ " beq- 90b;\n"
+ : "=r" (rval)
+ : "i" (SPRN_TBRL));
+
+ return rval;
+}
+#else
static inline unsigned long long get_cpu_clock(void)
{
unsigned int tbl, tbu0, tbu1;
static inline unsigned long long get_cpu_clock(void)
{
unsigned int tbl, tbu0, tbu1;
@@
-72,16
+93,18
@@
static inline unsigned long long get_cpu_clock(void)
tbl = mfspr(SPRN_ATBL);
tbu1 = mfspr(SPRN_ATBU);
} else {
tbl = mfspr(SPRN_ATBL);
tbu1 = mfspr(SPRN_ATBU);
} else {
-
__asm__ __volatile__("mftbu %0" : "=r"(tbu0)
);
-
__asm__ __volatile__("mftb %0" : "=r"(tbl)
);
-
__asm__ __volatile__("mftbu %0" : "=r"(tbu1)
);
+
tbu0 = mfspr(SPRN_TBRU
);
+
tbl = mfspr(SPRN_TBRL
);
+
tbu1 = mfspr(SPRN_TBRU
);
}
} while (tbu0 != tbu1);
ret = (((unsigned long long)tbu0) << 32) | tbl;
return ret;
}
}
} while (tbu0 != tbu1);
ret = (((unsigned long long)tbu0) << 32) | tbl;
return ret;
}
+#endif
+#if 0
static void atb_child(void)
{
arch_flags |= ARCH_FLAG_1;
static void atb_child(void)
{
arch_flags |= ARCH_FLAG_1;
@@
-106,18
+129,35
@@
static void atb_clocktest(void)
arch_flags |= ARCH_FLAG_1;
}
}
arch_flags |= ARCH_FLAG_1;
}
}
+#endif
#define ARCH_HAVE_INIT
extern int tsc_reliable;
static inline int arch_init(char *envp[])
{
#define ARCH_HAVE_INIT
extern int tsc_reliable;
static inline int arch_init(char *envp[])
{
+#if 0
tsc_reliable = 1;
atb_clocktest();
tsc_reliable = 1;
atb_clocktest();
+#endif
return 0;
}
#define ARCH_HAVE_FFZ
return 0;
}
#define ARCH_HAVE_FFZ
+
+/*
+ * We don't have it on all platforms, lets comment this out until we
+ * can handle it more intelligently.
+ *
+ * #define ARCH_HAVE_CPU_CLOCK
+ */
+
+/*
+ * Let's have it defined for ppc64
+ */
+
+#ifdef __powerpc64__
#define ARCH_HAVE_CPU_CLOCK
#define ARCH_HAVE_CPU_CLOCK
+#endif
#endif
#endif